¡ Semiconductor MSM6636 ¡ Semiconductor MSM6636 SAE-J1850 Communication Protocol Conformity Transmission Controller for Automotive LAN GENERAL DESCRIPTION The MSM6636 is a transmission controller for automotive LAN based on data communication protocol SAE-J1850. This LSI can realize a data bus topology bus LAN system with a PWM bit encoding method (41.6 K bps). In addition to a protocol control circuit, MSM6636 has an enclosed quartz oscillation circuit, host CPU interface (clock synchronous serial / UART), a transmit/ receive buffer, and a bus receiver circuit that decreases the burden on the host CPU. FEATURES • Based on SAE-J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE (issued August 12, 1991) • CSMA/CD (Carrier-sense multiple access with collision detection) • Internal transmit buffer (1 frame) and receive buffer (2 frames) • Bit encoding: PWM (Pulse Width Modulation) • Transmission Speed: 41.6K bps • Multi-address setting with physical addressing: 1 type / functional addressing: 15 types • Address filter function by multi-addressing (broadcasting possible) • Automatic retransmission function by arbitration loss and non ACK • 3 types of in-frame response support: q Single-byte response from a single recipient w Multi-byte response from a single recipient (with CRC code) e Single-byte response from multiple recipients (ID response as ACK) • Error detection by cyclic redundancy check (CRC) • Various communication error detections • Dual-wire bus abnormality detection by internal bus receiver and fault tolerance function • Host CPU interface is LSB first / serial, 4 modes supported q Clock synchronous serial (no parity) Normal mode: 8-bit data MPC Mode: 8-bit data + MPC bit (1: address / 0: data select bit) w UART (yes/no parity selectable) Normal mode: 1 start bit + 8-bit data + (parity) + 1 stop bit MPC mode: 1 start bit + 8-bit data + MPC bit + (parity) + 1 stop bit • Sleep Function Low current consumption mode by oscillation stop (IDS Max < 50µA) SLEEP / WAKE UP control from host CPU, WAKE UP via LAN bus • Available package 18pin DIP, 18 pin QFJ (PLCC) and 24pin SOP. 1 MSM6636 ¡ Semiconductor BLOCK DIAGRAM Buffer Register CPU Serial Interface Receive Register Receive Buffer Address Register LAN Controller S-P Converter CRC Checker Status Register x'tal Clock Generator Bus Receiver Address Filter Transmission Controller CRC Generator P-S Converter MSM6636 2 Degital Filter Receive Controller Transmission Register Response Register PWM Decoder LAN Bus Input PWM Encoder LAN Bus Output ¡ Semiconductor MSM6636 PIN CONFIGURATION (TOP VIEW) 18pin Plastic QFJ AVDD 1 1 8 DVDD BO– 1 7 RES 2 24pin Plastic SOP BO– AVDD DVDD RES 18pin Plastic DIP 1 2 18 17 BI– 3 1 6 INT BI– 3 16 INT BI+ 4 1 5 TXD BI+ 4 15 TXD 5 1 4 AGND 6 1 3 U-C 1 2 M-N 7 8 11 DGND 9 10 RXD SCLK /PAE A-D BO+ 5 14 AGND 6 13 U-C 7 12 RXD SCLK /PAE A-D OSC0 8 OSC1 9 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DVDD RES INT TXD RXD NC NC NC SCLK/PAE A-D OSC0 OSC1 10 11 M-N DGND OSC1 OSC0 BO+ AVDD BO– BI– BI+ BO+ NC NC NC AGND U-C M-N DGND NC: No Connection PIN DESCRIPTION Pin # Pin Name DIP/ QFJ SOP I/O Function AVDD 1 1 — Analog power supply pin BO – 2 2 O LAN - BUS output – BI – 3 3 I LAN - BUS input – BI + 4 4 I LAN - BUS input + BO + 5 5 O LAN - BUS output + AGND 6 9 — Analog ground pin U-C 7 10 I M-N 8 11 I DGND 9 12 — Digital ground pin OSC 1 10 13 O Crystal oscillation output OSC 0 11 14 I Crystal oscillation input 12 15 I 0: data communication A-D 0: UART 1: clock synchronous serial select pin 0: MPC mode 1:normal mode select pin 1: address communication SCLK / PAE 13 16 I Serial clock input/Parity select pin RXD 14 20 I Serial data input pin TXD 15 21 O Serial data output pin INT 16 22 O Interrupt output pin RES 17 23 I Reset input pin DVDD 18 24 — Digital power supply pin 3 MSM6636 ¡ Semiconductor ABSOLUTE MAXIMUM RATINGS DGND = AGND = 0V Parameter Symbol Power Supply Voltage DVDD, AVDD Condition Rated Value Unit -0.3~7.0 V V Input Voltage VI AVDD = DVDD -0.3~DVDD+0.3 Output Voltage VO AVDD = DVDD -0.3~DVDD+0.3 V PD(DIP)*1 Ta = 25°C 860 mW PD(QFJ)*2 PD(SOP)*3 Ta = 25°C Ta = 25°C 960 830 mW -55~150 °C Power Dissipation Storage Temperature TSTG mW PD(DIP)*1: 18PIN DIP package power dissipation PD(QFJ)*2: 18PIN QFJ package power dissipation PD(SOP)*3: 24PIN SOP package power dissipation Power Dissipation Curve 1000 860 500 -40 25 125 150 Ambient temperature Ta (°C) Power dissipation PD(SOP) [mW] < 24PIN SOP package > 4 1000 830 500 -40 25 125 150 Ambient temperature Ta (°C) < 18PIN QFJ package > Power dissipation PD(QFJ) [mW] Power dissipation PD(DIP) [mW] < 18PIN DIP package > 1000 960 500 -40 25 125 150 Ambient temperature Ta (°C) ¡ Semiconductor MSM6636 OPERATION RANGE DGND = AGND = 0V Parameter Symbol Power Supply Voltage Operating Frequency Operating Temperature Ta Condition Rated Value Unit DVDD, AVDD AVDD = DVDD 4.5~5.5 V fOSC DVDD = AVDD = 5V±10% 2~16 MHz -40~+125 °C ELECTRICAL CHARACTERISTICS DC Characteristics DVDD = AVDD = 5V±10%, DGND = AGND = 0V, Ta = -40 ~ +125°C Parameter Symbol Condition Application MIN TYP MAX Unit H Level Input Voltage VIH1 — A DVDD ¥ 0.8 — DVDD + 0.3 V L Level Input Voltage VIL1 — A DGND - 0.3 — DVDD ¥ 0.2 V H Level Input Voltage VIH2 — F DVDD - 2.0 — DVDD + 1.0 V L Level Input Voltage VIL2 — F DGND - 1.0 — DGND + 2.0 V Receiver Hysteresis Width VH — F 100 — 400 mV H Level Input Current IIH1 VI = VDD B — — +1 µA L Level Input Current IIL1 VI = 0V B — — -1 µA H Level Input Current IIH2 VI = VDD C — — +1 µA L Level Input Current IIL2 VI = 0V C — — - 100 µA H Level Input Current IIH3 VI = VDD BI (+) — — + 100 µA L Level Input Current IIL3 VI = 0V BI (-) — — - 100 µA H Level Output Voltage VOH1 IO = -400µA D DVDD - 0.4 — — V L Level Output Voltage VOL1 IO = +3.2mA D — — DGND + 0.4 V H Level Output Voltage VOH2 IO = -4.0mA E DVDD - 0.4 — — V L Level Output Voltage VOL2 IO = +4.0mA E — — DGND + 0.4 V GND Offset Voltage VOFF — — — — ±1 V Current Consumption 1 IDS During sleep — — — 50 µA — — — 10 mA Current Consumption 2 IDD f = 16MHz, no load A: RES, SCLK/PAE, RXD, U-C, M-N, A-D, OSC0 B: SCLK/PAE, RXD, U-C, M-N, A-D C: RES D: TXD, INT E: BO-, BO+ F: BI-, BI+ 5 MSM6636 ¡ Semiconductor AC Chacteristics PWM Bit Timing Parameter Transmit Symbol Bit Length TP1 Receive typ max min max 23.64 24.00 24.36 21.00 28.00 µs "1" Dominant Width TP2 6.90 7.00 7.11 5.00 12.00 µs "0" Dominant Width TP3 14.87 15.00 15.23 13.00 20.00 µs "SOF" Dominant Width TP4 30.54 31.00 31.47 29.00 36.00 µs "SOF,BRK" Length TP5 47.28 48.00 48.72 45.00 52.00 µs "BRK" Dominant Width TP6 38.42 39.00 39.59 37.00 44.00 µs "EOD" + Bit Length TP7 47.28 48.00 48.72 43.00 51.00 µs "EOF" + Bit Length TP8 70.92 72.00 — 69.00 76.00 µs "EOF + IFS" + Bit Length TP9 94.56 96.00 — 86.00 — µs "0" Passive Width TP10 8.86 9.00 9.14 4.00 15.00 µs Note: DVDD = AVDD = 5 V ± 10%, Ta = -40 ~ +125˚C, In setting 41.6 K bps Dominant "1" Passive TP2 Dominant "0 " Passive TP3 TP1 TP10 Dominant " SOF " Passive TP4 TP5 Dominant " EOD " Passive LAST BIT EOD TP7 " EOF " " IFS " Dominant Passive LAST BIT EOF TP8 TP9 Dominant " BRK " Passive TP6 TP5 6 Unit min IFS ¡ Semiconductor MSM6636 CPU Serial Interface Timing mClock synchronous Serial DVDD=AVDD=5V±10%, Ta =-40~+125°C Parameter Symbol Min Typ Max Unit OSCO (source oscillation) Pulse Cycle tø 62 — 500 ns SCLK-L Interval Width tCKLW 8tø — — ns SCLK-H Interval Width tCKHW 8tø — — ns SCLK ≠ - RXD Setup Time tSRS 4tø — — ns SCLK ≠ - RXD Hold Time tSRH 4tø — — ns SCLK ≠ - TXD Output Delay Time tSTD 4tø — 6tø + 100 ns A-D - SCLK ≠ Setup Time tAS 0 — — ns SCLK ≠ - A-D Hold Time tAH 8tø — — ns SCLK Frame Interval Time *1 tINT1 8tø — — ns SCLK Frame Interval Time *2 tINT2 16tø — — ns SCLK Frame Interval Time *1 Between “Communication type (WR) and address setting” frame and “WR data” frame. Between “WR data” frame and “WR data” frame during continuous WR. SCLK Frame Interval Time *2 Between “Communication type (RD) and address setting” frame and “RD data” frame. Between “RD data” frame and “RD data” frame during continuous RD. 7 MSM6636 ¡ Semiconductor mUART DVDD=AVDD=5V±10%, Ta =-40~+125°C Parameter Symbol Min Typ Max Unit 0 — — ns tUAH 0 — — ns tUTD 48tø — 50tø + 100 ns A-D - STOP bit ≠ Setup Time tUAS STOP bit Ø – A-D Hold Time START bit Ø – TXD Output Delay Time Write Frame Interval Time *3 tINT3 0 — — ns Read Frame Interval Time *4 tINT4 10tø — — ns Write Frame Interval Time *3 Between “Communication type (WR) and address setting” frame and “WR data” frame. Between “WR data” frame and “WR data” frame during continuous WR. Read Frame Interval Time *4 Between “Communication type (RD) and address setting” frame and “RD data” frame. 8 ¡ Semiconductor MSM6636 Wakeup Input Signal DVDD=AVDD=5V±10%, Ta =-40~+125°C Parameter Symbol Min Typ Max Unit tWD 7 — — µs RXD Terminal Input Pulse Width tWR 300 — — ns Bus Receiver Stable Time *5 tRS 1 — — µs LAN bus Passive Æ Dominant Change Pulse Width tø OSC0 tUAS tUAH A-D RXD TXD STOP tINT3 tINT4 START tUTD START STOP bit Termination Note: The time chart shows the wakeup input signals from each sleep status Bus Receiver Stable Time *5 The stable time of the bus receiver is from just after wakeup to the restart of message transmission and reception. However, the clock oscillation source should use an external clock. (A clock is input even in the sleep status.) 9 MSM6636 ¡ Semiconductor Fault Tolerant Function Operation Conditions DVDD=AVDD=5V±10%, Ta =-40~+125°C, In setting 41.6Kbps Parameter Symbol Min Typ Max Unit LAN bus (+) GND Short Circuit Detection Pulse Width tPG 5 — — µs LAN bus (+) VDD Short Circuit Detection Pulse Width tPV 48 — — µs LAN bus (-) GND Short Circuit Detection Pulse Width tNG 48 — — µs LAN bus (-) VDD Short Circuit Detection Pulse Width tNV 5 — — µs BUS(+) BUS(-) tPG tPV tNV tNG BUS(+) BUS(-) Reset Input Pulse Width DVDD=AVDD=5V±10%, Ta=–40~+125°C Parameter Reset Input Pulse Width RES tRES 10 Symbol Min Typ Max Unit tRES 0.1 — — µs ¡ Semiconductor MSM6636 APPLICATION EXAMPLE Host CPU and LAN bus Connection Example Host CPU and LAN bus connection example of MSM6636 is shown below. Unit A Host CPU MSM6636 SOUT SIN INT CLKOUT OPEN RES DVDD AVDD RXD TXD BO (+) INT OSC0 BI (+) OSC1 SCLK / PAE BI (-) U-C M-N BO (-) A-D RES DGND AGND ZD ZD Unit B . . . Bus + Bus - The above connection example is when "UART, MPC and parity no mode" was used as the "host CPU interface, and when CLKOUT output of the host CPU" was used as the clock for MSM6636. Depending on the control target, an optimum host CPU (number of ports, A/D converter yes / no) can be selected, and an optimum system can be constructed. 11