NEC UPD178F098

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD178F098
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD178F098 is a flash memory model of the µPD178076, 178078, 178096, and 178098, and is provided with
a flash memory to/from which data can be written/erased with the microcontroller mounted on a printed circuit board.
For the detailed functional description, refer to the following User’s Manuals:
µPD178078, 178098 Subseries User’s Manual: U12790E
78K/0 Series User’s Manual - Instruction
: U12326E
FEATURES
• Serial interface (UART mode)
• IEBusTM controller
• Pin-compatible with mask ROM models (except VPP pin)
• Flash memory: 60K bytesNote
• Internal high-speed RAM: 1024 bytes
• Internal extension RAM: 2048 bytesNote
• Buffer RAM: 32 bytes
• Operable at same supply voltage as mask ROM models (VDD = 4.5 to 5.5 V during PLL operation)
Note
The capacities of the flash memory and internal extension RAM can be changed using the memory size
select register (IMS) and internal extension RAM size select register (IXS).
Remark For the differences between the flash memory model and mask ROM models, refer to 1. DIFFERENCES
BETWEEN µPD178F098 AND MASK ROM MODELS.
The electrical specifications (such as supply current) in the µPD178F098 differ from those of the
mask ROM models. Confirm these differences before mass-producing any application set.
APPLICATION FIELD
Car stereos
ORDERING INFORMATION
Part Number
Package
µPD178F098GF-3BA
100-pin plastic QFP (14 × 20)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12920EJ1V0DS00
Date Published June 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 2000
µPD178F098
DEVELOPMENT OF 8-BIT DTS SERIES
Models under mass production
Models under development
Flash memory model or
PROM model
80 pins
µ PD178F048
Mask ROM model
80 pins
Internal OSD controller
8-bit PWM × 4 channels
14-bit PWM × 1 channel
µ PD178048 subseries
Internal OSD controller
8-bit PWM × 4 channels
14-bit PWM × 1 channel
100 pins
µ PD178098 subseries
Internal IEBus controller
100 pins
µ PD178F098
Internal IEBus controller and UART
100 pins
µ PD178078 subseries
Internal UART
80 pins
µ PD178F134
80 pins
Internal LCD and UART
80 pins
µ PD178F124
Internal LCD and UART
80 pins
Internal UART
80 pins
µPD178034 subseries
µPD178024 subseries
Internal UART
80 pins
µPD178018A subseries
80 pins
µPD178003 subseries
µPD178P018A
Limits functions of µPD178018A subseries
2
Data Sheet U12920EJ1V0DS00
µPD178F098
FUNCTIONAL OUTLINE
(1/2)
Item
Functions
Internal
Flash memory
60K bytes
memory
High-speed RAM 1024 bytes
Buffer RAM
32 bytes
Extension RAM
2048 bytes
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution
• 0.32 µs/0.64 µs/1.27 µs/2.54 µs/5.08 µs (with crystal resonator of fX = 6.3 MHz)
time
• 0.44 µs/0.89 µs/1.78 µs/3.56 µs/7.11 µs (with crystal resonator of f X = 4.5 MHz) Note 1
Instruction set
•
•
•
•
I/O port
Total
: 80 pins
• CMOS input
:
• CMOS I/O
: 64 pins
16-bit operation
Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
Bit manipulation (set, reset, test Boolean operation)
BCD adjustment, etc.
• N-ch open-drain output :
A/D converter
8-bit resolution × 8 channels
Serial interface
•
•
•
•
8 pins
3-wire/SBI/2-wire/I2C busNote 2 mode selectable
:1
3-wire mode
:1
3-wire mode (with automatic transmit/receive function of up to 32 bytes): 1
UART mode
:1
IEBus controller
Provided
Timer
•
•
•
•
Buzzer output
8 pins
Basic timer (timer carry FF (10 Hz))
16-bit timer/event counter
8-bit timer/event counter
Watchdog timer
:
:
:
:
1
1
2
1
channel
channel
channel
channel
channel
channel
channels
channel
BEEP0 pin: 1 kHz, 1.5 kHz, 3 kHz, 4 kHz
BUZ pin: 0.77 kHz, 1.54 kHz, 3.08 kHz, 6.15 kHz (with crystal resonator of fX = 6.3 MHz)
Vectored
Maskable
Internal : 15, External: 8
interrupt
Non-maskable
Internal: 1
source
Software
1
PLL
Division mode
frequency
2 types
• Direct division mode (VCOL pin)
synthesizer
• Pulse swallow mode (VCOL and VCOH pins)
Reference
frequency
Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz)
Charge pump
Error out output: 2 pins
Phase
comparator
Unlock detectable in software
Notes 1. When using the IEBus controller, the 4.5-MHz crystal resonator cannot be used. Use the 6.3-MHz
crystal resonator.
2. When the I2C bus mode is used (including when the mode is implemented in software without using
the peripheral hardware), consult NEC when ordering a mask.
Data Sheet U12920EJ1V0DS00
3
µPD178F098
(2/2)
Item
Frequency counter
Functions
Frequency measurement
• AMIFC pin: For 450-kHz counting
• FMIFC pin: For 450-kHz/10.7-MHz counting
Standby function
• HALT mode
• STOP mode
Reset
•
•
•
•
•
•
Supply voltage
• VDD = 4.5 to 5.5 V (during CPU, PLL operation)
• VDD = 3.5 to 5.5 V (during CPU operation)
Package
100-pin plastic QFP (14 × 20)
Note
4
Reset by RESET pin
Internal reset by watchdog timer
Reset by power-ON clear circuit
Detection of less than 4.5 VNote (Reset does not occur, however.)
Detection of less than 3.5 VNote (during CPU operation)
Detection of less than 2.3 VNote (in STOP mode)
These voltages are the maximum values. In practice, the chip may be reset at voltages lower than these.
Data Sheet U12920EJ1V0DS00
µPD178F098
PIN CONFIGURATION (Top View)
• 100-pin plastic QFP (14 × 20)
GNDPORT
VDDPORT
P47
P46
P45
P44
P43
P42
P41
P40
P67
P66
P65
P64
P63
P62
P61
P60
GND1
P07/INTP7
µPD178F098GF-3BA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P06/INTP6
P05/INTP5
P04/INTP4
P124
P123
P122
P121/RX0
P120/TX0
P77
P76
P75/TXD0
P74/RXD0
P137
P136
P135
P134
P133
P132
P131/TO51
P130/TO50
P37/BUZ
P36/BEEP0
P35/TI51
P34/TI50
P33/TI01
P32/TI00
P31/TO0
P30/VM45
P03/INTP3
P02/INTP2
P17/ANI7
AVSS
REGCPU
VDD
REGOSC
X2
X1
GND0
P100
GND2
P101/AMIFC
P102/FMIFC
VDDPLL
VCOH
VCOL
GNDPLL
EO0
EO1
VPP
RESET
P00/INTP0
P01/INTP1
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P70/SI3
P71/SO3
P72/SCK3
P73
P50
P51
P52
P53
P54
P55
P56
P57
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
AVDD
P14/ANI4
P15/ANI5
P16/ANI6
Cautions 1. Directly connect the VPP pin to GND0, GND1, or GND2 in normal operating mode.
2. Keep the voltage at AVDD, VDDPORT, and VDDPLL same as that at the VDD pin.
3. Keep the voltage at AVSS, GNDPORT, and GNDPLL same as that at GND0, GND1, or GND2.
4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-µF capacitor.
Data Sheet U12920EJ1V0DS00
5
µPD178F098
Pin Name
AMIFC
: AM intermediate frequency counter
input
REGOSC
: Regulator for oscillation circuit
RESET
: Reset input
ANI0-ANI7
: A/D converter input
RXD0
: UART0 serial data input
AVDD
: A/D converter power supply
RX0
: IEBus serial data input
: Serial data bus input/output
AVSS
: A/D converter ground
SB0, SB1
BUSY
: Busy output
SCK0, SCK1, SCK3 : Serial clock input/output
BEEP0, BUZ
: Buzzer output
SCL
: Serial clock input/output
EO0, EO1
: Error out output
SDA0, SDA1
: Serial data input/output
FMIFC
: FM intermediate frequency counter
SI0, SI1, SI3
: Serial data input
SO0, SO1, SO3
: Serial data output
input
GNDPLL
: PLL ground
STB
: Strobe output
GND0-GND2
: Ground
TI00, TI01
: 16-bit timer capture trigger input
INTP0-INTP7
: Interrupt input
TI50, TI51
: 8-bit timer clock input
P00-P07
: Port 0
TO0
: 16-bit timer output
P10-P17
: Port 1
TO50, TO51
: 8-bit timer output
P20-P27
: Port 2
TXD0
: UART0 serial data output
P30-P37
: Port 3
TX0
: IEBus serial data output
P40-P47
: Port 4
VCOL, VCOH
: Local oscillation input
P50-P57
: Port 5
VDDPORT
: Port power supply
P60-P67
: Port 6
VDDPLL
: PLL power supply
P70-P77
: Port 7
VDD
: Power supply
P100-P102
: Port 10
VM45
: VDD = 4.5 V monitor output
P120-P124
: Port 12
VPP
: Programming power supply
P130-P137
: Port 13
X1, X2
: Crystal resonator
REGCPU
: Regulator for CPU power supply
6
Data Sheet U12920EJ1V0DS00
µPD178F098
BLOCK DIAGRAM
TO0/P31
TI00/P32
TI01/P33
16-bit TIMER/
EVENT COUNTER
PORT 0
8
P00-P07
TI50/P34
TO50/P130
8-bit TIMER/
EVENT COUNTER 50
PORT 1
8
P10-P17
TI51/P35
TO51/P131
8-bit TIMER/
EVENT COUNTER 51
PORT 2
8
P20-P27
WATCHDOG TIMER
PORT 3
8
P30-P37
BASIC TIMER
PORT 4
8
P40-P47
PORT 5
8
P50-P57
PORT 6
8
P60-P67
PORT 7
8
P70-P77
PORT10
3
P100-P102
PORT 12
5
P120-P124
PORT 13
8
P130-P137
8
ANI0/P10ANI7/P17
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
SERIAL
INTERFACE 1
SI3/P70
SO3/P71
SCK3/P72
SERIAL
INTERFACE 3
RXD0/P74
TXD0/P75
UART0
RX0/P121
TX0/P120
IEBus0
INTP0/P00INTP7/P07
BEEP0/P36
BUZ/P37
RESET
X1
X2
VDDPORT
GNDPORT
VDD
VM45/P30
REGOSC
REGCPU
GND0
78K/0
CPU
CORE
SERIAL
INTERFACE 0
8
FLASH
MEMORY
(60K bytes)
RAM
(3K bytes)
INTERRUPT
CONTROL
A/D
CONVERTER
BUZZER OUTPUT
SYSTEM
CONTROL
RESET
CPU
FREQUENCY
COUNTER
AMIFC/P101
FMIFC/P102
PERIPHERAL
PLL
VOLTAGE
REGULATOR
AVDD
AVSS
VOSC
VCPU
PLL
VOLTAGE
REGULATOR
EO0
EO1
VCOL
VCOH
VDDPLL
GNDPLL
IC
GND2
GND1
Data Sheet U12920EJ1V0DS00
7
µPD178F098
CONTENTS
1.
DIFFERENCES BETWEEN µPD178F098 AND MASK ROM MODELS ..................................... 9
2.
PIN
2.1
2.2
2.3
3.
MEMORY SIZE SELECT REGISTER (IMS) ................................................................................. 17
4.
INTERNAL EXTENSION RAM SIZE SELECT REGISTER (IXS) .............................................. 18
5.
INTERRUPT FUNCTION ................................................................................................................. 19
6.
FLASH MEMORY PROGRAMMING ..............................................................................................
6.1 Selecting Communication Mode ...........................................................................................
6.2 Flash Memory Programming Function .................................................................................
6.3 Connecting Flashpro III ..........................................................................................................
7.
ELECTRICAL SPECIFICATIONS ................................................................................................... 26
8.
PACKAGE DRAWING ..................................................................................................................... 44
9.
RECOMMENDED SOLDERING CONDITIONS ............................................................................. 45
FUNCTION LIST ...................................................................................................................... 10
Port Pins .................................................................................................................................. 10
Pins Other Than Port Pins ...................................................................................................... 11
I/O Circuits of Pins and Recommended Connections of Unused Pins ............................. 13
23
23
24
25
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 46
APPENDIX B. RELATED DOCUMENTS .............................................................................................. 48
8
Data Sheet U12920EJ1V0DS00
µPD178F098
1. DIFFERENCES BETWEEN µPD178F098 AND MASK ROM MODELS
The µPD178F098 is provided with a flash memory to/from which data can be written/erased with the device
mounted on a printed circuit board. The differences between the flash memory model (µPD178F098) and mask ROM
models (µPD178076, 178078, 178096, and 178098) are shown in Table 1-1.
Table 1-1. Differences between µPD178F098 and Mask ROM Models
µPD178F098
Item
Internal memory
µPD178076, 178078
µPD178096, 178098
ROM structure
Flash memory
Mask ROM
ROM capacity
60K bytes
µPD178076: 48K bytes
µPD178078: 60K bytes
µPD178096: 48K bytes
µPD178098: 60K bytes
External
2048 bytes
µPD178076: 1024 bytes
µPD178078: 2048 bytes
µPD178096: 1024 bytes
µPD178098: 2048 bytes
Internal ROM capacity selected by
memory size select register (IMS)
Equivalent to mask ROM
model
µPD178076: CCH
µPD178078: CFH
µPD178096: CCH
µPD178098: CFH
Internal extension RAM capacity
selected by internal extension RAM
size select register (IXS)
Equivalent to mask ROM
model
µPD178076: 0AH
µPD178078: 08H
µPD178096: 0AH
µPD178098: 08H
Serial interface
4
•
•
•
•
IEBus controller
Provided
extension RAM
channels
3-wire/SBI/2-wire/I2C bus mode selectable
3-wire (with automatic transmit/receive function)
3-wire
UART
3 channels
• 3-wire/SBI/2-wire/I2C bus
mode selectable
• 3-wire (with automatic
transmit/receive function)
• 3-wire
Not provided
Provided
21
Interrupt source
24
22
IC pin
Not provided
Provided
VPP pin
Provided
Not provided
Electrical specifications and
recommended soldering conditions
See the relevant data sheet
Caution The noise resistance and noise radiation differ between flash memory versions and mask ROM
versions. When considering the replacement of flash memory versions with mask ROM versions
in the process from trial manufacturing to mass production, adequate evaluation should be carried
out using CS products (not ES products) of mask ROM versions.
Data Sheet U12920EJ1V0DS00
9
µPD178F098
2. PIN FUNCTION LIST
2.1 Port Pins (1/2)
Pin Name
P00-P07
I/O
I/O
Function
Port 0.
8-bit I/O port.
At Reset
Shared by:
Input
INTP0-INTP7
Can be set in input or output mode in 1-bit units.
P10-P17
Input
Port 1.
8-bit input port.
Input
ANI0-ANI7
P20
I/O
Port 2.
Input
SI1
P21
8-bit I/O port.
SO1
P22
Can be set in input or output mode in 1-bit units.
SCK1
P23
STB
P24
BUSY
P25
SI0/SB0/SDA0
P26
SO0/SB1/SDA1
P27
SCK0/SCL
P30
I/O
Port 3.
Input
P31
8-bit I/O port.
P32
Can be set in input or output mode in 1-bit units.
VM45
TO0
TI00
P33
TI01
P34
TI50
P35
TI51
P36
BEEP0
P37
P40-47
BUZ
I/O
Port 4.
Input
–
Input
–
Input
–
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
P50-P57
I/O
Port 5.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
P60-P67
I/O
Port 6.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
P70
I/O
Port 7.
Input
SI3
P71
8-bit I/O port.
SO3
P72
Can be set in input or output mode in 1-bit units.
SCK3
P73
–
P74
RXD0
P75
TXD0
P76, P77
10
–
Data Sheet U12920EJ1V0DS00
µPD178F098
2.1 Port Pins (2/2)
Pin Name
P100
I/O
I/O
P101
At Reset
Port 12.
5-bit I/O port.
P122-P124
Can be set in input or output mode in 1-bit units.
Output
FMIFC
Input
P121
P130
–
AMIFC
Can be set in input or output mode in 1-bit units.
I/O
Shared by:
Input
3-bit I/O port.
P102
P120
Function
Port 10.
TX0
RX0
–
Port 13.
Low-level
TO50
P131
8-bit output port.
output
TO51
P132-P137
N-ch open-drain output port (15 V withstand)
–
2.2 Pins Other Than Port Pins (1/2)
Pin Name
INTP0-INTP7
I/O
Input
Function
At Reset
External maskable interrupt input whose valid edge
Input
Shared by:
P00-P07
(rising edge, falling edge, or both rising and falling edges)
can be specified.
SI0
Input
Serial data input to serial interface.
Input
SI1
SI3
SO0
P70
Output
Serial data output from serial interface.
Input
SO1
P71
I/O
SB1
Serial data input/output to/from
N-ch open drain I/O
Input
serial interface.
P25/SI0/SDA0
P26/SO0/SDA1
SDA0
P25/SI0/SB0
SDA1
SCK0
P26/SB1/SDA1
P21
SO3
SB0
P25/SB0/SDA0
P20
P26/SO0/SB1
I/O
Serial clock input/output to/from serial interface.
Input
P27/SCL
SCK1
P22
SCK3
P72
SCL
STB
N-ch open drain I/O
Output
Strobe output for serial interface automatic transmission/
P27/SCK0
Input
P23
Input
P24
reception.
BUSY
Input
Busy input for serial interface automatic transmission/
reception.
VW45
Output
V DD = 4.5 V monitor output
Input
P30
TI00
Input
External count clock input to 16-bit timer (TM0).
Input
P32
TI01
TI50
P33
Input
TI51
TO0
Output
TO50
TO51
BEEP0
External count clock input to 8-bit timer (TM50).
Input
External count clock input to 8-bit timer (TM51).
Output
P34
P35
16-bit timer (TM0) output.
Input
P31
8-bit timer (TM50) output.
Low-level
P130
8-bit timer (TM51) output.
output
P131
Buzzer output.
Input
P36
BUZ
P37
Data Sheet U12920EJ1V0DS00
11
µPD178F098
2.2 Pins Other Than Port Pins (2/2)
Pin Name
I/O
ANI0-ANI7
Input
EO0, EO1
Output
Function
Analog input to A/D converter.
Error out output from charge pump of PLL frequency
At Reset
Shared by:
Input
P10-P17
–
–
–
–
synthesizer.
VCOL
Input
Inputs local oscillation frequency of PLL (in HF and MF
modes).
VCOH
Input
Inputs local oscillation frequency of PLL (in VHF mode).
AMIFC
Input
Input to AM intermediate frequency counter.
Input
–
P101
–
FMIFC
Input
Input to FM intermediate frequency or AM intermediate
Input
P102
Serial data input to asynchronous serial interface (UART0).
Input
P74
Serial data output from asynchronous serial interface
Input
P75
frequency counter.
RXD0
Input
TXD0
Output
(UART0).
TX0
Output
IEBus controller data output.
Input
P120
RX0
Input
IEBus controller data input.
Input
P121
RESET
Input
System reset input.
–
–
X1
Input
Connection of crystal resonator for system clock oscillation.
–
–
–
–
–
–
–
–
X2
–
REGOSC
–
Regulator for oscillation circuit. Connect this pin to GND via
0.1-µF capacitor.
REGCPU
–
Regulator for CPU power supply. Connect this pin to GND
via 0.1-µF capacitor.
VDD
–
Positive power supply.
–
–
GND0-GND2
–
Ground.
–
–
VDDPORT
–
Port power supply.
–
–
GNDPORT
–
Port ground.
–
–
AVDD
–
A/D converter positive power supply. Keep voltage at this
–
–
AVSS
–
–
–
VDDPLL Note
–
PLL positive power supply.
–
–
GNDPLLNote
–
PLL ground.
–
–
VPP
–
Pin to apply high voltage at program writing/verifying.
–
–
pin same as that at VDD0.
A/D converter ground. Keep voltage at this pin same as
that at GND0 through GND2.
Directly connect this pin to GND0, GND1, or GND2 in
normal operating mode.
Note
12
Connect a capacitor of about 1000 pF between the VDDPLL and GNDPLL pins.
Data Sheet U12920EJ1V0DS00
µPD178F098
2.3 I/O Circuits of Pins and Recommended Connections of Unused Pins
Table 2-1 shows the types of the I/O circuits of the respective pins and the recommended connections of the pins
when they are not used.
For the configuration of the I/O circuit of each pin, refer to Figure 2-1.
Table 2-1. I/O Circuit Type of Each Pin (1/2)
Pin Name
I/O Circuit Type
I/O
Recommended Connection of Unused Pin
P00/INTP0-P07/INTP7
8
I/O
Input: Connect each of them to VDD, VDDPORT, GND0 to
GND2, or GNDPORT via resistor.
Output: Leave open.
P10/ANI0-P17/ANI7
25
Input
Connect these pins to VDD, VDDPORT, GND0 to GND2 or
GNDPORT.
P20/SI1
5-K
I/O
Input: Connect each of them to VDD, VDDPORT, GND0 to
GND2, or GNDPORT via resistor.
Output: Leave open.
P21/SO1
5
P22/SCK1
5-K
P23/STB
5
P24/BUSY
5-K
P25/SI0/SB0/SDA0
10-D
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30/VM45
5
P31/TO0
P32/TI00
5-K
P33/TI01
P34/TI50
P35/TI51
P36/BEEP0
5
P37/BUZ
P40-P47
P50-P57
P60-P67
P70/SI3
5-K
P71/SO3
5
P72/SCK3
5-K
P73
5
P74/RXD0
5-K
P75/TXD0
5
P76, P77
P100
P101/AMIFC
P102/FMIFC
P120/TX0
P121/RX0
5-K
P122-P124
5
Data Sheet U12920EJ1V0DS00
13
µPD178F098
Table 2-1. I/O Circuit Type of Each Pin (2/2)
Pin Name
P130/TO50
I/O Circuit Type
19
I/O
Output
Recommended Connection of Unused Pin
Open these pins.
P131/TO51
P132-P137
EO0
DTS-EO1
EO1
VCOL, VCOH
DTS-AMP2
REGOSC, REGCPU
RESET
AVDD
AVSS
Input
–
2
Disable PLL in software and select pull-down.
–
Connect these pins to GND0, GND1, or GND2 via 0.1-µF
capacitor.
–
Connect this pin to VDD or VDDPORT.
Input
–
–
Directly connect these pins to GND0 to GND2, or GNDPORT.
VPP
14
Data Sheet U12920EJ1V0DS00
µPD178F098
Figure 2-1. I/O Circuits of Respective Pins (1/2)
Type 5
Type 2
VDD
data
P-ch
IN/OUT
IN
output
disable
Schmitt trigger input with hysteresis characteristics
N-ch
input
enable
Type 8
Type 5-K
VDD
VDD
data
P-ch
data
P-ch
IN/OUT
IN/OUT
output
disable
N-ch
output
disable
N-ch
input
enable
Type 19
Type 10-D
VDD
data
P-ch
OUT
IN/OUT
open drain
output disable
N-ch
N-ch
input
enable
Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as
VDDPORT and GNDPORT.
Data Sheet U12920EJ1V0DS00
15
µPD178F098
Figure 2-1. I/O Circuits of Respective Pins (2/2)
Type 25
Type DTS-EO1
VDDPLL
P-ch
Comparator
+
DW
–
N-ch
VREF (Threshold voltage)
P-ch
IN
OUT
input
enable
UP
N-ch
GNDPLL
Type DTS-AMP
VDDPLL
IN
Note
GNDPLL
Note
This switch is selectable in software only for the VCOL and VCOH pins.
Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as
VDDPORT and GNDPORT.
16
Data Sheet U12920EJ1V0DS00
µPD178F098
3. MEMORY SIZE SELECT REGISTER (IMS)
The internal memory capacity of the µPD178F098 can be changed using the memory size select register (IMS).
By using this register, the memory of the µPD178F098 can be mapped in the same manner as a mask ROM model
with a different internal memory capacity.
Use an 8-bit memory manipulation instruction to set the IMS.
This register is set to CFH at reset.
Figure 3-1. Format of Memory Size Select Register (IMS)
Symbol
7
6
5
4
IMS RAM2 RAM1 RAM0
RAM2
1
0
3
0
Others
0
Address
At reset
R/W
FFF0H
CFH
R/W
Selects internal high-speed RAM capacity
1024 bytes
Setting prohibited
RAM3 RAM2
RAM1
RAM0
Selects internal ROM capacity
1
1
0
0
48K bytes
1
1
1
1
60K bytes
Others
1
ROM3 ROM2 ROM1 ROM0
RAM1 RAM0
1
2
Setting prohibited
Table 3-1 shows the setting of IMS to perform the same memory mapping as that of a mask ROM model.
Table 3-1. Setting of Memory Size Select Register
Targeted Model
Setting of IMS
µPD178076, 178096
CCH
µPD178078, 178098
CFH
Data Sheet U12920EJ1V0DS00
17
µPD178F098
4. INTERNAL EXTENSION RAM SIZE SELECT REGISTER (IXS)
The internal extention RAM capacity of the µPD178F098 can be changed using the internal extention RAM size
select register (IXS). By using this register, the memory of the µPD178F098 can be mapped in the same manner
as a mask ROM model with a different internal extention RAM capacity.
Use an 8-bit memory manipulation instruction to set the IXS.
This register is set to 0CH at reset.
Figure 4-1. Format of Internal Extension RAM Size Select Register (IXS)
Symbol
7
6
5
IXS
0
0
0
4
3
2
1
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0
Address
At reset
R/W
FFF4H
0CH
R/W
Selects internal extension RAM capacity
0
1
0
0
0
2048 bytes
0
1
0
1
0
1024 bytes
Others
0
Setting prohibited
Table 4-1 shows the setting of IXS to perform the same memory mapping as that of a mask ROM model.
Table 4-1. Setting of Internal RAM Size Select Register
18
Targeted Model
Setting of IXS
µPD178076, 178096
0AH
µPD178078, 178098
08H
Data Sheet U12920EJ1V0DS00
µPD178F098
5. INTERRUPT FUNCTION
The µPD178F098 has the following three types and 24 sources of interrupts:
• Non-maskable : 1Note
• Maskable
: 23Note
• Software
: 1
Note
Two types of watchdog interrupt sources (INTWDT), non-maskable and maskable, are available, and
either of them can be selected.
Table 5-1. Interrupt Sources (1/2)
Default
Interrupt Type PriorityNote 1
Interrupt Source
Name
Trigger
Internal/
External
Vector
Basic
Table
Configuration
Address TypeNote 2
Internal
0004H
Non-maskable
–
INTWDT
Overflow of watchdog timer
(when watchdog timer mode 1 is selected)
Maskable
0
INTWDT
Overflow of watchdog timer
(when interval timer mode is selected)
1
INTP0
Pin input edge detection
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTP6
0012H
8
INTP7
0014H
9
INTCSI0
End of transfer by serial interface 0
10
INTCSI1
End of transfer by serial interface 1
0018H
11
INTCSI3
End of transfer by serial interface 3
001AH
12
INTTM50
Generation of coincidence signal of 8-bit
timer/event counter 50
001CH
13
INTTM51
Generation of coincidence signal of 8-bit
timer/event counter 51
001EH
14
INTSER0
Reception error of serial interface UART0
0020H
15
INTSR0
End of reception by serial interface UART0
0022H
(A)
(B)
External
Internal
0006H
0016H
16
INTST0
End of transmission by serial interface UART0
0024H
17
INTBTM0
Generation of coincidence signal of basic
0026H
(C)
(B)
timer
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending
according to their default priorities. The default priority 0 is the highest, while 22 is the lowest.
2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 5-1.
Data Sheet U12920EJ1V0DS00
19
µPD178F098
Table 5-1. Interrupt Sources (2/2)
Default
Interrupt Type PriorityNote 1
Maskable
18
19
Software
Internal/
External
Vector
Basic
Table
Configuration
Address Type Note 2
Generation of signal indicating coincidence
between 16-bit timer counter (TM0) and
capture/compare register (CR00) (when
CR00 is used as compare register)
Internal
0028H
Detection of input edge of TI00/P32 pin
(when CR00 is used as capture register)
External
Generation of signal indicating coincidence
between 16-bit timer counter (TM0) and
capture/compare register (CR01) (when
CR01 is used as compare register)
Internal
Detection of input edge of TI01/P33 pin
(when CR01 is used as capture register)
External
Internal
Interrupt Source
Name
INTTM00
INTTM01
Trigger
(B)
(D)
002AH
(B)
(D)
20
INTIE1
IEBus0 data access request
21
INTIE2
IEBus0 communication error and start/end
of communication
002EH
22
INTAD
End of conversion by A/D converter AD1
0030H
(B)
–
BRK
Execution of BRK instruction
003EH
(E)
–
002CH
(B)
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending
according to their default priorities. The default priority 0 is the highest, while 22 is the lowest.
2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 5-1.
20
Data Sheet U12920EJ1V0DS00
µPD178F098
Figure 5-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Interrupt
request
Vector table
address generation
circuit
Priority control
circuit
Standby release
signal
(B) Internal maskable interrupt
Internal bus
MK
Interrupt
request
IE
PR
ISP
Priority control
circuit
IF
Vector table
address generation
circuit
Standby release
signal
(C) External maskable interrupt (INTP0 through INTP7)
Internal bus
External interrupt
rising/falling edge enable
registers (EGP, EGN)
Interrupt
request
Edge detection
circuit
MK
IF
IE
PR
Priority control
circuit
ISP
Vector table
address generation
circuit
Standby release
signal
Data Sheet U12920EJ1V0DS00
21
µPD178F098
Figure 5-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupts (INTTM00, INTTM01)
Internal bus
Prescaler mode register
(PRM0)
Interrupt
request
Edge detection
circuit
MK
IF
IE
PR
ISP
Priority control
circuit
Vector table
address generation
circuit
Standby release
signal
(E) Software interrupt
Internal bus
Interrupt
request
Priority control
circuit
Remark IF : Interrupt request flag
IE : Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority specification flag
22
Data Sheet U12920EJ1V0DS00
Vector table
address generation
circuit
µPD178F098
6. FLASH MEMORY PROGRAMMING
The program memory provided in the µPD178F098 is flash memory.
The flash memory can be written on-board, i.e., with the µPD178F098 mounted on the target system.
To do so, connect a dedicated flash writer (Flashpro III (Part number FL-PR3, PG-FP3)) to the host machine and
target system.
Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.
6.1 Selecting Communication Mode
The flash memory is written by using Flashpro III and by means of serial communication. Select a communication
mode from those listed in Table 6-1. To select a communication mode, the format shown in Figure 6-1 is used. Each
communication mode is selected depending on the number of VPP pulses shown in Table 6-1.
Table 6-1. Communication Modes
Communication Mode
Number of Channels
Pins Used
3-wire serial I/O (SIO3)
1
SI3/P70
SO3/P71
UART0
1
RXD0/P74
TXD0/P75
Number of VPP Pulses
0
SCK3/P72
8
Caution Be sure to select a communication mode by the number of VPP pulses shown in Table 6-1.
Figure 6-1. Communication Mode Selection Format
VPP pulse
10 V
VPP
VDD
GND
VDD
RESET
GND
Flash memory writing mode
Data Sheet U12920EJ1V0DS00
23
µPD178F098
6.2 Flash Memory Programming Function
An operation such as writing the flash memory is performed when a command or data is transmitted/received in
the selected communication mode. The major flash memory programming functions are listed in Table 6-2.
Table 6-2. Major Flash Memory Programming Functions
Function
Description
Batch erase
Erases all memory contents.
Batch blank check
Checks erased status of entire memory.
Data write
Writes data to flash memory starting from write start address and based on number
of data (bytes) to be written).
Batch verify
24
Compares all contents of memory with input data.
Data Sheet U12920EJ1V0DS00
µPD178F098
6.3 Connecting Flashpro III
Connection with Flashpro III differs depending on the communication mode (3-wire serial I/O or UART0). Figures
6-2 and 6-3 show the connection in the respective modes.
Figure 6-2. Connection of Flashpro III in 3-Wire Serial I/O Mode
µ PD178F098
Flashpro III
VPP
VPP
VDD
VDD
RESET
RESET
CLK
X1
SCK
SCK3
SO
SI3
SI
SO3
GND
GND
Figure 6-3. Connection of Flashpro III in UART0 Mode
µ PD178F098
Flashpro III
VPP
VPP
VDD
VDD
RESET
RESET
CLK
X1
SO
RXD0
SI
TXD0
GND
GND
Data Sheet U12920EJ1V0DS00
25
µPD178F098
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T A = 25 °C)
Parameter
Supply voltage
Symbol
Conditions
VDD
Unit
–0.3 to +6.0
V
0.3 Note 1
V
AVDD
–0.3 to VDD + 0.3 Note 1
V
VDDPLL
–0.3 to VDD + 0.3 Note 1
V
VPP
–0.3 to +10.5
V
–0.3 to VDD + 0.3
V
–0.3 to VDD + 0.3
V
V
VDDPORT
Input voltage
VI
Output voltage
VO
Output breakdown
Rating
–0.3 to VDD +
Excluding P130 to P137
VBDS
P130-P137
N-ch open drain
16
Analog input voltage
VAN
P10-P17
Analog input pin
–0.3 to VDD + 0.3
V
High-level output
IOH
1 pin
–8
mA
Total of P00-P01, P20-P27, P50-P57, and P70-P73
–15
mA
Total of P02-P07, P30-P37, P40-P47, P60-P67,
–15
mA
–10
mA
Peak value
16
mA
r.m.s
8
mA
voltage
current
P74-P77, and P120-P124
Total of P100-P102
Low-level output
IOL Note 2
1 pin
current
Total of P00-P01, P20-P27, P50-P57,
Peak value
30
mA
and P70-P73
r.m.s
15
mA
Total of P02-P07, P30-P37, P40-P47,
Peak value
30
mA
P60-P67, P74-P77, P120-P124, and
r.m.s
15
mA
Peak value
20
mA
r.m.s
10
mA
–40 to +85
°C
10 to 40
°C
–55 to +125
°C
P130-P137
Total of P100-102
Operating temperature
TA
During normal operation
During flash memory programming
Storage temperature
Tstg
Notes 1. Keep the voltage at VDDPORT, AVDD, and VDDPLL same as that at the VDD pin.
2. Calculate the r.m.s as follows: [r.m.s] = [Peak value] x √Duty
Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality
of the product may be degraded. The absolute maximum ratings, therefore, are the values
exceeding which the product may be physically damaged. Be sure to use the product with these
ratings never being exceeded.
Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
26
Data Sheet U12920EJ1V0DS00
µPD178F098
Recommended Supply Voltage Ranges (TA = –40 to +85 °C)
Parameter
Supply voltage
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VDD1
When CPU and PLL are operating
4.5
5.0
5.5
V
VDD2
When CPU is operating and PLL is stopped
3.5
5.0
5.5
V
Data retention voltage
VDDR
When crystal oscillation stops
2.3
5.5
V
Output breakdown
VBDS
P130-P137 (N-ch open drain)
15
V
MAX.
Unit
voltage
DC Characteristics (TA = –40 to +85°C, V DD = 3.5 to 5.5 V)
Parameter
High-level input
voltage
Low-level input
Symbol
Test Conditions
MIN.
VIH1
P10-P17, P21, P23, P30, P31, P36, P37, P40-P47,
P50-P57, P60-P67, P71, P73, P75-P77, P100-P102,
P120, P122-P124
0.7 VDD
VDD
V
VIH2
P00-P07, P20, P22, P24-P27, P32-P35, P70, P72,
P74, P121, RESET
0.8 VDD
VDD
V
VIL1
P10-P17, P21, P23, P30, P31, P36, P37, P40-P47,
P50-P57, P60-P67, P71, P73, P75-P77, P100-P102,
P120, P122-P124
0
0.3 VDD
V
VIL2
P00-P07, P20, P22, P24-P27, P32-P35, P70, P72,
P74, P121, RESET
0
0.2 VDD
V
VOH1
P00-P07, P20-P24, P30-P37, 4.5 V ≤ VDD ≤ 5.5 V,
P40-P47, P50-P57, P60-P67, IOH = –1 mA
P70-P77, P100-P102,
3.5 V ≤ VDD < 4.5 V,
P120-P124
IOH = –100 µA
VDD – 1.0
V
VDD – 0.5
V
VDD – 1.0
V
voltage
High-level output
voltage
Low-level output
VOH2
EO0, EO1
VOH1
P00-P07, P20-P27, P30-P37, 4.5 V ≤ VDD ≤ 5.5 V,
P40-P47, P50-P57, P60-P67, IOL = 1 mA
P70-P77, P100-P102,
3.5 V ≤ VDD < 4.5 V,
P120-P124, P130-P137,
IOL = 100 µA
1.0
V
0.5
V
EO0, EO1
VDD = 4.5 to 5.5 V,
IOL = 3 mA
1.0
V
P00-P07, P10-P17,
P20-P24, P30-P37,
P40-P47, P50-P57,
P60-P67, P70-P77,
P100-P102, P120-P124,
VI = VDD
3
µA
voltage
VOL2
High-level input
leakage current
ILIH
VDD = 4.5 to 5.5 V,
IOH = –3 mA
TYP.
RESET
Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
Data Sheet U12920EJ1V0DS00
27
µPD178F098
DC Characteristics (TA = –40 to +85°C, V DD = 3.5 to 5.5 V)
Parameter
Symbol
Low-level input
Supply
currentNote
Unit
µA
ILOH1
P130-P137
VO = 15 V
–3
µA
ILOL1
P130-P137
VO = 0 V
3
µA
ILOH2
P25-P27
(at N-ch open drain I/O)
VO = VDD
–3
µA
ILOL2
P25-P27
(at N-ch open drain I/O)
VO = 0 V
3
µA
ILOH3
EO0, EO1
VO = VDD
–3
µA
ILOL3
EO0, EO1
VO = 0 V
3
µA
IDD1
When CPU is operating
and PLL is stopped.
Sine wave input to X1 pin
VI = VDD
fx = 4.5 MHz
5.0
18
mA
fx = 6.3 MHz
7.0
20
mA
In HALT mode with PLL
stopped.
Sine wave input to X1 pin
VI = VDD
fx = 4.5 MHz
0.3
0.8
mA
fx = 6.3 MHz
0.4
1.0
mA
5.5
V
IDD4
VDDR1
When crystal resonator is oscillating
3.5
VDDR2
When crystal oscillation is
stopped
Power-failure detection
function
2.2
V
Data memory retained
2.0
V
VDDR3
IDDR1
When crystal oscillation is
stopped
TA = 25°C,
VDD = 5 V
IDDR2
Note
MAX.
–3
IDD3
Data retention
current
TYP.
VI = 0 V
IDD2
Data retention
voltage
MIN.
P00-P07, P10-P17,
P20-P27, P30-P37,
P40-P47, P50-P57,
P60-P67, P70-P77,
P100-P102, P120-P124,
RESET
ILIL
leakage current
Output off
leakage current
Conditions
2.0
4.0
µA
2.0
20
µA
Excluding AVDD current and VDDPLL current.
Remarks 1. fX: System clock oscillation frequency
2. Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
28
Data Sheet U12920EJ1V0DS00
µPD178F098
Reference Characteristics (TA = –40 to +85°C, V DD = 4.5 to 5.5 V)
Parameter
Symbol
Supply current
IDD5
Conditions
MIN.
When CPU and PLL are operating.
Sine wave input to VCOH pin
At fIN = 160 MHz, VIN = 0.15 VP-P
TYP.
MAX.
8
Unit
mA
AC Characteristics
(1) Basic operation (T A = –40 to +85 °C, V DD = 3.5 to 5.5 V)
Parameter
Cycle time
Symbol
TCY
(minimum instruction
execution time)
Conditions
At fX = 6.3 MHz
At fX = 4.5
TI00, TI01 input
high-/low-level
widths
tTIH0,
tTIL0
TI50, TI51 input
fTI5
MHzNote 1
MIN.
TYP.
MAX.
Unit
0.32
5.08
µs
0.44
7.11
µs
4/fsamNote 2
s
2
MHz
frequency
TI50, TI51 input
tTIH5,
high-/low-level
widths
tTIL5
Interrupt input
high-/low-level
widths
tINTH,
tINTL
RESET pin
low-level width
tRSL
INTP0-INTP7
200
ns
1
µs
10
µs
Notes 1. Only when products not using IEBus are supported.
2. fsam = fX/2, fX/4, f X/64 selectable by bits 0 and 1 (PRM00 and PRM01) of the prescaler mode register
0 (PRM0). However, fsam = f X/8 when the valid edge of TI00 is selected as the count clock.
Data Sheet U12920EJ1V0DS00
29
µPD178F098
(2) Serial interface (T A = –40 to +85°C, V DD = 3.5 to 5.5 V)
(a) Serial interface 0
(i) 3-wire serial I/O mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
tKCY1
tKH1,
Test Conditions
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
tKL1
SI0 setup time (to SCK0↑)
SI0 hold time (from SCK0↑)
SO0 output delay time from SCK0↓
Note
tSIK1
VDD = 4.5 to 5.5 V
tKSI1
tKSO1
C = 100 pF
MIN.
TYP.
MAX.
Unit
800
ns
1600
ns
tKCY1/2 – 50
ns
tKCY1/2 – 100
ns
100
ns
150
ns
400
ns
Note
300
ns
MAX.
Unit
C is the load capacitance of SCK0 and SO0 output line.
(ii) 3-wire serial I/O mode (SCK0 ... external clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
tKCY2
tKH2,
Test Conditions
VDD = 4.5 to 5.5 V
TYP.
800
ns
1600
ns
400
ns
tKL2
800
ns
SI0 setup time (to SCK0↑)
tSIK2
100
ns
SI0 hold time (from SCK0↑)
tKSI2
400
ns
SO0 output delay time from SCK0↓
tKSO2
SCK0 at rising or falling edge time
tR2, tF2
Note
30
VDD = 4.5 to 5.5 V
MIN.
C = 100 pF
Note
C is the load capacitance of SO0 output line.
Data Sheet U12920EJ1V0DS00
300
ns
1000
ns
µPD178F098
(iii) SBI mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
tKCY3
tKH3,
Test Conditions
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
tKL3
SB0, SB1 setup time (to SCK0↑)
tSIK3
SB0, SB1 hold time (from SCK0↑)
tKSI3
SB0, SB1 output delay time from
tKSO3
VDD = 4.5 to 5.5 V
R = 1 kΩ
VDD = 4.5 to 5.5 V
C = 100 pF Note
SCK0↓
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
tKCY3/2 – 50
ns
tKCY3/2 – 150
ns
100
ns
300
ns
tKCY3/2
ns
0
250
ns
0
1000
ns
SB0, SB1↓ from SCK0↑
tKSB
tKCY3
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY3
ns
SB0, SB1 high-level width
tSBH
tKCY3
ns
SB0, SB1 low-level width
tSBL
tKCY3
ns
Note R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line.
(iv) SBI mode (SCK0 ... external clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
tKCY4
tKH4,
Test Conditions
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
tKL4
SB0, SB1 setup time (to SCK0↑)
tSIK4
SB0, SB1 hold time (from SCK0↑)
tKSI4
SB0, SB1 output delay time from
tKSO4
VDD = 4.5 to 5.5 V
R = 1 kΩ
VDD = 4.5 to 5.5 V
C = 100 pF Note
SCK0↓
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
300
ns
tKCY4/2
ns
0
250
ns
0
1000
ns
SB0, SB1↓ from SCK0↑
tKSB
tKCY4
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY4
ns
SB0, SB1 high-level width
tSBH
tKCY4
ns
SB0, SB1 low-level width
tSBL
tKCY4
ns
SCK0 at rising or falling edge time
Note
tR4, tF4
1000
ns
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
Data Sheet U12920EJ1V0DS00
31
µPD178F098
(v) 2-wire serial I/O mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY5
SCK0 high-level width
tKH5
SCK0 low-level width
tKL5
SB0, SB1 setup time (to SCK0↑)
Test Conditions
R = 1 kΩ
C = 100 pF
Note
VDD = 4.5 to 5.5 V
tSIK5
VDD = 4.5 to 5.5 V
MIN.
TYP.
MAX.
Unit
1600
ns
tKCY5/2 – 160
ns
tKCY5/2 – 50
ns
tKCY5/2 – 100
ns
300
ns
350
ns
ns
SB0, SB1 hold time (from SCK0↑)
tKSI5
600
SB0, SB1 output delay time from
tKSO5
0
300
ns
SCK0↓
Note
R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line.
(vi) 2-wire serial I/O mode (SCK0 ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY6
1600
ns
SCK0 high-level width
tKH6
650
ns
SCK0 low-level width
tKL6
800
ns
SB0, SB1 setup time (to SCK0↑)
tSIK6
100
ns
SB0, SB1 hold time (from SCK0↑)
tKSI6
tKCY6/2
ns
SB0, SB1 output delay time from
tKSO6
SCK0↓
C = 100 pF
SCK0 at rising or falling edge time
Note
32
R = 1 kΩ
VDD = 4.5 to 5.5 V
Note
0
300
ns
0
500
ns
1000
ns
tR6, tF6
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
Data Sheet U12920EJ1V0DS00
µPD178F098
(vii) I 2C Bus mode (SCL ... internal clock output)
Parameter
SCL cycle time
Symbol
tKCY7
Test Conditions
R = 1 kΩ
C = 100 pF
Note
MIN.
TYP.
MAX.
Unit
10
µs
tKCY7 – 160
ns
SCL high-level width
tKH7
SCL low-level width
tKL7
tKCY7 – 50
ns
SDA0, SDA1 setup time (to SCL↑)
tSIK7
200
ns
SDA0, SDA1 hold time
(from SCL↓)
tKSI7
0
ns
SDA0, SDA1 output delay time
tKSO7
VDD = 4.5 to 5.5 V
(from SCL↓)
0
300
ns
0
500
ns
SDA0, SDA1↓ from SCL↑ or
SDA0, SDA1↑ from SCL↑
tKSB
200
ns
SCL↓ from SDA0, SDA1↓
tSBK
400
ns
SDA0, SDA1 high-level width
tSBH
500
ns
Note
R and C are the load resistance and load capacitance of SCL, SDA0 and SDA1 output line.
(viii) I2 C Bus mode (SCL ... external clock input)
Parameter
SCL cycle time
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
tKCY8
1000
ns
tKH8, tKL8
400
ns
SDA0, SDA1 setup time (to SCL↑)
tSIK8
200
ns
SDA0, SDA1 hold time
(from SCL↓)
tKSI8
0
ns
SDA0, SDA1 output delay time
tKSO8
SCL high-/low-level width
from SCL↓
R = 1 kΩ
C = 100 pF
VDD = 4.5 to 5.5 V
Note
0
300
ns
0
500
ns
SDA0, SDA1↓ from SCL↑ or
SDA0, SDA1↑ from SCL↑
tKSB
200
ns
SCL↓ from SDA0, SDA1↓
tSBK
400
ns
SDA0, SDA1 high-level width
tSBH
500
ns
SCL at rising or falling edge time
Note
tR8, tF8
1000
ns
R and C are the load resistance and load capacitance of SDA0 and SDA1 output line.
Data Sheet U12920EJ1V0DS00
33
µPD178F098
(b) Serial interface 1
(i) 3-wire serial I/O mode (SCK1 ... internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
tKCY9
800
ns
SCK1 high/low-level width
tKH9,
tKL9
tKCY9/2 – 50
ns
SI1 setup time (to SCK1↑)
tSIK9
100
ns
SI1 hold time (from SCK1↑)
tKSI9
400
ns
SO1 output delay time (from SCK1↓)
tKSO9
Note
C = 100 pF Note
300
ns
MAX.
Unit
C is the load capacitance of SCK1 and SO1 output line.
(ii) 3-wire serial I/O mode (SCK1 ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
SCK1 cycle time
tKCY10
800
ns
SCK1 high/low-level width
tKH10,
tKL10
400
ns
SI1 setup time (to SCK1↑)
tSIK10
100
ns
SI1 hold time (from SCK1↑)
tKSI10
400
ns
SO1 output delay time (from SCK1↓)
tKSO10
C = 100 pF Note
SCK1 at rising or falling edge time tR10, tF10
Note
34
C is the load capacitance of SO1 output line.
Data Sheet U12920EJ1V0DS00
300
ns
1000
ns
µPD178F098
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... internal clock
output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
tKCY11
800
ns
SCK1 high/low-level width
tKH11,
tKL11
tKCY11/2 – 50
ns
SI1 setup time (to SCK1↑)
tSIK11
100
ns
SI1 hold time (from SCK1↑)
tKSI11
400
ns
SO1 output delay time (from SCK1↓)
tKSO11
C = 100 pF Note
300
ns
STB↑ from SCK1↑
tSBD
tKCY11/2 – 100
tKCY11/2 + 100
ns
Strobe signal high-level width
tSBW
tKCY11/2 – 30
tKCY11/2 + 30
ns
Busy signal setup time
tBYS
100
ns
Busy signal hold time
(from busy signal detection timing)
tBYH
100
ns
SCK1↓ from busy inactive
tSPS
200
ns
(to busy signal detection timing)
Note
C is the load capacitance of SO1 output line.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... external clock
input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
tKCY12
800
ns
SCK1 high/low-level width
tKH12,
tKL12
400
ns
SI1 setup time (to SCK1↑)
tSIK12
100
ns
SI1 hold time (from SCK1↑)
tKSI12
400
ns
SO1 output delay time (from SCK1↓)
tKSO12
C = 100 pF Note
SCK1 at rising or falling edge time tR12, tF12
Note
300
ns
1000
ns
C is the load capacitance of SO1 output line.
Data Sheet U12920EJ1V0DS00
35
µPD178F098
(c) Serial interface 3
(i) 3-wire serial I/O mode (SCK3 ... internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK3 cycle time
tKCY13
800
ns
SCK3 high/low-level width
tKH13,
tKL13
tKCY13/2 – 50
ns
SI3 setup time (to SCK3↑)
tSIK13
100
ns
SI3 hold time (from SCK3↑)
tKSI13
400
ns
SO3 output delay time (from SCK3↓)
tKSO13
Note
C = 100 pF Note
300
ns
MAX.
Unit
C is the load capacitance of SCK3 and SO3 output line.
(ii) 3-wire serial I/O mode (SCK3 ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
SCK3 cycle time
tKCY14
800
ns
SCK3 high/low-level width
tKH14,
tKL14
400
ns
SI3 setup time (to SCK3↑)
tSIK14
100
ns
SI3 hold time (from SCK3↑)
tKSI14
400
ns
SO3 output delay time (from SCK3↓)
tKSO14
C = 100 pF Note
SCK3 at rising or falling edge time tR14, tF14
Note
300
ns
1000
ns
MAX.
Unit
38400
bps
C is the load capacitance of SO3 output line.
(d) Serial interface UART0 (Dedicated baud rate generator output)
Parameter
Symbol
Test Conditions
Transfer rate
36
Data Sheet U12920EJ1V0DS00
MIN.
TYP.
µPD178F098
AC Timing Test Point (Excluding X1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
TI Timing
tTIL0
tTIH0
TI00, TI01
1/fTI5
tTIL5
tTIH5
TI50,TI51
Interrupt Input Timing
tINTL
tINTH
INTP0 to INTP7
RESET Input Timing
tRSL
RESET
Data Sheet U12920EJ1V0DS00
37
µPD178F098
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
tFn
tRn
SCK0, SCK1, SCK3
tSIKm
SI0, SI1, SI3
tKSIm
Input Data
tKSOm
SO0, SO1, SO3
Output Data
Remark m = 1, 2, 9, 10, 13, 14
n = 2, 10, 14
SBI mode (bus release signal transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tF4
tR4
SCK0
tKSB
tSBL
tSBH
tSIK3, 4
tSBK
tKSI3, 4
SB0, SB1
tKSO3, 4
38
Data Sheet U12920EJ1V0DS00
µPD178F098
SBI mode (command signal transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tF4
tR4
SCK0
tSIK3, 4
tKSI3, 4
tSBK
tKSB
SB0, SB1
tKSO3, 4
2-wire serial I/O mode:
tKCY5, 6
tKL5, 6
tKH5, 6
tR6
tF6
SCK0
tSIK5, 6
tKSI5, 6
tKSO5, 6
SB0, SB1
I 2C bus mode:
tF8
tR8
tKCY7, 8
SCL
tKL7, 8
tKSI7, 8
tKH7, 8
tSIK7, 8
tKSO7, 8
tKSB
tKSB
tSBK
SDA0, SDA1
tSBH
tSBK
Data Sheet U12920EJ1V0DS00
39
µPD178F098
3-wire serial I/O mode with automatic transmit/receive function:
SO1
SI1
D2
D1
D2
D1
D0
D7
D0
D7
tKSI11, 12
tKH11, 12
tF12
tSIK11, 12
tKSO11, 12
SCK1
tR12
tSBD
tKL11, 12
STB
tSBW
tKCY11, 12
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK1
7
9 Note
8
10 Note
tBYS
10 + n Note
tBYH
1
tSPS
BUSY
(Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
IEBus Controller Characteristics (T A = –40 to +85 °C, V DD = 3.5 to 5.5 V)
Parameter
IEBus system
clock frequency
Note
Symbol
fs
Conditions
MIN.
TYP.
6.3Note
Fixed to mode 1
Unit
MHz
Although the system clock frequency is 6.0 MHz in the IEBus standard, in these products, normal
operation is guaranteed at 6.3 MHz.
Remark 6.0 MHz and 6.3 MHz cannot both be used as the IEBus system clock frequency.
40
MAX.
Data Sheet U12920EJ1V0DS00
µPD178F098
A/D Converter Characteristics (T A = –40 to +85 °C, V DD = AV DD = 3.5 to 5.5 V)
Parameter
Symbol
Conditions
Resolution
Total conversion
MIN.
TYP.
MAX.
Unit
8
8
8
bit
±1.0
%FSR
±1.4
%FSR
VDD = 4.5 to 5.5 V
errorNotes 1, 2
Conversion time
tCONV
15.2
45.7
µs
Analog input voltage
VIAN
0
VDD
V
MAX.
Unit
Notes 1. Excluding quantization error (±0.2%FSR)
2. This value is indicated as a ratio to the full-scall value.
PLL Characteristics (T A = –40 to +85°C, V DD = 4.5 to 5.5 V)
Parameter
Operating
frequency
Symbol
Conditions
MIN.
TYP.
fIN1
VCOL pin, MF mode, sine wave input, VIN = 0.15 VP-P
0.5
3.0
MHz
fIN2
VCOL pin, HF mode, sine wave input, VIN = 0.15 VP-P
10
40
MHz
fIN3
VCOH pin, VHF mode, sine wave input, VIN = 0.15 VP-P
60
130
MHz
fIN4
VCOH pin, VHF mode, sine wave input, VIN = 0.3 VP-P
40
160
MHz
Remark The above values are the result of NEC’s evaluation of the device. If the device is likely to be affected
by noise in your application, it is recommended to use the device at a voltage higher than the above
values.
IFC Characteristics (T A = –40 to +85°C, V DD = 4.5 to 5.5 V)
Parameter
Operating
frequency
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
fIN5
AMIFC pin, AMIF count mode, sine wave input,
VIN = 0.15 VP-P
0.4
0.5
MHz
fIN6
FMIFC pin, FMIF count mode, sine wave input,
VIN = 0.15 VP-P
10
11
MHz
fIN7
FMIFC pin, AMIF count mode, sine wave input,
VIN = 0.15 VP-P
0.4
0.5
MHz
Remark The above values are the result of NEC’s evaluation of the device. If the device is likely to be affected
by noise in your application, it is recommended to use the device at a voltage higher than the above
values.
Data Sheet U12920EJ1V0DS00
41
µPD178F098
Flash Memory Programming Characteristics (V DD = 3.5 to 5.5 V, TA = 10 to 40 °C)
(1) Write/delete characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Write current (VDD pin)Note
tDDW
When VPP = VPP1, fX = 6.3 MHz
23
mA
Write current (VPP pin)Note
IPPW
When VPP = VPP1, fX = 6.3 MHz
20
mA
Delete current (VDD pin)Note
IDDE
When VPP = VPP1, fX = 6.3 MHz
23
mA
Delete current (VPP pin)Note
IPPE
When VPP = VPP1
100
mA
Unit delete time
tER
1
s
Total delete time
tERA
20
s
Number of overwrite
CWRT
Delete and write are counted as one cycle
20
times
VPP power supply voltage
VPP0
In normal mode
0.2 VDD
V
VPP1
At flash memory programming
10.3
V
Note
0.5
1
0
9.7
10.0
AVDD current and Port current (current flowing to internal pull-up resistor) are not included.
Remark fX: System clock oscillation frequency
(2) Serial write operation characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPP setup time
tPSRON
VPP high voltage
1.0
µs
VPP↑ setup time from VDD↑
tDRPSR
VPP high voltage
1.0
µs
RESET↑ setup time from VPP↑
tPSRRF
VPP high voltage
1.0
µs
VPP count start time from RESET↑
tRFCF
1.0
µs
Count execution time
tCOUNT
2.0
ms
VPP counter high-level width
tCH
8.0
µs
VPP counter low-level width
tCL
8.0
µs
VPP counter noise elimination width
42
tNFW
40
Data Sheet U12920EJ1V0DS00
ns
µPD178F098
Flash Write Mode Setting Timing
VDD
VDD
0V
tDRPSR
tRFCF
tCH
VPPH
VPP
VPP
tCL
VPPL
tPSRON tPSRRF
tCOUNT
VDD
RESET (input)
0V
Data Sheet U12920EJ1V0DS00
43
µPD178F098
8. PACKAGE DRAWING
100-PIN PLASTIC QFP (14x20)
A
B
51
50
80
81
detail of lead end
S
C D
Q
R
31
30
100
1
F
G
J
H
I
M
P
K
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
23.6±0.4
B
20.0±0.2
C
14.0±0.2
D
17.6±0.4
F
0.8
G
H
0.6
0.30±0.10
I
0.15
J
K
L
0.65 (T.P.)
1.8±0.2
0.8±0.2
M
0.15+0.10
−0.05
N
0.10
P
2.7±0.1
Q
R
S
0.1±0.1
5°±5°
3.0 MAX.
P100GF-65-3BA1-4
44
Data Sheet U12920EJ1V0DS00
µPD178F098
9. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions.
For details of the recommended soldering conditions, refer to information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended, consult NEC.
Table 9-1. Soldering Conditions for Surface-Mount Type
µPD178F098GF-3BA: 100-pin plastic QFP (14 × 20)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 sec max. (210°C min.),
Recommended
Conditions Symbol
IR35-00-3
Number of times: 3 max.
VPS
Package peak temperature: 215°C, Time: 40 sec max. (200°C min.),
VP15-00-3
Number of times: 3 max.
Wave soldering
Solder bath temperature: 260°C max., Time: 10 sec max.,
Number of times: 1, Preheating temperature: 120°C max.,
(Package surface temperature)
Partial heating
Pin temperature: 300°C max., Time: 3 sec max (per device side)
WS60-00-1
–
Caution Do not use two or more soldering methods in combination (except partial heating).
Data Sheet U12920EJ1V0DS00
45
µPD178F098
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for development of systems using the µPD178078 and 178098
subseries.
Language processor software
RA78K/0Notes 1, 2, 3
Assembler package common to 78K/0 series
CC78K/0Notes 1, 2, 3
C compiler package common to 78K/0 series
DF178098Notes 1, 2, 3
Device file for µPD178078 subseries and µPD178098 subseries
CC78K0-LNotes 1, 2, 3
C compiler library source file common to 78K/0 series
Flash memory writing tools
Fashpro III
(Part number:
FL-PR3Note 4, PG-FL3)
Dedicated flash programmer
FA-100GF-3BANote 4
Flash programmer adapter
Debugging tools
• When in-circuit emulator IE-78K0-NS is used
IE-78K0-NS
In-circuit emulator common to 78K/0 series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PA
Performance board for enhancing and expanding the IE-78K0-NS function
IE-70000-98-IF-C
Interface adapter necessary when PC-9800 series (except notebook type) is used as host machine
(C bus supported)
IE-70000-CD-IF-A
PC card and interface cable necessary when a notebook-type PC is used as host machine (PCMCIA
socket supported)
IE-70000-PC-IF-C
Interface adapter necessary when a IBM PC/ATTM compatible machine is used as host machine (ISA
bus supported)
IE-70000-PCI-IF
Interface adapter necessary when a PC with a PCI bus is used as host machine
IE-178098-NS-EM1
Emulation board to emulate µPD178078 and 178098 subseries
NP-100GFNote 4
Emulation probe for 100-pin plastic QFP (GF-3BA type)
EV-9200GF-100
Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type)
SM78K0Notes 1, 2
System simulator common to 78K/0 series
ID78K0-NSNotes 1, 2
Integrated debugger common to 78K/0 series
DF178098Notes 1, 2, 3
Device file for µPD178078 subseries and µPD178098 subseries
Notes 1. PC-9800 series (Japanese WindowsTM) based
2. IBM PC/AT compatible machine (Japanese/English windows) based
3. HP9000 series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM, SolarisTM) based, NEWSTM
(NEWS-OSTM) based
4. Products of Naito Densei Machida Mfg. Co., Ltd. (Tel: 044-822-3813).
Remark Use the RA78K0, CC78K0, and SM78K0 in combination with the DF178098.
46
Data Sheet U12920EJ1V0DS00
µPD178F098
• When in-circuit emulator IE-78001-R-A is used
IE-78001-R-A
In-circuit emulator common to 78K/0 series
IE-70000-98-IF-C
Interface adapter necessary when PC-9800 series (except notebook type) is used as host machine
(C bus supported)
IE-70000-PC-IF-C
Interface adapter necessary when IBM PC/AT compatible machine is used as host machine (ISA
bus supported)
IE-70000-PCI-IF
Interface adapter necessary when a PC with a PCI bus is used as host machine
IE-78000-R-SV3
Interface adapter and cable necessary when EWS is used as host machine
IE-178098-NS-EM1
Emulation board to emulate µPD178078 and 178098 subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary when using IE-178098-NS-EM1 on IE-78001-R-A
EP-78064GF-R
Emulation probe for 100-pin plastic QFP (GF-3BA type)
EV-9200GF-100
Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type)
SM78K0Notes 1, 2
System simulator common to 78K/0 series
ID78K0Notes 1, 2
Integrated debugger common to 78K/0 series
DF178098Notes 1, 2, 3
Device file for µPD178078 subseries and µPD178098 subseries
Real-time OS
RX78K/0Notes 1, 2, 3
Real-time OS for 78K/0 series
MX78K0Notes 1, 2, 3
OS for 78K/0 series
Notes 1. PC-9800 series (Japanese Windows) based
2. IBM PC/AT compatible machine (Japanese/English windows) based
3. HP9000 series 700 (HP-UX) based, SPARCstation (SunOS, Solaris) based, NEWS (NEWS-OS)
based
Remark Use the SM78K0 in combination with the DF178098.
Data Sheet U12920EJ1V0DS00
47
µPD178F098
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Device Documents
Document No.
Title
Japanese
English
µPD178076, 178078, 178096, 178098 Data Sheet
U12885J
U12885E
µPD178F098 Data Sheet
U12920J
This document
µPD178078, 178098 Subseries User’s Manual
U12790J
U12790E
78K/0 Series User’s Manual - Instruction
U12326J
U12326E
U12704J
U12704E
U14458J
U14458E
78K/0 Series Application Note
Basics (I)
78K/0, 78K/0S Series Flash Memory Write Application Note
Development Tool Documents (User’s Manual)
Document No.
Title
Japanese
RA78K0 Assembler Package
English
Operation
U11802J
U11802E
Assembly Language
U11801J
U11801E
Structured Assembly
U11789J
U11789E
Operation
U11517J
U11517E
Language
U11518J
U11518E
IE-78001-R-A
U14142J
To be prepared
IE-78K0-NS
U13731J
U13731E
IE-178098-NS-EM1
U14013J
U14013E
EP-78064
EEU-934
EEU-1469
Language
CC78K0 C Compiler
SM78K0 System Simulator Windows Based
Reference
U10181J
U10181E
SM78K Series System Simulator
External Parts User
Open Interface
Specifications
U10092J
U10092E
ID78K0 Integrated Debugger EWS Based
Reference
U11151J
—
ID78K0 Integrated Debugger PC Based
Reference
U11539J
U11539E
ID78K0 Integrated Debugger Windows Based
Guide
U11649J
U11649E
ID78K0-NS Integrated Debugger Windows Based
Reference
U12900J
U12900E
Operation
U14379J
To be prepared
Caution The contents of the above documents are subject to change without notice. Please ensure that
the latest versions are used in design work, etc.
48
Data Sheet U12920EJ1V0DS00
µPD178F098
Related Documents for Embedded Software (User’s Manual)
Document No.
Title
Japanese
78K/0 Series Real-time OS
78K/0 Series OS MX78K0
English
Fundamental
U11537J
U11537E
Installation
U11536J
U11536E
Fundamental
U12257J
U12257E
Other Documents
Document No.
Title
Japanese
English
SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Guides on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability and Quality Control
C10983J
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892J
C11892E
Semiconductor Device Quality/Reliability Handbook
C12769J
—
Microcomputer Product Series Guide
U11416J
—
Caution The contents of the above documents are subject to change without notice. Ensure that the
latest versions are used in design work, etc.
Data Sheet U12920EJ1V0DS00
49
µPD178F098
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material.
All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to V DD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
Purchase of NEC I 2C components conveys a license under the Philips I2 C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
IEBus is a trademark of NEC Corporation.
Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/
or other countries.
PC/AT is a trademark of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
50
Data Sheet U12920EJ1V0DS00
µPD178F098
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U12920EJ1V0DS00
51
µPD178F098
• The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4