OKI MSM9553

¡ Semiconductor
MSM9552/MSM9553
¡ Semiconductor
MSM9552/MSM9553
LSI for FM Multiplex Data Demodulation
GENERAL DESCRIPTION
The MSM9552 and MSM9553 are LSI devices which demodulate FM character multiplex signals in
the DARC (DAta Radio Channel)* format to acquire digital data. The MSM9552 and MSM9553
operate on 5V and 3V, respectively. In the DARC format, baseband signals at ordinary FM
broadcasting frequencies are multiplexed with 16k-bps digital data which are L-MSK-modulated at
76kHz.
Each of the MSM9552 and MSM9553 has a bandpass filter consisting of SCF, frame synchronization circuit, error correction circuit, etc. on a single chip.
So, a system for acquisition of digital data can be easily constructed by externally mounting an FM
receiver tuner, microcontroller for control, and memory for temporary storage of data.
The MSM9552 and MSM9553 have a simple configuration, and are equipped with only necessary
functions. By making changes to software for the external microcontroller, the MSM9552 and
MSM9553 can meet the various requirements of FM multiplex broadcasting services which will be
offered in future.
These LSI devices are best suited to the radio sets and information devices for FM character multiplex
broadcasting, which started in Japan in October 1994. Especially, the MSM9553 is suitable for
portable units.
* DARC is a registered trademark of NHK ENGINEERING SERVICES, INC.
Note that a contract needs to be made with NHK Engineering Service if a manufacturer produces/
sells electronic equipment utilizing the DARC technology.
FEATURES
• Built-in bandpass filter (SCF)
• Built-in block synchronization circuit and frame synchronization circuit
• Setting of the number of synchronization protecting stages
• Regeneration of data clocks by digital PLL
• 1T delay detection
• Built-in error correction circuit
• Built-in layer 4 and layer 2 CRC check circuit
• Microcontroller parallel interface
• Clock output for external devices (64kHz to 8.192MHz selectable)
• International standard frame format
• Power source:
5V (MSM9552), 3V (MSM9553)
• Package
44-pin plastic QFP (QFP44-P-910-0.80-2K)
1
LPF
+
Clock
regeneration
–
Block
synchronization
Frame
synchronization
Timing
control
MSM9552/MSM9553
AIN
BPF
(SCF)
BLOCK DIAGRAM
2
Limitter
Variable
gain
AMP
Vref
SG
Filter
PN
descrambler
34Byte RAM
¥
2
Read
write
register
Error
correction,
Lay 2 CRC
Layer 4 CRC
LSI internal
clock
DB2
WR31
D
CK
Q
Data bus
1T delay
circuit
CLR
DVDD
Addressbus
Limitter
Frequency
divider
Digital Signal
Processor
CPU interface
+
–
Delay Detection
XOUTC
XOUT
XTAL2
XTAL1
Data bus
DB0-DB7
Address
AD0-AD5
RD
WR
CS
CLR
INT
¡ Semiconductor
LPF
¡ Semiconductor
MSM9552/MSM9553
44
MON
A1
A2
A3
A4
A5
NC
CLR
IORD
IOWR
NC
NC
PIN CONFIGURATION (TOP VIEW)
34
1
33
ADETIN
A0
XOUT
CS
AVDD
AGND
XTAL2
SG
XTAL1
AIN
DVDD
XOUTC
DGND
MOUT0
DB7
MOUT1
DB6
MOUT2
DB5
11
23
DB2
DB1
RD
DB0
NC
INT
WR
MOUT6
22
MOUT5
MOUT4
12
DB4
DB3
MOUT3
44-Pin Plastic QFP
Note:
Leave the NC pins open.
3
MSM9552/MSM9553
¡ Semiconductor
PIN DESCRIPTION
Function
Microcontroller
interface
Tuner
interface
Analog
section test
Digital
section test
Clock
Power
supply
4
Symbol
Pin
Type
Description
WR
16
I
Write signal to internal register
RD
18
I
Read signal to internal register
INT
15
O
Interrupt signal to microcontroller. "L": Occurrence of an
interrupt
CS
31
I
Chip select signal.
"L": Read, write, and data bus signals valid
CLR
40
I
"L" initializes internal registers, and the device enters
power down mode
A0 to A5
33 to 38
I
Address signal to internal register
DB0 to DB7
19 to 26
I/O
AIN
6
I
FM multiplex signal input
SG
5
O
Analog reference voltage output pin. To prevent noise,
connect a capacitor between this pin and analog ground.
MON
1
O
Analog section waveform monitor pin. The analog block is
specified by the analog control register.
Data bus signal to internal register
ADETIN
2
I
Analog signal input pin for testing
IORD
IOWR
41
42
I
Digital section test signal input pins. Internally pulled up.
MOUT0 to
MOUT6
8 to 14
O
Digital section test signal output and monitor output pins
XTAL1
29
I
8.192MHz crystal oscillator connection pin
XTAL2
30
O
8.192MHz crystal oscillator connection pin
XOUT
32
O
Pin for supply of 64kHz to 8.192MHz clock to the outside
XOUTC
7
I
XOUT output control pin.
"L"=Clock output, "H"=Output disabled. Pulled up internally.
AVDD
3
—
Analog section power supply pin
AGND
4
—
Analog ground pin
DVDD
28
—
Digital section power supply pin
DGND
27
—
Digital ground pin
¡ Semiconductor
MSM9552/MSM9553
ABSOLUTE MAXIMUM RATINGS (MSM9552)
Parameter
Power supply voltage
Symbol
AVDD
DVDD
Input voltage
Output voltage
VI
VO
Maximum power dissipation
PD
Storage temperature
Condition
Rating
Unit
–0.3 to +7.0
AVDD=DVDD
Ta=25°C
Ta=25°C per package
400
Ta=25°C per output
50
—
–55 to +150
TSTG
V
–0.3 to AVDD+0.3
–0.3 to DVDD+0.3
mW
°C
RECOMMENDED OPERATING CONDITIONS (MSM9552)
Symbol
Condition
Range
Unit
Applied Pin
Power supply voltage
AVDD
DVDD
AVDD=DVDD
4.5 to 5.5
V
AVDD
DVDD
Crystal frequency
fXTAL
—
8.192MHz ±100ppm
—
XTAL1
XTAL2
FM multiplex signal input
voltage
VAIN
0.5 to 2
VP-P
AIN
Operating temperature
TOP
Composite signals,
including multiplex
signals
—
–40 to +85
°C
—
Parameter
ELECTRICAL CHARACTERISTICS (MSM9552)
Parameter
Current consumption
Min. Typ. Max. Unit Applied Pin
Symbol
Condition
IDD
During operation, No load
f=8.192MHz
—
16
32
mA
During power down, No load
—
—
20
mA
AVDD
DVDD
BPF pass band attenuation
GAIN1
72 - 80kHz
Variable gain amplifier
gain: 0dB
—
—
3.0
dB
MON
BPF reject band attenuation
GAIN2
0 - 53kHz
Variable gain amplifier
gain: 0dB
50
—
—
dB
MON
BPF reject band attenuation
GAIN3
100 - 500kHz
Variable gain amplifier
gain: 0dB
50
—
—
dB
MON
5
MSM9552/MSM9553
¡ Semiconductor
ABSOLUTE MAXIMUM RATINGS (MSM9553)
Parameter
Symbol
AVDD
DVDD
Power supply voltage
Input voltage
Output voltage
VI
VO
Maximum power dissipation
PD
Storage temperature
Condition
Rating
Unit
–0.3 to +7.0
AVDD=DVDD
Ta=25°C
Ta=25°C per package
400
Ta=25°C per output
50
—
–55 to +150
TSTG
V
–0.3 to AVDD+0.3
–0.3 to DVDD+0.3
mW
°C
RECOMMENDED OPERATING CONDITIONS (MSM9553)
Symbol
Condition
Range
Unit
Applied Pin
Power supply voltage
AVDD
DVDD
AVDD=DVDD
2.7 to 3.3
V
AVDD
DVDD
Crystal frequency
fXTAL
—
8.192MHz ±100ppm
—
XTAL1
XTAL2
FM multiplex signal input
voltage
VAIN
0.2 to 0.9
VP-P
AIN
Operating temperature
TOP
Composite signals,
including multiplex
signals
—
–20 to +75
°C
—
Parameter
ELECTRICAL CHARACTERISTICS (MSM9553)
Parameter
Current consumption
Condition
IDD
During operation, No load
f=8.192MHz
—
13
22
mA
During power down, No load
—
—
10
mA
AVDD
DVDD
BPF pass band attenuation
GAIN1
72 - 80kHz
Variable gain amplifier
gain: 0dB
—
—
3.0
dB
MON
BPF reject band attenuation
GAIN2
0 - 53kHz
Variable gain amplifier
gain: 0dB
50
—
—
dB
MON
GAIN3
100 - 500kHz
Variable gain amplifier
gain: 0dB
50
—
—
dB
MON
(1)
BPF reject band attenuation
(2)
6
MIN TYP MAX Unit Applied Pin
Symbol
¡ Semiconductor
APPLICATION CIRCUIT
MSM9552
FM
tuner
FM multiplex
data demodulation
LSI
8 bits
MSM6794 x 2
LCD control
driver
MCU
CPU
ROM
Buffer
RAM
Font
ROM
16 Chinese
characters
x 2 lines
LCD display
MSM6794: LCD driver with built-in 128-channel
RAM for liquid crystal dot matrix
MSM9552/MSM9553
7