FEDL9845DIGEST-01 1Semiconductor MSM9845 Version 3.10, Dec 4, 2000 VOICE SYNTHESIS LSI with on-chip FIFO Memory This document contains minimum specifications. For full specifications, please contact your nearest Oki office or representative. GENERAL DESCRIPTION MSM9845 is a Voice Synthesizer LSI with on-chip FIFO memory. A newly developed synthesis algorithm, OKI ADPCM2, promises superb sound quality. The LSI is fully controllable from an external CPU via 16/8-bit bus interface. MSM9845 is an ideal choice for application systems where such non-microchip data storage as CD ROM is used. FEATURES • 16/8-bit Bus Interface • On-chip FIFO Memory Capacity : 1024 Bits 16 ms Buffering When Sampling Frequency at 16.0 kHz, 4-bit ADPCM2 and Monaural Playback selected • Synthesis Algorithms for User's Selection 4, 5, 6, 7, 8-bit Oki ADPCM2 4-bit Oki ADPCM 8/16-bit Straight PCM 8-bit Oki Non-Linear PCM • Oscillation Clock Frequency: 16.9344 MHz/24.576 MHz • Sampling Frequency: 11.025 kHz, 22.05 kHz, 44.1 kHz at fOSC = 16.9344 MHz 4.0 kHz, 6.4 kHz, 8.0 kHz, 12.8 kHz, 16.0 kHz, 32.0 kHz, 48.0 kHz at fOSC = 24.576 MHz • Sound Level Control (8 levels, 0 dB to –21 dB) • Built-in 14-bit D/A Converter • 3 types of Serial Interface for External DAC • Sampling Rate Conversion Function • Packaging: 56-pin Plastic QFP (QFP56-P-910-0.65-2K) Product Code: MSM9845GA DIFFERENCE BETWEEN MSM9845 AND MSM9844 ITEM MSM9845GA MSM9844GA SRC On-Chip FIR Filter Not On-Chip FIR Filter 1/9 FEDL9845DIGEST-01 1Semiconductor MSM9845 D0 D1 D2 D3 DVDD 43 SlOCK 44 DASD 45 TEST2 46 VCK 47 TEST0 48 TEST1 50 DACKL 49 DGND 52 lOW 51 DREQL 53 NC 55 XT 54 XT 56 NC PIN CONFIGURATION (TOP VIEW) 1 42 BUSY 2 3 4 41 40 39 D/C CS RD WR FUL/DREQR D4 6 38 37 D5 D6 7 8 36 35 MID D7 9 CH/DACKR NC 10 34 33 D8 11 D9 D10 D11 12 32 31 13 14 30 29 EMP RESET CBUSY DVDD AVDD AOUTR AOUTL 28 24 25 TEST3 26 NC 27 NC NC 20 21 AGND 22 NC 23 DGND NC D14 18 D15 19 NC 15 D12 16 D13 17 5 NC : No Connection 56-Pin Plastic QFP 2/9 FEDL9845DIGEST-01 1Semiconductor MSM9845 DAC LPF DAC LPF FIFO Volume Controller LPF (FIR) D15 to D0 WR RD CS D/C BUSY CBUSY AVDD AGND DVDD DGND Serial Port EMP MID FUL/DREQR CH/DACKR AOUTL AOUTR BLOCK DIAGRAM SRC MCU I/F VCK SIOCK DASD ADPCM2 / ADPCM / PCM Synthesizer Timing Controller DMA I/F TEST0 TEST1 TEST2 TEST3 XT XT IOW DACKL DREQL RESET 3/9 FEDL9845DIGEST-01 1Semiconductor MSM9845 PIN DESCRIPTION Pin 11 - 14 16 - 19 1-4 Symbol D15 to D8 Type I/O Description When 8-bit bus interface selected, you can define, by using a command, these pins as input/output to/from external memory. When no definition made, these pins are input mode. When 16-bit bus interface selected, they are one half of bi-directional data bus for data input/output from/to external micro-controller and memory. Another half of bi-directional data bus for data input/output from/to external micro-controller and memory and for status output. D7 to D0 I/O 38 WR I WRITE pulse input pin. Input “L” pulse before you can enter command and data to D15 to D0 pins. 39 RD I READ pulse input pin. Input “L” pulse before the LSI can output status and data to D15 to D0 pins. 40 CS I With this pin at “L” level, the LSI accepts WRITE or READ pulse input. At “H” level the LSI would not accept WRITE or READ pulse. 41 D/C I While this pin being held “H”, D15 to D0 pins are enabled to input/output sound data. While this pin being held “L”, D7 to D0 pins are enabled to input a command or output status data. 42 BUSY O Output “L” level during playback/PAUSE operation. 32 CBUSY O Output “L” level when the LSI is ready to accept a command. O “H” level output from this pin indicates FIFO memory is empty. You can change this pin to “L” active by a command input. 6-9 35 EMP “H” level output from this pin indicates FIFO memory is more than half. 36 MID O During playback, voice synthesis starts when MID changes to “H” level. You can change this pin to “L” active by a command input. This pin outputs a synchro signal for voice data input / output when non-use of FIFO is selected. “H” level output from this pin indicates FIFO memory is full. During playback operation this pin is held “H” and FIFO memory is write -disabled. 37 34 FUL/ DREQR CH/ DACKR You can change this pin to “L” active by a command input. O I When DMA Transfer and stereo-playback selected by the command input, the output from this pin becomes DMA Transfer request signal. The pin outputs “H” when the right channel FIFO memory is empty. You can change this pin to “L” active by a command input. When stereo-playback selected, write sound data to the right channel FIFO at “H” level, while data to the left channel FIFO at “L” level. When monaural playback selected, keep this pin “L”. You can change this pin to “L” active by a command input. When DMA Transfer and stereo-playback selected by the command input, this pin acknowledges the right channel DMA Transfer permission signal. With this pin at “L” level the LSI enabled the IOW pin to accept the signal. You can change this pin to “H” active by a command input. 51 DREQL O Output “H” level to represent DMA Transfer request signal when FIFO gets empty. If stereo-playback selected, the pin outputs “H” level to represent DMA Transfer request signal when the left channel FIFO gets empty. 4/9 FEDL9845DIGEST-01 1Semiconductor Pin Symbol MSM9845 Type Description 50 DACKL I DMA Transfer Permission Acknowledgement signal. With this pin at “L” level the LSI enables the IOW pin to accept the signal. When stereo-playback selected, the pin acknowledges DMA Transfer permission signal for the left channel FIFO. You can change this pin to “H” active by a command input. When DMA Transfer is not in use, keep the pin “H”. 52 IOW I When DMA Transfer selected, the signal to start writing external memory data to the MSM9845 is entered to this pin. When DMA Transfer is not use, keep the pin “H”. 44 DASD O 16-bit serial data output pin when the external DAC is in use. 43 SIOCK I/O Synchronizing clock signal for 16-bit serial data input/output when the external DAC is in use. 54 XT I 55 XT O 46 VCK I/O 33 RESET I “L” level input to this pin turns the LSI to the initial status. 47, 48 TEST0, 1 45, 26 TEST2, 3 I Pins for testing the LSI. Keep these pins “L”. 28 AOUTL O The left channel output from the built-in LPF. Analog waveform output can be directly connected to an amplifier to drive a speaker. 29 AOUTR O The right channel output from the built-in LPF. Analog waveform output can be directly connected to an amplifier to drive a speaker. 5, 31 DVDD — Digital power supply pin. Insert a 0.1µF or larger bypass capacitor between this pin and the DGND pin. 21, 49 DGND — Digital GND pin. 30 AVDD — Analog power supply pin. Insert a 0.1µF or larger bypass capacitor between this pin and the AGND pin. 22 AGND — Analog GND pin. Pins wired to the oscillator. When the external clock is used, input the clock signal to the XT pin and keep the XT pin open. Input/Output the sampling frequency in use. The signal is used as the synchronizing signal when the external DAC is in use. 5/9 FEDL9845DIGEST-01 1Semiconductor MSM9845 ABSOLUTE MAXIMUM RATINGS (GND = 0 V) Parameter Symbol Power Supply Voltage VDD Input Voltage VIN Power Dissipation Conditions Rating Unit –0.3 to +7.0 V Ta = 25°C –0.3 to VDD +0.3 V 571.4 mW — –55 to +150 °C PD Storage Temperature TSTG RECOMMENDED OPERATING CONDITIONS (GND = 0 V) Parameter Symbol Conditions Rating Unit VDD DGND = AGND = 0 V +4.5 to +5.5 V Operating Temperature TOP — –40 to +85 °C Master Clock Frequency fOSC — 24.576 MHz Power Supply Voltage ELECTRICAL CHARACTERISTICS DC Characteristics DVDD = AVDD = +4.5 V to +5.5 V DGND = AGND = 0 V, Ta = –40 to + 85°C Symbol Conditions Min. Typ. Max. Unit “H” Input Voltage Parameter VIH — VDD × 0.85 — — V “L” Input Voltage VIL — — — VDD × 0.15 V “H” Output Voltage note 1 VOH1 IOH = –40 µA VDD –0.3 — — V “L” Output Voltage note 1 VOL1 IOL = 2 mA — — 0.45 V “H” Output Voltage note 2 VOH2 IOH = –40 µA VDD –0.3 — — V “L” Output Voltage note 2 VOL2 IOL = 2 mA — — 0.8 V “H” Input Current note 3 IIH1 VIH = VDD — — 10 µA “H” Input Current note 4 IIH2 VIH = VDD — — 20 µA “L” Input Current note 3 IIL1 VIL = GND –10 — — µA “L” Input Current note 4 IIL2 VIL = GND –20 — — µA IDD fOSC = 24.576 MHz without load — — 40 mA — — 10 µA — — 50 µA Operating Current Consumption At reset, power down without load Standby Current Consumption IDDS Ta = –40 to +70°C At reset, power down without load Ta = +70 to +85°C note 1) note 2) note 3) note 4) Applies to output pins excluding XT pin. Applies to XT pin. Applies to input pins excluding XT pin. Applies to XT pins . 6/9 FEDL9845DIGEST-01 1Semiconductor MSM9845 APPLICATION CIRCUIT SAMPLE Data Bus MEMORY MSM9845 D15 to D0 DREQL DACKL IOW DREQR DMA Controller CPU or MCU DACKR RD WR CS D/C Sample 1 for 16 bit bus interface with DMA Controller Data Bus MEMORY MSM9845 D15 to D0 CPU or MCU RD WR CS D/C EMP MID FUL Sample 2 for 16 bit bus interface with External Memory 7/9 FEDL9845DIGEST-01 1Semiconductor MSM9845 PACKAGE DIMENSIONS (Unit: mm) QFP56-P-910-0.65-2K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.43 TYP. 4/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 8/9 FEDL9845DIGEST-01 1Semiconductor MSM9845 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 9/9