PLL701-50 Low EMI Spread Spectrum Multiplier IC FEATURES • BLOCK DIAGRAM Spread Spectrum Clock Generator/Multiplier with output selectable from 1x to 8x. 13MHz to 224MHz output with output enable. 13MHz to 30 MHz input frequency from crystal or external clock signal. Reduced EMI from Spread Spectrum Modulation, with selectable modulation magnitude for Center Spread, Down Spread or Asymmetric Spread. TTL/CMOS compatible outputs. 3.3V Operating Voltage. 150 ps maximum cycle-to-cycle jitter. Available in 16-Pin 150mil SSOP. • • • • • • • REF XIN/FIN XOUT 69 mil 0 1 0 1 0 1 0 1 13 13 14 13 20 17 15 13 ~ ~ ~ ~ ~ ~ ~ ~ 28 28 30 28 30 30 30 28 X1 X2 X3 X4 X5 X6 X7 X8 13 ~ 28 26 ~ 56 42 ~ 90 52 ~ 112 100 ~ 150 102 ~ 180 105 ~ 210 104 ~ 224 104 mil M1^ 29 M0^ 30 TESTB 33 SC0^ 34 SC1^ 35 Y X 20 19 C501A A2727 -27 1 4 5 6 GND 0 0 1 1 0 0 1 1 28 21 GND GND 0 0 0 0 1 1 1 1 Multiplier M2^ AVDD 25 22 (Optional) GNDOSC GND 23 (Optional) XOUT/SD0*^ GND M0 Logic XIN M1 OE Control SC2^ M2 FOUT (MHz) FOUT DIE PAD CONFIGURATION OUTPUT CLOCK (FOUT) SELECTION FIN/XIN (MHz) XTAL OSC SC(0:3) SD(0:1) M(0:2) DESCRIPTION The PLL701-50 is a low EMI Clock Generator and Multiplier for high-speed digital systems. It uses PhaseLink’s unique (Patent Pending) Spread Spectrum Technology (SST) and permits different levels of EMI reduction by selecting the amplitude of the applied SST. The SST feature can be disabled. The chip operates with input frequencies ranging from 13 to 30 MHz and provides 1x to 8x multiplication at its output. PLL SST 1700, 2540 18 AVDD 17 AVDD 16 REF/SD1*^ 15 14 VDD VDD (optional) 13 VDD (optional) 12 SC3^ 10 OE^ 8 FOUT 7 GNDBUF DIE SPECIFICATIONS Name Value Size Reverse side Pad dimensions Thickness 104 x 69 mil GND 80 micron x 80 micron 10 mil 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1 PLL701-50 Low EMI Spread Spectrum Multiplier IC SPREAD SPECTRUM SELECTION TABLE SD1 SD0 SC3 SC2 SC1 SC0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Modulation Modulation Magnitude Frequency 0.250% 0.500% 0.750% 1.250% 1.500% 1.750% 2.000% 2.250% 2.500% 2.750% Fin / 512 3.000% 3.250% 3.500% 3.750% Modulation Type C C C C A C A C A C A D C A A C A A C A A C D A A C A A A C A A A C A A A 0.00 % ± 0.125% ± 0.25% ± 0.375% ± 0.625% +0.125 ~ -1.125% ± 0.75% +0.25 ~ -1.25% ± 0.875% +0.375 ~ -1.375% ± 1.00% +0.50 ~ -1.5% -2.00% ± 1.125% +0.625 ~ -1.625% +0.125 ~ -2.125% ± 1.25% +0.25 ~ -2.25% +0.75 ~ -1.75% ± 1.375% +0.875 ~ -1.875% +0.375 ~ -2.375% ± 1.50% -3.00% +1.00 ~ -2.00% +0.50 ~ -2.50% ± 1.625% +1.125 ~ -2.125% +0.625 ~ -2.625% +0.125 ~ -3.125% ± 1.75% +1.25 ~ -2.25% +0.75 ~ -2.75% +0.25 ~ -3.25% ± 1.875% +1.37 ~ -2.375% +0.875 ~ -2.875% +0.375 ~ -3.375% SST turned off SST turned off SST turned off SST turned off Notes: C: Center Spread. A: Asymmetric Spread. D: Down Spread. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2 PLL701-50 Low EMI Spread Spectrum Multiplier IC FUNCTIONAL DESCRIPTION Selectable spread spectrum and modulation magnitude The PLL701-50 provides selectable multiplier factors (1x to 8X), selectable spread spectrum modulation type, as well as selectable modulation magnitude. Selection is made by connecting specific input pins to a logical “zero” or “one”. Pins 6 (SC0), 7 (SC1), 8 (SC2) and 12 (SC3) are used as inputs to select the spread spectrum modulation magnitude as shown on the spread spectrum selection table (page 2). Pins 3 (M2), 4 (M1), 5 (M0) are used as inputs to select the multiplication factor as shown on the output clock selection table (page 1). Pin 11 is the output enable pin, which tri-states all outputs when low (logical “zero”). In order to reduce the number of pins on the chip, the PLL701-50 uses pins 2 and 14 (XOUT/SD0 and REF/SD1) as bi-directional pins. The pins serve as modulation type selector inputs (SD0 and SD1) upon power-up (see spread spectrum selection table on page 2), and as XOUT crystal connection (pin 2), and REF output signal (pin 14) as soon as the inputs have been latched. Connecting a selection pin to a logical “one” All selection pins have an internal pull-up resistor (30kΩ for pins 3, 4, 5, 6, 7, 8, 11, 12, 14 and 120kΩ for pin 2). This internal pull-up resistor will pull the input value to a logical “one” (pull-up) by default, i.e. when no resistive load is connected between the pin and GND. No external pull-up resistor is therefore required for connecting a logical “one” upon power-up. Connecting a selection pin to a logical “zero” For an input only pin, i.e. all input pins except XOUT/SD0 (pin 2) and REF/SD1 (pin 14), the pin simply needs to be grounded to pull the input down to a logical “zero”. For the Bidirectional pins ( pins 2 and 14 ) you will need an external resistor. For pin 2 a 27kΩ resistor is recommended and for pin 14 a 4.7kΩ resistor is recommended. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3 PLL701-50 Low EMI Spread Spectrum Multiplier IC 2. DC/AC Specifications PARAMETERS SYMBOL Supply Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage Input Frequency CONDITIONS V DD V IH V IL I IH I IL V OH V OL I OH =5mA, V DD =3.3V I OL =6mA, V DD =3.3V F XIN When using a crystal F IN When using reference clock Maximum interruption of F IN Load Capacitance CL Pull-up Resistor Pull-up Resistor Short Circuit Current 3.3V Dynamic Supply Current R up R up I sc I CC MIN. TYP. 2.97 0.7* V DD MAX. UNITS 3.63 V V V 0.3* V DD 100 100 When using reference clock Between Pin XIN and XOUT* PIN 2 PIN 3,4,5,6,7,8,11,12,14 µA µA 2.4 0.4 See Output Clock Selection table on page 1 See Output Clock Selection table on page 1 100 No Load MHz MHz µs 18 pF 120 30 50 20 kΩ kΩ mA mA *Note: Pin XIN and XOUT each has a 36pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 18pF. If driving XIN with a reference clock signal, the load capacitance will be 36pF (typical). 3. Timing Characteristics PARAMETERS SYMBOL Rise Time Fall Time Output Duty Cycle Cycle to Cycle Jitter Cycle to Cycle Jitter Tr Tf DT T cyc-cyc T cyc-cyc CONDITIONS Measured at 0.8V ~ 2.0V @ 3.3V Measured at 2.0V ~ 0.8V @ 3.3V MIN. TYP. MAX. UNITS 0.8 0.78 45 0.95 0.85 50 1.1 0.9 55 100 150 ns ns % ps ps X1, X2, X4, X8 FOUT @ 3.3V X3, X5, X6, X7 FOUT @ 3.3V 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4 PLL701-50 Low EMI Spread Spectrum Multiplier IC PAD ASSIGNMENT (LOWER LEFT CORNER: X = 0, Y = 0) X (µm) Y (µm) Pad # Name Description 1 SC2 338.9 104.7 2 N/C 569 104.7 3 N/C 780.5 104.7 4 GND 1027.6 104.7 Ground. 5 GND 1127.3 104.7 Ground. 6 GND 1284.5 104.7 Ground. 7 GNDBUF 1595.1 139.7 8 FOUT 1595.1 381.7 Ground, Buffer Circuitry Modulated Clock Frequency Output. The input frequency is multiplied per M(0:2), modulation type is selected per SD(0:1) and modulation rate is selected per SC(0:3). Digital control input to select SS modulation magnitude.30kΩ internal pull-up. 9 N/C 1595.1 596.3 10 OE 1595.1 811.9 11 N/C 1595.1 970.3 12 SC3 1595.1 1069.3 Digital control input to select SS modulation magnitude.30kΩ internal pull-up. 13 VDD (Optional) 1595.1 1312.3 3.3V power supply, Optional 14 VDD (Optional) 1595.1 1555.6 3.3V power supply, Optional 15 VDD 1595.1 1656.8 16 REF/SD1 1595.1 1879.9 17 AVDD 1595.1 2093 3.3V power supply. At power-up, this pin acts as input pin to select the modulation type and is latched in. After the input sampling, this pin provides a buffered Reference Clock Output of the same frequency as the crystal or clock input. 30kΩ internal pull-up. 3.3V Analog power supply. 18 AVDD 1595.1 2390.6 Output Enable. When low, Tri-states all outputs. 30kΩ internal pull-up. 3.3V Analog power supply. 19 AVDD 1369.2 2435 3.3V Analog power supply. 20 GND (Optional) 1037.3 2435 Ground, Optional 21 GND (Optional) 824.7 2435 22 XIN 529.7 2435 23 XOUT/SD0 105.6 2343.5 Ground, Optional Crystal input to be connected to fundamental parallel mode crystal. (C L =18pF) or clock input. At power-up, this pin is acts as input pin to select the modulation type. After the input sampling, it is used as crystal output connector. 120kΩ internal pull up resistor. 24 N/C 105.6 2136.1 25 GNDOSC 105.6 2035.6 26 N/C 105.6 1934.9 27 N/C 105.6 1741.5 28 M2 105.6 1641.4 Digital control input to select multiplier. 30kΩ internal pull-up. 29 M1 105.6 1396.2 Digital control input to select multiplier. 30kΩ internal pull-up. 30 M0 105.6 1180.3 Digital control input to select multiplier. 30kΩ internal pull-up. 31 N/C 105.6 993.5 32 N/C 105.6 836.7 33 TESTB 105.6 680.1 Disables multiplication and SST when pulled low. For crystal fine tuning. Internal pull up. 34 SC0 105.6 354.9 Digital control input to select SS modulation magnitude.30kΩ internal pull-up. 35 SC1 105.6 110.7 Digital control input to select SS modulation magnitude.30kΩ internal pull-up. Ground, Oscillator Circuitry 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5 PLL701-50 Low EMI Spread Spectrum Multiplier IC ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL701-50 PART NUMBER XC TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE D= Die Order Number Marking Package Option PLL701-50DC P701-50DC Die –Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6