LNK353/354 ® LinkSwitch-HF Family Enhanced, Energy Efficient, Low Power Off-Line Switcher IC Product Highlights Features Optimized for Lowest System Cost • Fully integrated auto-restart for short-circuit and open loop protection • Self-biased supply – saves transformer auxiliary winding and associated bias supply components • Tight tolerances and negligible temperature variation on key parameters eases design and lowers cost • High maximum switching frequency allows very low flux density transformer designs, practically eliminating audible noise • Frequency jittering greatly reduces EMI • Packages with large creepage to high voltage pin • Lowest component count switcher solution Much Better Performance over Linear/RCC • Lower system cost than RCC, discrete PWM and other integrated solutions • Universal input range allows worldwide operation • Simple ON/OFF control – no loop compensation needed • No bias winding – simpler, lower cost transformer • High frequency switching – smaller and lower cost transformer • Very low component count – higher reliability and single side printed circuit board • High bandwidth provides fast turn on with no overshoot and excellent transient load response • Current limit operation rejects line frequency ripple • Built-in current limit and hysteretic thermal shutdown protection ® EcoSmart – Extremely Energy Efficient • No-load consumption <300 mW without bias winding at 265 VAC input • Meets California Energy Commission (CEC), Energy Star, and EU requirements Applications • Chargers for cell/cordless phones, PDAs, digital cameras, MP3/portable audio devices, shavers etc. • Standby and auxiliary supplies Description LinkSwitch-HF integrates a 700 V power MOSFET, oscillator, simple ON/OFF control scheme, a high voltage switched current + DC Output Wide Range HV DC Input D LinkSwitch-HF + FB BP S PI-3855-022704 Figure 1. Typical Standby Application. OUTPUT POWER TABLE PRODUCT(3) 230 VAC ±15% Adapter(1) 85-265 VAC Open Open Adapter(1) Frame(2) Frame(2) LNK353 P or G 3W 4W LNK354 P or G 3.5 W 5W 2.5 W(4) 3W (4) 3W 4.5 W Table 1. Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50 °C ambient. 2. Maximum practical continuous power in an open frame design with adequate heat sinking, measured at 50 °C ambient. 3. Packages: P: DIP-8B, G: SMD-8B. For lead-free package options, see Part Ordering Information. 4. For designs without a Y capacitor, the available power may be lower (see Key Applications Considerations). source, frequency jittering, cycle-by-cycle current limit, and thermal shutdown circuitry onto a monolithic IC. The start-up and operating power are derived directly from the DRAIN pin, eliminating the need for a bias winding and associated circuitry. The 200 kHz maximum switching frequency allows very low flux transformer designs, practically eliminating audible noise with the simple ON/OFF control scheme using standard varnished transformer construction. Efficient operation at this high switching frequency is achieved due to the optimized switching characteristics and small capacitances of the integrated power MOSFET. The fully integrated auto-restart circuit safely limits output power during fault conditions such as output short circuit or open loop, reducing component count and secondary feedback circuitry cost. The internal oscillator frequency is jittered to significantly reduce both the quasi-peak and average EMI, minimizing filtering cost. February 2005 LNK353/354 BYPASS (BP) DRAIN (D) REGULATOR 5.8 V FAULT PRESENT AUTORESTART COUNTER CLOCK RESET + 5.8 V 4.85 V BYPASS PIN UNDER-VOLTAGE - CURRENT LIMIT COMPARATOR 6.3 V + VI - LIMIT JITTER CLOCK DCMAX OSCILLATOR FEEDBACK (FB) THERMAL SHUTDOWN 1.65 V -VT S Q R Q LEADING EDGE BLANKING SOURCE (S) PI-2367-021105 Figure 2. Functional Block Diagram. Pin Functional Description DRAIN (D) Pin: Power MOSFET drain connection. Provides internal operating current for both start-up and steady-state operation. BYPASS (BP) Pin: Connection point for a 0.1 µF external bypass capacitor for the internally generated 5.8 V supply. FEEDBACK (FB) Pin: During normal operation, switching of the power MOSFET is controlled by this pin. MOSFET switching is terminated when a current greater than 49 µA is delivered into this pin. SOURCE (S) Pin: This pin is the power MOSFET source connection. It is also the ground reference for the BYPASS and FEEDBACK pins. 2 F 2/05 P Package (DIP-8B) G Package (SMD-8B) S 1 8 S S 2 7 S BP 3 FB 4 5 D PI-3491-111903 Figure 3. Pin Configuration. LNK353/354 LinkSwitch-HF combines a high voltage power MOSFET switch with a power supply controller in one device. Unlike conventional PWM (pulse width modulator) controllers, LinkSwitch-HF uses a simple ON/OFF control to regulate the output voltage. The LinkSwitch-HF controller consists of an oscillator, feedback (sense and logic) circuit, 5.8 V regulator, BYPASS pin under-voltage circuit, over-temperature protection, frequency jittering, current limit circuit, leading edge blanking and a 700 V power MOSFET. The LinkSwitch-HF incorporates additional circuitry for auto-restart. Oscillator The typical oscillator frequency is internally set to an average of 200 kHz. Two signals are generated from the oscillator: the maximum duty cycle signal (DCMAX) and the clock signal that indicates the beginning of each cycle. The LinkSwitch-HF oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 16 kHz peak-to-peak, to minimize EMI emission. The modulation rate of the frequency jitter is set to 1.5 kHz to optimize EMI reduction for both average and quasi-peak emissions. The frequency jitter should be measured with the oscilloscope triggered at the falling edge of the DRAIN waveform. The waveform in Figure 4 illustrates the frequency jitter of the LinkSwitch-HF. Feedback Input Circuit The feedback input circuit at the FB pin consists of a low impedance source follower output set at 1.65 V. When the current delivered into this pin exceeds 49 µA, a low logic level (disable) is generated at the output of the feedback circuit. This output is sampled at the beginning of each cycle on the rising edge of the clock signal. If high, the power MOSFET is turned on for that cycle (enabled), otherwise the power MOSFET remains off (disabled). Since the sampling is done only at the beginning of each cycle, subsequent changes in the FB pin voltage or current during the remainder of the cycle are ignored. 5.8 V Regulator and 6.3 V Shunt Voltage Clamp The 5.8 V regulator charges the bypass capacitor connected to the BYPASS pin to 5.8 V by drawing a current from the voltage on the DRAIN, whenever the MOSFET is off. The BYPASS pin is the internal supply voltage node for the LinkSwitch-HF. When the MOSFET is on, the LinkSwitch-HF runs off of the energy stored in the bypass capacitor. Extremely low power consumption of the internal circuitry allows the LinkSwitch-HF to operate continuously from the current drawn from the DRAIN pin.Abypass capacitor value of 0.1 µF is sufficient for both high frequency decoupling and energy storage. In addition, there is a 6.3 V shunt regulator clamping the BYPASS pin at 6.3 V when current is provided to the BYPASS pin through an external resistor. This facilitates powering of LinkSwitch-HF externally through a bias winding to decrease the no-load consumption to less than 50 mW. BYPASS Pin Under-Voltage The BYPASS pin under-voltage circuitry disables the power MOSFET when the BYPASS pin voltage drops below 4.85 V. Once the BYPASS pin voltage drops below 4.85 V, it must rise back to 5.8 V to enable (turn-on) the power MOSFET. Over-Temperature Protection The thermal shutdown circuitry senses the die temperature. The threshold is set at 142 °C typical with a 75 °C hysteresis. When the die temperature rises above this threshold (142 °C) the power MOSFET is disabled and remains disabled until the die temperature falls by 75 °C, at which point it is re-enabled. Current Limit The current limit circuit senses the current in the power MOSFET. When this current exceeds the internal threshold (ILIMIT), the power MOSFET is turned off for the remainder of that cycle. The leading edge blanking circuit inhibits the current limit comparator for a short time (tLEB) after the power MOSFET is turned on. This leading edge blanking time has been set so that current spikes caused by capacitance and rectifier reverse recovery time will not cause premature termination of the switching pulse. Auto-Restart In the event of a fault condition such as output overload, output short circuit, or an open loop condition, LinkSwitch-HF enters into auto-restart operation. An internal counter clocked by the oscillator gets reset every time the FB pin is pulled high. If the FB pin is not pulled high for 30 ms, the power MOSFET switching is disabled for 650 ms. The auto-restart alternately enables and disables the switching of the power MOSFET until the fault condition is removed. 600 500 V PI-3857-022504 LinkSwitch-HF Functional Description DRAIN 400 300 200 100 0 208 kHz 192 kHz 6.4 0 Figure 4. Frequency Jitter. Time (µs) F 2/05 3 LNK353/354 CY1 100 pF D6 SS14 T1 EE16 D1 1N4005 D2 1N4005 R1 100 kΩ RF1 8.2 Ω 2.5 W C3 2.2 nF 400 V R3 200 Ω 5 4 5 J1 C1 4.7 µF 400 V 85-265 VAC NC NC C2 4.7 µF 400 V J2 LinkSwitch-HF D3 1N4005 8 3 D5 1N4007GP 9 U1 LNK354P D4 1N4005 L1 1 mH D FB R4 5.1 kΩ R5 68 Ω C5 2.2 nF 5.7 V, 400 mA J3-2 C6 330 µF 16 V R6 6.8 Ω R7 220 Ω RTN J3-1 Q1 MMST 3906 VR1 BZX79B5V1 5.1 V, 2% R8 390 Ω R9 200 Ω BP S C4 100 nF U2B U2A PC817D PC817D R10 2.4 Ω 1W PI-3891-070204 Figure 5. Universal Input, 5.7 V, 400 mA, Constant Voltage, Constant Current Battery Charger Using LinkSwitch-HF. Applications Example A 2.4 W CC/CV Charger Adapter The circuit shown in Figure 5 is a typical implementation of a 5.7 V, 400 mA, constant voltage, constant current (CV/CC) battery charger. The input bridge formed by diodes D1-D4, rectifies the AC input voltage. The rectified AC is then filtered by the bulk storage capacitors C1 and C2. Resistor RF1 is a flameproof, fusible, wire wound type and functions as a fuse, inrush current limiter and, together with the π filter formed by C1, C2 and L1, differential mode noise attenuator. This simple EMI filtering, together with the frequency jittering of LinkSwitch-HF (U1), a small value Y1 capacitor (CY1), and shield windings within T1, and a secondary-side RC snubber (R5, C5), allows the design to meet both conducted and radiated EMI limits. The low value of CY1 is important to meet the requirement of low line frequency leakage current, in this case <10 µA. The rectified and filtered input voltage is applied to the primary winding of T1. The other side of the transformer primary is driven by the integrated MOSFET in U1. Diode D5, C3, R1 and R3 form the primary clamp network. This limits the peak drain voltage due to leakage inductance. Resistor R3 allows the use of a slow, low cost rectifier diode by limiting the reverse current through D5 when U1 turns on. The selection of a slow diode improves efficiency and conducted EMI. 4 F 2/05 Output rectification is provided by Schottky diode D6. The low forward voltage provides high efficiency across the operating range and the low ESR capacitor C6 minimizes output voltage ripple. In constant voltage (CV) mode, the output voltage is set by the Zener diode VR1 and the emitter-base voltage of PNP transistor Q1. The VBE of Q1 divided by the value of R7 sets the bias current through VR1 (~2.7 mA). When the output voltage exceeds the threshold voltage determined by Q1 and VR1, Q1 is turned on and current flows through the LED of U2. As the LED current increases, the current fed into the FEEDBACK pin increases, disabling further switching cycles of U1. At very light loads, almost all switching cycles will be disabled, giving a low effective switching frequency and providing low no-load consumption. During load transients, R6 and R8 ensure that the ratings of Q1 are not exceeded while R4 prevents C4 from being discharged. Resistors R9 and R10 form the constant current (CC) sense circuit. Above approximately 400 mA, the voltage across the sense resistor exceeds the optocoupler diode forward conduction voltage of approximately 1 V. The current through the LED is therefore determined by the output current and CC control dominates over the CV feedback loop. CC control is maintained even under output short circuit conditions. LNK353/354 Key Application Considerations LinkSwitch-HF Design Considerations Output Power Table Data sheet maximum output power table (Table 1) represents the maximum practical continuous output power level that can be obtained under the following assumed conditions: 1. The minimum DC input voltage is 90 V or higher for 85 VAC input, or 240 V or higher for 230 VAC input or 115 VAC with a voltage doubler. The value of the input capacitance should be large enough to meet these criteria for AC input designs. 2. Secondary output of 5.5 V with a Schottky rectifier diode. 3. Assumed efficiency of 70%. 4. Operating frequency of fOSC(min) and ILIMIT(min). 5. Voltage only output (no secondary side constant current circuit). 6. Continuous mode operation (0.6 ≤ KP ≤ 1). 7. The part is board mounted with SOURCE pins soldered to a sufficient area of copper to keep the SOURCE pin temperature at or below 100 °C. 8. Ambient temperature of 50 °C for open frame designs and an internal enclosure temperature of 60 °C for adapter designs. Below a value of 1, KP is the ratio of ripple to peak primary current. Above a value of 1, KP is the ratio of primary MOSFET off time to the secondary diode conduction time. Operating at a lower effective switching frequency can simplify meeting conducted and radiated EMI limits, especially for designs where the safety Y capacitor must be eliminated. By using a lower effective full load frequency, the calculated value of the primary inductance is higher than required for power delivery. However, the maximum power capability at this lower operating frequency will be lower than the values shown in Table 1. Audible Noise The cycle skipping mode of operation used in LinkSwitch-HF can generate audio frequency components in the transformer. To limit this audible noise generation, the transformer should be designed such that the peak core flux density is below 1250 Gauss (125 mT). Following this guideline and using the standard transformer production technique of dip varnishing practically eliminates audible noise. Higher flux densities are possible however, careful evaluation of the audible noise performance should be made using production transformer samples before approving the design. Ceramic capacitors that use dielectrics such as Z5U, when used in clamp circuits, may also generate audio noise. If this is the case, try replacing them with a capacitor having a different dielectric, for example a polyester film type. LinkSwitch-HF Layout Considerations See Figure 6 for a recommended circuit board layout for LinkSwitch-HF. Single Point Grounding Use a single point ground connection from the input filter capacitor to the area of copper connected to the SOURCE pins. Bypass Capacitor (CBP) The BYPASS pin capacitor should be located as near as possible to the BYPASS and SOURCE pins. Primary Loop Area The area of the primary loop that connects the input filter capacitor, transformer primary and LinkSwitch-HF together should be kept as small as possible. Primary Clamp Circuit A clamp is used to limit peak voltage on the DRAIN pin at turn off. This can be achieved by using an RCD clamp (as shown in Figure 5) or a Zener (~200 V) and diode clamp across the primary winding. In all cases, to minimize EMI, care should be taken to minimize the circuit path from the clamp components to the transformer and LinkSwitch-HF. Thermal Considerations The copper area underneath the LinkSwitch-HF acts not only as a single point ground, but also as a heatsink. As this area is connected to the quiet source node, this area should be maximized for good heatsinking of LinkSwitch-HF. The same applies to the cathode of the output diode. Y-Capacitor The placement of the Y-capacitor should be directly from the primary input filter capacitor positive terminal to the common/return terminal of the transformer secondary. Such a placement will route high magnitude common mode surge currents away from the LinkSwitch-HF device. Note that if an input π (C, L, C) EMI filter is used, then the inductor in the filter should be placed between the negative terminals of the input filter capacitors. Optocoupler Place the optocoupler physically close to the LinkSwitch-HF to minimize the primary side trace lengths. Keep the high current, high voltage drain and clamp traces away from the optocoupler to prevent noise pick up. Output Diode For best performance, the area of the loop connecting the secondary winding, the output diode and the output filter capacitor should be minimized. In addition, sufficient copper area should be provided at the anode and cathode terminals F 2/05 5 LNK353/354 of the diode for heatsinking. A larger area is preferred at the quiet cathode terminal. A large anode area can increase high frequency radiated EMI. Quick Design Checklist As with any power supply design, all LinkSwitch-HF designs should be verified on the bench to make sure that component specifications are not exceeded under worst-case conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage – Verify that VDS does not exceed 675 V at the highest input voltage and peak (overload) output power. 2. Maximum drain current – At maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms for any signs of transformer saturation and excessive leading edge current spikes at startup. Repeat under steady state conditions and verify that TOP VIEW the leading edge current spike event is below ILIMIT(MIN) at the end of the tLEB(MIN). Under all conditions, the maximum drain current should be below the specified absolute maximum ratings. 3. Thermal Check – At specified maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature specifications are not exceeded for LinkSwitch-HF, transformer, output diode, and output capacitors. Enough thermal margin should be allowed for part-to-part variation of the RDS(ON) of LinkSwitch-HF as specified in the data sheet. Under low line, maximum power, a maximum LinkSwitch-HF SOURCE pin temperature of 100 °C is recommended to allow for these variations. Design Tools Up-to-date information on design tools can be found at the Power Integrations website: www.powerint.com. Input Filter Capacitor Y1Capacitor + HV DC Input - PRI S T r a n s f o r m e r + DC Out - Output Filter Capacitor SEC D S LinkSwitch-HF S S BP FB Optocoupler CBP Figure 6. Recommended Printed Circuit Layout for LinkSwitch-HF in a Flyback Converter Configuration. 6 F 2/05 Maximize hatched copper areas ( ) for optimum heatsinking PI-3890-102704 LNK353/354 ABSOLUTE MAXIMUM RATINGS(1,5) DRAIN Voltage .................................................. -0.3 V to 700 V Peak DRAIN Current......................................400 mA (750 mA)(2) FEEDBACK Voltage ................................................ -0.3 V to 9 V FEEDBACK Current .................................................... 100 mA BYPASS Voltage...................................................... -0.3 V to 9 V Storage Temperature .......................................... -65 °C to 150 °C Operating Junction Temperature(3) ..................... -40 °C to 150 °C Lead Temperature(4).......................................................... 260 °C Notes: 1. All voltages referenced to SOURCE, TA = 25 °C. 2. The higher peak DRAIN current is allowed while the DRAIN voltage is less than 400 V. 3. Normally limited by internal circuitry. 4. 1/16 in. from case for 5 seconds. 5. Maximum ratings specified may be applied, one at a time, without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect product reliability. THERMAL IMPEDANCE Thermal Impedance: P or G Package: Notes: (θJA) ........................... 70 °C/W(2); 60 °C/W(3) 1. Measured on pin 2 (SOURCE) close to plastic interface. (θJC)(1) ............................................... 11 °C/W 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad. 3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad. Conditions Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C See Figure 7 (Unless Otherwise Specified) Min Typ Max 186 200 214 Units CONTROL FUNCTIONS Output Frequency Maximum Duty Cycle FEEDBACK Pin Turnoff Threshold Current FEEDBACK Pin Voltage DRAIN Supply Current BYPASS Pin Charge Current BYPASS Pin Voltage BYPASS Pin Voltage Hysteresis fOSC TJ = 25 °C Average Peak-Peak Jitter 16 kHz DCMAX S2 Open 60 63 % IFB TJ = 25 °C 30 49 68 µA VFB IFB = 49 µA 1.54 1.65 1.76 V IS1 VFB ≥2 V (MOSFET Not Switching) See Note A 200 275 µA IS2 FEEDBACK Open (MOSFET Switching) See Notes A, B 280 365 µA ICH1 VBP = 0 V, TJ = 25 °C See Note C -5.5 -3.3 -1.8 ICH2 VBP = 4 V, TJ = 25 °C See Note C -3.8 -2.1 -1.0 VBP 5.55 5.8 6.10 V VBPH 0.8 0.95 1.2 V mA F 2/05 7 LNK353/354 Conditions Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C See Figure 7 (Unless Otherwise Specified) Min Typ Max Units CONTROL FUNCTIONS (cont) BYPASS Pin Supply Current IBPSC See Note D 68 µA CIRCUIT PROTECTION di/dt = 90 mA/µs TJ = 25 °C Current Limit ILIMIT (See Note E) tLEB Thermal Shutdown Temperature TSD Thermal Shutdown Hysteresis TSHD OFF-State Drain Leakage Current Breakdown Voltage RDS(ON) F 2/05 300 336 LNK353 390 470 610 LNK354 280 360 500 170 215 135 142 See Note G LNK353 ID = 25 mA LNK354 ID = 25 mA TJ = 100 °C TJ = 25 °C TJ = 100 °C Measured in a Typical Flyback Converter Application 150 °C °C 34 40 54 63 24 28 38 45 50 700 ns ns 75 TJ = 25 °C VBP = 6.2 V, VFB ≥2 V, TJ = 25 °C tF 8 264 LNK354 BVDSS Fall Time 274 268 VBP = 6.2 V, VFB ≥2 V, VDS = 560 V, TJ = 125 °C tR 245 250 IDSS Rise Time 215 233 TJ = 25 °C See Note F OUTPUT ON-State Resistance 198 mA di/dt = 115 mA/µs TJ = 25 °C tON(MIN) Leading Edge Blanking Time 185 LNK353 di/dt = 400 mA/µs TJ = 25 °C di/dt = 500 mA/µs TJ = 25 °C Minimum On Time 172 Ω µA V 50 ns 50 ns LNK353/354 Conditions Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C See Figure 7 (Unless Otherwise Specified) Min Typ Max Units OUTPUT (cont) DRAIN Supply Voltage 50 Output Enable Delay tEN Output Disable Setup Time tDST Auto-Restart ON-Time tAR Auto-Restart Duty Cycle V See Figure 9 TJ = 25 °C See Note H DCAR 10 µs 0.5 µs 31 ms 5 % NOTES: A. Total current consumption is the sum of IS1 and IDSS when FEEDBACK pin voltage is ≥2 V (MOSFET not switching) and the sum of IS2 and IDSS when FEEDBACK pin is shorted to SOURCE (MOSFET switching). B Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN. An alternative is to measure the BYPASS pin current at 6 V. C. See Typical Performance Characteristics section Figure 14 for BYPASS pin start-up charging waveform. D. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK pins and not any other external circuitry. E. For current limit at other di/dt values, refer to Figure 13. F. This parameter is guaranteed by design. G. This parameter is derived from characterization. H. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). F 2/05 9 LNK353/354 470 Ω 5W 470 kΩ D S1 FB S2 BP 50 V S S S S 50 V 0.1 µF PI-3490-060204 Figure 7. LinkSwitch-HF General Test Circuit. DCMAX t2 HV 90% (internal signal) t1 tP 90% FB DRAIN VOLTAGE 0V t D= 1 t2 VDRAIN 10% tP = tEN 1 fOSC PI-3707-112503 PI-2048-033001 Figure 8. LinkSwitch-HF Duty Cycle Measurement. 10 F 2/05 Figure 9. LinkSwitch-HF Output Enable Timing. LNK353/354 Typical Performance Characteristics 1.0 PI-2680-012301 1.2 Output Frequency (Normalized to 25 °C) PI-2213-012301 1.0 0.8 0.6 0.4 0.2 0 0.9 -50 -25 0 25 50 -50 75 100 125 150 -25 Junction Temperature (°C) 1.0 0.8 Normalized di/dt di/dt = 1 di/dt = 6 0.6 0.4 0.2 50 100 100 125 PI-3892-061604 1.2 1.0 0.8 TBD Normalized 0.6 0.4 LNK353 LNK354 0.2 LNK353 LNK354 150 Temperature (°C) Figure 12. Current Limit vs. Temperature at Normalized di/dt. di/dt = 1 90 mA/µs 115 mA/µs Normalized Current Limit = 1 185 mA 250 mA 6 1 2 3 4 5 Normalized di/dt Figure 13. Current Limit vs. di/dt. PI-2240-012301 7 BYPASS Pin Voltage (V) 75 0 0 5 4 3 2 1 400 350 DRAIN Current (mA) 0 -50 50 1.4 Normalized Current Limit PI-3709-111203 Current Limit (Normalized to 25 °C) 1.2 25 Figure 11. Frequency vs. Temperature. Figure 10. Breakdown vs. Temperature. 1.4 0 Junction Temperature (°C) PI-3949-102004 Breakdown Voltage (Normalized to 25 °C) 1.1 25 °C 300 100 °C 250 200 Scaling Factors: LNK353 0.7 LNK354 1.0 150 100 50 0 0 0 0.2 0.4 0.6 0.8 Time (ms) Figure 14. BYPASS Pin Start-up Waveform. 1.0 0 2 4 6 8 10 12 14 16 18 20 DRAIN Voltage (V) Figure 15. Output Characteristics. F 2/05 11 LNK353/354 Typical Performance Characteristics (cont.) PI-3888-052104 Drain Capacitance (pF) 1000 100 10 1 0 100 200 300 400 500 600 Drain Voltage (V) Figure 16. COSS vs. Drain Voltage. PART ORDERING INFORMATION LinkSwitch Product Family HF Series Number Package Identifier G Plastic Surface Mount DIP P Plastic DIP Lead Finish Blank Standard (Sn Pb) N Pure Matte Tin (Pb-Free) Tape & Reel and Other Options LNK 354 G N - TL 12 F 2/05 Blank Standard Configurations TL Tape & Reel, 1 k pcs minimum, G Package only LNK353/354 DIP-8B ⊕ D S .004 (.10) -E- Notes: 1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing. 2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 3. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. 4. Pin locations start with Pin 1, and continue counter-clockwise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 6 is omitted. 5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. Lead width measured at package body. 7. Lead spacing measured with the leads constrained to be perpendicular to plane T. .137 (3.48) MINIMUM .240 (6.10) .260 (6.60) Pin 1 -D- .367 (9.32) .387 (9.83) .125 (3.18) .145 (3.68) -T- .015 (.38) MINIMUM SEATING PLANE .100 (2.54) BSC .057 (1.45) .068 (1.73) (NOTE 6) .008 (.20) .015 (.38) .120 (3.05) .140 (3.56) .300 (7.62) BSC (NOTE 7) .300 (7.62) .390 (9.91) .048 (1.22) .053 (1.35) .014 (.36) .022 (.56) ⊕ T E D S .010 (.25) M P08B PI-2551-121504 SMD-8B ⊕ D S .004 (.10) .137 (3.48) MINIMUM -E- .372 (9.45) .388 (9.86) ⊕ E S .010 (.25) .240 (6.10) .260 (6.60) Pin 1 .100 (2.54) (BSC) -D- .367 (9.32) .387 (9.83) .057 (1.45) .068 (1.73) (NOTE 5) .125 (3.18) .145 (3.68) .032 (.81) .037 (.94) .048 (1.22) .053 (1.35) Notes: 1. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 2. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. .420 3. Pin locations start with Pin 1, and continue counter-clock.046 .060 .060 .046 wise to Pin 8 when viewed from the top. Pin 6 is omitted. 4. Minimum metal to metal .080 spacing at the package body Pin 1 for the omitted lead location is .137 inch (3.48 mm). .086 5. Lead width measured at .186 package body. .286 6. D and E are referenced Solder Pad Dimensions datums on the package body. .004 (.10) .009 (.23) .004 (.10) .012 (.30) .036 (0.91) .044 (1.12) 0°- 8° G08B PI-2546-121504 F 2/05 13 LNK353/354 Notes 14 F 2/05 LNK353/354 Notes F 2/05 15 LNK353/354 Revision Notes Date D 1) Released Final Data Sheet. 10/04 E 1) Added lead-free ordering information. 12/04 F 1) Minor error corrections. 2/05 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. PATENT INFORMATION The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrationsʼ patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. LIFE SUPPORT POLICY POWER INTEGRATIONSʼ PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, EcoSmart, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©Copyright 2005, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations WORLD HEADQUARTERS 5245 Hellyer Avenue San Jose, CA 95138, USA. Main: +1-408-414-9200 Customer Service: Phone: +1-408-414-9665 Fax: +1-408-414-9765 e-mail: [email protected] GERMANY Rueckertstrasse 3 D-80336, Munich Germany Phone: +49-89-5527-3910 Fax: +49-89-5527-3920 e-mail: [email protected] JAPAN Keihin Tatemono 1st Bldg 2-12-20 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa ken, Japan 222-0033 Phone: +81-45-471-1021 Fax: +81-45-471-3717 e-mail: [email protected] TAIWAN 5F, No. 318, Nei Hu Rd., Sec. 1 Nei Hu Dist. Taipei, Taiwan 114, R.O.C. Phone: +886-2-2659-4570 Fax: +886-2-2659-4550 e-mail: [email protected] CHINA (SHANGHAI) Rm 807-808A, Pacheer Commercial Centre, 555 Nanjing Rd. West Shanghai, P.R.C. 200041 Phone: +86-21-6215-5548 Fax: +86-21-6215-2468 e-mail: [email protected] INDIA 261/A, Ground Floor 7th Main, 17th Cross, Sadashivanagar Bangalore, India 560080 Phone: +91-80-5113-8020 Fax: +91-80-5113-8023 e-mail: [email protected] KOREA RM 602, 6FL Korea City Air Terminal B/D, 159-6 Samsung-Dong, Kangnam-Gu, Seoul, 135-728, Korea Phone: +82-2-2016-6610 Fax: +82-2-2016-6630 e-mail: [email protected] EUROPE HQ 1st Floor, St. Jamesʼs House East Street, Farnham Surrey, GU9 7TJ United Kingdom Phone: +44 (0) 1252-730-140 Fax: +44 (0) 1252-727-689 e-mail: [email protected] CHINA (SHENZHEN) Rm 2206-2207, Block A, Electronics Science & Technology Bldg. 2070 Shennan Zhong Rd. Shenzhen, Guangdong, China, 518031 Phone: +86-755-8379-3243 Fax: +86-755-8379-5828 e-mail: [email protected] ITALY Via Vittorio Veneto 12 20091 Bresso MI Italy Phone: +39-028-928-6000 Fax: +39-028-928-6009 e-mail: [email protected] SINGAPORE 51 Newton Road, #15-08/10 Goldhill Plaza, Singapore, 308900 Phone: +65-6358-2160 Fax: +65-6358-2015 e-mail: [email protected] APPLICATIONS HOTLINE World Wide +1-408-414-9660 16 F 2/05 APPLICATIONS FAX World Wide +1-408-414-9760