SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004 D Controlled Baseline D D D D D D D D D D D D Flow-Through Architecture Optimizes PCB − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Member of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Supports Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed VCC and GND Pins Minimize High-Speed Switching Noise D D Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) DGG OR DL PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE description/ordering information The SN74LVTH16373 is a 16-bit transparent D-type latch with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright 2004, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"& *%$"# $ " #'&$$!"# '& "+& "&# &,!# #"%&"# #"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*& "&#"/ !)) '!!&"&# POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004 description/ordering information (continued) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. GQL OR ZQL PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 1 2 3 4 5 A A 1OE NC NC NC NC 1LE B B 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 1D4 1Q6 1Q5 VCC GND 1D3 D VCC GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 C D E F G F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND GND 2D4 2D3 H 2Q5 2Q6 VCC GND 2D6 2D5 2D8 2D7 NC NC 2LE H J 2Q7 2Q8 VCC GND J K 2OE NC NC K NC − No internal connection ORDERING INFORMATION TA −40°C −40 C to 85 85°C C PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING SSOP − DL Tape and reel CLVTH16373IDLREP LH16373EP TSSOP − DGG Tape and reel CLVTH16373IDGGREP LH16373EP VFBGA − GQL VFBGA − ZQL (Pb-free) CLVTH16373IGQLREP Tape and reel CLVTH16373IZQLREP LL373EP † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. 2 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004 FUNCTION TABLE (each 8-bit section) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) 1OE 1LE 1D1 1 2OE 48 47 2LE C1 1D 2 1Q1 24 25 C1 2D1 36 1D 13 2Q1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004 recommended operating conditions (see Note 4) MIN MAX 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 5.5 V IOH IOL High-level output current −32 mA ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature −40 High-level input voltage 2 V 0.8 Low-level output current Outputs enabled V V 64 mA 10 ns/V µs/V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS Control inputs Data inputs Ioff V IOH = −8 mA IOH = −32 mA IOL = 100 µA IOL = 24 mA 0.2 VCC = 2.7 V 0.4 VCC = 3 V IOL = 16 mA IOL = 32 mA 0.55 VCC = 0 or 3.6 V, IOL = 64 mA VI = 5.5 V VCC = 3.6 V, VI = VCC or GND VCC = 3.6 V VI = VCC VI = 0 VCC−0.2 2.4 VCC = 3 V IOZH IOZL VCC = 3.6 V, VCC = 3.6 V, VO = 3 V VO = 0.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care V 2 0.5 10 ±1 µA 1 −5 ±100 µA 75 µA −75 ±500 Outputs high VCC = 3.6 V, IO = 0, VI = VCC or GND V 0.5 VI or VO = 0 to 4.5 V VI = 0.8 V VCC = 3.6 V‡, ICC UNIT −1.2 VCC = 2.7 V, VCC = 3 V, VCC = 0, Data inputs MAX II = −18 mA IOH = −100 µA VI = 2 V VI = 0 to 3.6 V II(hold) TYP† VCC = 2.7 V, VCC = 2.7 V to 3.6 V, VOL II MIN 5 µA −5 µA ± 100 µA ±100 µA 0.19 Outputs low 5 Outputs disabled mA 0.19 ∆ICC§ VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 0.2 3 mA pF Co 9 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN MAX VCC = 2.7 V MIN UNIT MAX tw tsu Pulse duration, LE high 3 3 ns Setup time, data before LE↓ 1 0.6 ns th Hold time, data after LE↓ 1 1.1 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q PARAMETER tsk(o) † All typical values are at VCC = 3.3 V, TA = 25°C. 6 POST OFFICE BOX 655303 VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN TYP† MAX 1.5 2.7 3.8 4.2 1.5 2.5 3.6 4 2.1 3 4.3 4.8 2.1 2.9 4 4 1.5 2.8 4.3 5.1 1.5 2.8 4.3 4.7 2.4 3.5 5 5.4 2 3.2 4.7 4.8 0.5 • DALLAS, TEXAS 75265 MIN UNIT MAX ns ns ns ns ns SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω 2.7 V Timing Input LOAD CIRCUIT 1.5 V 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1.5 V Output 1.5 V VOL tPHL 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPLZ 3V 1.5 V tPZH VOH Output Output Waveform 1 S1 at 6 V (see Note B) tPLH 1.5 V 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing CLVTH16373IDGGREP ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CLVTH16373IDLREP ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CLVTH16373IZQLREP ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 SNAGCU Level-1-260C-UNLIM V62/04712-01XE ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04712-01YE ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04712-01ZA ACTIVE GQL 56 BGA MI CROSTA R JUNI OR Pins Package Eco Plan (2) Qty Pb-Free (RoHS) TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVTH16373-EP : SN74LVTH16373 • Catalog: • Military: SN54LVTH16373 NOTE: Qualified Version Definitions: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 - TI's standard catalog product • Catalog Military QML certified for Military and Defense Applications • Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CLVTH16373IDGGREP CLVTH16373IDLREP CLVTH16373IZQLREP Package Package Pins Type Drawing TSSOP SSOP BGA MI CROSTA R JUNI OR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.8 12.0 24.0 Q1 DGG 48 2000 330.0 24.4 8.6 15.8 DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 ZQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CLVTH16373IDGGREP TSSOP DGG 48 2000 367.0 367.0 45.0 CLVTH16373IDLREP SSOP DL 48 1000 367.0 367.0 55.0 CLVTH16373IZQLREP BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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