PT6526 LCD Driver IC DESCRIPTION PT6526 is a General Purpose LCD Driver IC utilizing CMOS Technology specially designed for electronic tuners controlled by microcontroller. It can drive up to a maximum of 204 segment outputs and can control up to 12 general purpose output ports. Pin assignments and application circuit are optimized for easy PCB layout and cost saving advantages. APPLICATION • Frequency Display for Electronic Tuners FEATURES • • • • • • • • • • • CMOS Technology Up to 4 Common and 51 Segment Drivers Up to 204 LCD Segments Up to 12 General Purpose Output Ports 1/4 Duty – 1/2 Bias or 1/4 Duty – 1/3 Bias Drive Technique No Decoder Intervention Necessary to Display the Data Power Saving Mode provided Power Supply Voltage: 4.5V to 6V CMOS/TTL compatible logic input pins RC Oscillation Circuit Available in 64 pins, LQFP BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6526 APPLICATION CIRCUITS 1/2 BIAS (NORMAL PANELS) Notes: 1. C ≥ 0.047µF 2. 39KΩ ≥ R1 ≥ 1KΩ V1.1 2 November 2009 PT6526 1/2 BIAS (LARGE PANELS) Notes: 1. C ≥ 0.047µF 2. 10KΩ ≥ R ≥ 1KΩ 3. 39KΩ ≥ R1 ≥ 1KΩ V1.1 3 November 2009 PT6526 1/3 BIAS (NORMAL PANELS) Notes: 1. C ≥ 0.047µF 2. 39KΩ ≥ R1 ≥ 1KΩ V1.1 4 November 2009 PT6526 1/3 BIAS (LARGE PANELS) Notes: 1. 10KΩ ≥ R ≥ 1KΩ 2. C ≥ 0.047µF 3. 39KΩ ≥ R1 ≥ 1KΩ V1.1 5 November 2009 PT6526 ORDER INFORMATION Valid Part Number PT6526-LQ Package Type 64 Pin, LQFP Top Code PT6526-LQ PIN CONFIGURATION V1.1 6 November 2009 PT6526 PIN DESCRIPTION Pin Name SG1/P1 ~ SG12/P12 SG13 ~ SG51 COM1 ~ COM4 VDD I/O O O O - VDD1 - VDD2 - VSS OSC I/O /INH I CE CLK DI I I I Description Segment Driver Output/General Purpose Output Ports Segment Driver Output Pins Common Driver Output Pins Power Supply Power Supply This pin is used to apply a 2/3 LCD Drive Bias Voltage. If the ½ Bias Drive Technique is used, this pin must be short to VDD2. Power Supply This pin is used to apply a 1/3 LCD Drive Bias Voltage. If the ½ Bias Drive Technique is used, this pin must be short to VDD1. Ground Oscillation Input / Output Pin Display OFF Control Pin If this pin is set to “LOW” (VSS), the display is forced to turn OFF. Output driver pins -- SG1/P1 to SG12/P12, SG13 to SG51, COM1 to COM4 are set to “LOW”. If this pin is set to “HIGH” (VDD), the display is turned ON. (see Note) Chip Enable Pin Clock Input Pin Data Input Pin Pin No. 1 ~ 12 13 ~ 51 52 ~55 56 57 58 59 60 61 62 63 64 Note: It must be noted that when the display is forcibly turned OFF, the serial data transfers can still be performed. V1.1 7 November 2009 PT6526 INPUT/OUTPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below: INPUT PIN: CLK, CE, DI, /INH OUTPUT PIN: COM1 TO COM4, SG13 TO SG51 OUTPUT PIN: SG1/P1 TO SG12/P12 V1.1 8 November 2009 PT6526 UNCTION DESCRIPTION CONTROL DATA BITS CU: NORMAL MODE CURRENT DRAIN CONTROL DATA BIT This control bit is used to select the current drain (either Normal Current Drain or Low Current Drain) in the Normal Mode. Please refer to the table below. CU 0 1 Current Drain (under the Normal Mode) Normal Current Drain (IDD2, IDD3) Low Current Drain (IDD4, IDD5) It should be noted that when the Low Current Drain is selected by setting the CU to “1”, the output waveforms of the common and segment driver are easily distorted since the capacity to supply the current to the LCD panel from the Common and Segment Pins is less than capacity under the Normal Current Drain (CU = “0”). P0 TO P3: SEGMENT / GENERAL PURPOSE OUTPUT PORT SELECT BITS These control bits are used to select the function of the SG1/P1 to SG12/P12 output pins (either Segment Output Pins or General Purpose Output Pins). Please refer to the table below. Control Data Output Pins SG1/ SG2/ SG3/ SG4/ SG5/ SG6/ SG7/ SG8/ SG9/ SG10 SG11 SG12/ P0 P1 P2 P3 P1 P2 P3 P4 P5 P6 P7 P8 P9 /P10 /P11 P12 0 0 0 0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 0 0 1 P1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 0 1 0 P1 P2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 0 1 1 P1 P2 P3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 1 0 0 P1 P2 P3 P4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 1 0 1 P1 P2 P3 P4 P5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 1 1 0 P1 P2 P3 P4 P5 P6 SG7 SG8 SG9 SG10 SG11 SG12 0 1 1 1 P1 P2 P3 P4 P5 P6 P7 SG8 SG9 SG10 SG11 SG12 1 0 0 0 P1 P2 P3 P4 P5 P6 P7 P8 SG9 SG10 SG11 SG12 1 0 0 1 P1 P2 P3 P4 P5 P6 P7 P8 P9 SG10 SG11 SG12 1 0 1 0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 SG11 SG12 1 0 1 1 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 SG12 1 1 0 0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 When the General Purpose Output Port Function is selected, the correspondence between the output pins and the respective display data is given in the table below. Output Pin Corresponding Display Data Output Pin Corresponding Display Data SG1/P1 D1 SG7/P7 D25 SG2/P2 D5 SG8/P8 D29 SG3/P3 D9 SG9/P9 D33 SG4/P4 D13 SG10/P10 D37 SG5/P5 D17 SG11/P11 D41 SG6/P6 D21 SG12/P12 D45 When the General Purpose Output Port Function is selected, the respective output pin is output a “HIGH” level when it corresponding display data is set to “1”. Likewise, it will output a “LOW” level, if its corresponding display data is set to “0”. For example, SG4/P4 is used as a General Purpose Output Port, if its corresponding display data – D13 is set to “1”, then SG4/P4 will output “HIGH” level. Likewise, if D13 is set to “0”, then SG4/P4 will output “LOW” level. V1.1 9 November 2009 PT6526 DR: BIAS DRIVE TECHNIQUE CONTROL DATA BIT This control bit is used to select either 1/2 Bias drive or 1/3 Bias Drive Technique. Please refer to the table below. DR Bias Drive Technique 0 1/3 1 1/2 SC: SEGMENT ON / OFF CONTROL DATA BIT This control bit is used to select the state of the segment driver output pins. Please refer to the table below. SC Display State 0 ON 1 OFF BU: NORMAL / POWER SAVING MODE SELECT BIT This control bit is used to select either the Normal Mode or the Power Saving Mode. Please refer to the table below. BU Mode Remarks 0 Normal Mode The oscillation circuit stops, the common and segment output pins are set to 1 Power Saving Mode “LOW” level. It must be noted that the output pins - SG1/P1 to SG12/P12 may be used as General Purpose Output Ports by setting the control bits – P0 to P3. V1.1 10 November 2009 PT6526 DISPLAY CONTROL AND THE /INH PIN When power is initialized, the internal data of PT6526 (that is, display data – D1 to D204 and the control data) are not defined. Irrelevant displays caused by the undefined internal data can be prevented by using the following procedures. The /INH pin must be set to “LOW” at the same time as the power is applied to turn OFF the display. Doing this will set the output pins – SG1/P1 to SG12/P12, SG13 to SG51 and COM1 to COM4 to “LOW” level. While the /INH pin is held at “LOW” level, the microcontroller must send the serial data. Then the application can set the /INH pin to “HIGH”. Please refer to the figure below. Notes: 1. t1 = determined by the value of C and R. 2. tc = 10us (minimum) V1.1 11 November 2009 PT6526 DISPLAY DATA AND THE OUTPUT PIN CORRESPONDENCE Output Pin SG1/P1 SG2/P2 SG3/P3 SG4/P4 SG5/P5 SG6/P6 SG7/P7 SG8/P8 SG9/P9 SG10/P10 SG11/P11 SG12/P12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 SG32 SG33 SG34 SG35 SG36 SG37 SG38 SG39 SG40 SG41 SG42 SG43 SG44 SG45 SG46 SG47 SG48 SG49 SG50 SG51 COM1 D1 D5 D9 D13 D17 D21 D25 D29 D33 D37 D41 D45 D49 D53 D57 D61 D65 D69 D73 D77 D81 D85 D89 D93 D97 D101 D105 D109 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 D153 D157 D161 D165 D169 D173 D177 D181 D185 D189 D193 D197 D201 COM2 D2 D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 D82 D86 D90 D94 D98 D102 D106 D110 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 D162 D166 D170 D174 D178 D182 D186 D190 D194 D198 D202 COM3 D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 D83 D87 D91 D95 D99 D103 D107 D111 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 D155 D159 D163 D167 D171 D175 D179 D183 D187 D191 D195 D199 D203 COM4 D4 D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 D88 D92 D96 D100 D104 D108 D112 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 D164 D168 D172 D176 D180 D184 D188 D192 D196 D200 D204 Note: The Segment Output Port function is assumed to be selected for the output pins – SG1/P1 to SG12/P12. V1.1 12 November 2009 PT6526 To illustrate further, the states of the S21 output pin is given in the table below. Display Data State of SG21 Output Pin D81 D82 D83 D84 0 0 0 0 LCD Segments corresponding to COM1 to COM4 are OFF. 0 0 0 1 LCD Segment corresponding to COM4 is ON. 0 0 1 0 LCD Segment corresponding to COM3 is ON. 0 0 1 1 LCD Segments corresponding to COM3 and COM4 are ON. 0 1 0 0 LCD Segment corresponding to COM2 is ON. 0 1 0 1 LCD Segments corresponding to COM2 and COM4 are ON. 0 1 1 0 LCD Segments corresponding to COM2 and COM3 are ON. 0 1 1 1 LCD Segments corresponding to COM2, COM3 and COM4 are ON. 1 0 0 0 LCD Segment corresponding to COM1 is ON. 1 0 0 1 LCD Segments corresponding to COM1 and COM4 are ON. 1 0 1 0 LCD Segments corresponding to COM1 and COM3 are ON. 1 0 1 1 LCD Segments corresponding to COM1, COM3 and COM4 are ON. 1 1 0 0 LCD Segments corresponding to COM1 and COM2 are ON. 1 1 0 1 LCD Segments corresponding to COM1, COM2, and COM4 are ON. 1 1 1 0 LCD Segments corresponding to COM1, COM2, and COM3 are ON. 1 1 1 1 LCD Segments corresponding to COM1 and COM 4 are ON. V1.1 13 November 2009 PT6526 SERIAL DATA INPUT CONDITION 1: WHEN CLK IS TERMINATED AT “LOW” LEVEL Notes: 1. Address: 41H 2. D1 to D204: Display Data 3. CU: Normal Mode Current Drain Control Data 4. P0 to P3: Segment Output Port/General Purpose Port Control Data Bit 5. DR: 1/2 or 1/3 Bias Drive Control Data Bit 6. SC: Segment ON /OFF Control Data Bit 7. BU: Normal Mode/Power-Saving Mode Control Data Bit V1.1 14 November 2009 PT6526 CONDITION 2: WHEN CLK IS TERMINATED AT “HIGH” LEVEL Notes: 1. Address: 41H 2. D1 to D204: Display Data 3. CU: Normal Mode Current Drain Control Data 4. P0 to P3: Segment Output Port / General Purpose Port Control Data Bit 5. DR: 1/2 or 1/3 Bias Drive Control Data Bit 6. SC: Segment ON /OFF Control Data Bit 7. BU: Normal Mode/Power-Saving Mode Control Data Bit V1.1 15 November 2009 PT6526 SERIAL DATA TRANSFER SERIAL DATA TRANSFER FOR 157 OR MORE SEGMENTS SERIAL DATA TRANSFER FOR LESS THAN 157 SEGMENTS Under a serial data transfer whereby less than 157 segments are used, 64, 128 or 192 bits of serial data must be transmitted depending on the actual number of segments used. The display data bits D1 to D52 and the control data must always sent. Please refer to the figure below. V1.1 16 November 2009 PT6526 1/4 DUTY, 1/2 BIAS DRIVE TECHNIQUE V1.1 17 November 2009 PT6526 1/4 DUTY, 1/3 BIAS DRIVE TECHNIQUE V1.1 18 November 2009 PT6526 ABSOLUTE MAXIMUM RATING (Unless otherwise stated, Ta=25 oC, Vss=0V) Parameter Symbol Maximum Supply Voltage VDDmax VIN1 Input Voltage VIN2 Output Voltage Output Current Allowable Power Dissipation Operating Temperature Storage Temperature VOUT IOUT1 IOUT2 IOUT3 PDmax Topr Tstg Condition VDD CE, CLK, DI, /INH OSC, VDD1, VDD2 OSC, SG1 to SG51, COM1 to COM4, P1 to P12 SG1 to SG51 COM1 to COM4 P1 to P12 Ta=85 oC Rating -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD+0.3 Unit V V V -0.3 to VDD+0.3 V 300 3 5 200 -40 to +85 -65 to +150 µA mA mA mW o C o C ALLOWABLE OPERATING RANGE (Unless otherwise stated, Ta=25oC, Vss=0V) Parameter Symbol Supply Voltage VDD VDD1 Input Voltage VDD2 High Level Input Voltage VIH Low Level Input Voltage VIL Recommended External Rosc Resistance Recommended External Cosc Capacitance Guaranteed Oscillation fosc Range Data Setup Time tds Data Hold Time tdh CE Wait Time tcp CE Setup Time tcs CE Hold Time tch High Level Clock Pulse tΦH Width Low Level Clock Pulse tΦL Width Rise Time tr Fall Time tf /INH Switching Time tc V1.1 Condition VDD VDD1 VDD2 CE, CLK, DI, /INH CE, CLK, DI, /INH Min. 4.5 2.4 0 Typ. 2/3VDD 1/3VDD - Max. 6.0 VDD VDD VDD 0.7 Unit V V V V V OSC - 270 - KΩ OSC - 100 - pF OSC 25 50 100 KHz CLK, DI (see Note) CLK, DI (see Note) CE, CLK (see Note) CE, CLK (see Note) CE, CLK (see Note) 160 160 160 160 160 - - ns ns ns ns ns CLK (see Note) 160 - - ns CLK, (see Note) 160 - - ns CE, CLK, DI (see Note) CE, CLK, DI (see Note) /INH, CE (see Note) 10 160 160 - - ns ns µs 19 November 2009 PT6526 Notes: 1. When CLK is terminated at “LOW” level 2. When CLK is terminated at “HIGH” level. V1.1 20 November 2009 PT6526 ELECTRICAL CHARACTERISTICS (Unless otherwise stated, Ta=25oC, Vss=0V) Parameter Symbol Conditions Hysteresis VH CE, CLK, DI, /INH CE, CLK, DI, /INH High Level Input IIH VI=6.0V Current Low Level Input CE, CLK, DI, /INH IIL Current VI=0V SG1 to SG51 VOH1 Io=-20µA COM1 to COM2 High Level Output VOH2 Io=-100µA Voltage P1 to P12 VOH3 Io=-1mA SG1 to SG51 VOL1 Io=20µA COM1 to COM4 Low Level Output VOL2 Io=100µA Voltage P1 to P12 VOL3 Io=1mA COM1 to COM4 VMID1 1/2 Bias, Io=±100µA SG1 to SG51 VMID2 1/3 Bias, Io=±20µA Middle Level Output SG1 to SG51 VMID3 Voltage 1/3 Bias, Io=±20µA COM1 to COM4 VMID4 1/3 Bias, Io=±100µA COM1 to COM4 VMID5 1/3 Bias, Io=±100µA OSC Oscillation Fequency Fosc Rosc=270KΩ, Cosc=100pF IDD1 IDD2 IDD3 Current Drain IDD4 IDD5 V1.1 Power Saving Mode VDD=6V Outputs Open 1/2 Bias, fosc=50KHZ Control Data CU=0 VDD=6.0V Outputs Open 1/3 Bias, fosc=50KHz Control Data CU=0 VDD=6.0V Outputs Open 1/2 Bias, fosc=50KHz Control Data CU=1 VDD=6.0 Outputs Open 1/3 Bias, fosc=50KHz Control Data CU=1 21 Min. - Typ. 0.1VDD Max. - Unit V - - 5.0 µA -5.0 - - µA VDD-1.0 - - V VDD-1.0 - - VDD-1.0 - - V - - 1.0 V - - 1.0 V - - 1.0 V 1/2VDD-1.0 - 1/2VDD+1.0 V 2/3VDD-1.0 - 2/3VDD+1.0 V 1/3VDD-1.0 - 1/3VDD+1.0 V 2/3VDD-1.0 - 2/3VDD+1.0 V 1/3VDD-1.0 - 1/3VDD+1.0 V 40 50 60 KHz - - 5 µA - 200 400 µA - 250 500 - 130 260 - 150 300 V µA µA µA November 2009 PT6526 Note: The Bias Voltage Generation Divider built-into the VDD1 and VDD2 are not included. Please refer to the diagram below. V1.1 22 November 2009 PT6526 PACKAGE INFORMATION 64 PINS, LQFP (BODY SIZE: 10mm x 10mm, PITCH: 0.50mm, THK BODY: 1.40mm) Symbol A A1 A2 b c D D1 E E1 e L L1 Min. 0.05 1.35 0.17 0.09 11.80 9.90 11.80 9.90 Nom. Max. 1.60 0.15 1.40 1.45 0.22 0.27 0.20 12.00 12.20 10.00 10.10 12.00 12.20 10.00 10.10 0.50 BSC 0.45 0.60 0.75 1.00 REF θ 0° 3.5° 7° Notes: 1. Unit: mm 2. Refer to JEDEC MS-026BCB V1.1 23 November 2009 PT6526 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.1 24 November 2009