Download

PT6578
General Purpose LCD Driver
DESCRIPTION
PT6578 is a general purpose LCD Driver IC utilizing
CMOS technology specially designed with character
and graphical displays. It provides 1/8 to 1/10 duty and
can drive up to a maximum of 730 segment drivers and
control up to 4 general purpose ports. Housed in a
100-pin LQFP package, PT6578 can directly display
the display data without any decoder intervention,
thereby providing a high level of generality. Built-in
display contrast adjustment circuit, independent LCD
drive block power supply and serial data control of the
power saving mode based on the backup function as
well as all segments forced OFF functions are
incorporated into a single chip having the highest
performance and reliability. Pin assignments and
application circuits are optimized for easy PCB layout
and cost saving benefits.
APPLICATIONS







FEATURES
 CMOS technology
 Wide variety of bias drive techniques:
- 1/8 duty, 1/4 bias drive technique: (600 segments
max.)
- 1/9 duty, 1/4 bias drive technique: (666 segments
max.)
- 1/10 duty, 1/4 bias drive technique: (730 segments
max.)
 RC oscillation circuit
 Up to 4 general purpose output ports
 Built-in display contrast adjustment circuit
 Direct display of display data without any decoder
intervention
 All segments forced OFF function
 Serial data control of the power saving mode
based backup function
 Available in 100-pin LQFP package
Cellular phones
Data banks / organizers
Electronic dictionaries / translators
Information appliances / PDAs
Car audio systems
POS terminals
Equipment with LCD display panels
BLOCK DIAGRAM
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6578
CONTENTS
1. APPLICATION CIRCUIT ................................................................................................................................................. 3
1.1 1/8 DUTY, 1/4 BIAS DRIVE TECHNIQUE ............................................................................................................. 3
1.2 1/8 DUTY, 1/4 BIAS DRIVE TECHNIQUE ............................................................................................................. 4
1.3 1/9 DUTY, 1/4 BIAS DRIVE TECHNIQUE ............................................................................................................. 5
1.4 1/9 DUTY, 1/4 BIAS DRIVE TECHNIQUE ............................................................................................................. 6
1.5 1/10 DUTY, 1/4 BIAS DRIVE TECHNIQUE ........................................................................................................... 7
1.6 1/10 DUTY, 1/4 BIAS DRIVE TECHNIQUE ........................................................................................................... 8
2. ORDER INFORMATION .................................................................................................................................................. 9
3. PIN CONFIGURATION .................................................................................................................................................... 9
4. PIN DESCRIPTION ....................................................................................................................................................... 10
5. INPUT/OUTPUT CONFIGURATION ............................................................................................................................. 11
6. FUNCTION DESCRIPTION........................................................................................................................................... 12
6.1 CONTROL DATA BITS ........................................................................................................................................ 12
6.1.1 PC1 TO PC4: GENERAL PURPOSE OUTPUT PORT CONTROL DATA BITS .................................................... 12
6.1.2 CT0 TO CT3, CTC: DISPLAY CONTRAST CONTROL DATA BITS ...................................................................... 12
6.1.3 SC: SEGMENT ON/OFF CONTROL DATA BIT ..................................................................................................... 13
6.1.4 BU: NORMAL/POWER SAVING MODE CONTROL DATA BIT ............................................................................. 13
6.1.5 DT1, DT2: DISPLAY TECHNIQUE CONTROL DATA BITS ................................................................................... 13
6.2 /INH PIN AND DISPLAY CONTROL .................................................................................................................... 14
6.3 POWER ON/OFF ................................................................................................................................................. 14
6.3.1 1/8 DUTY ................................................................................................................................................................. 15
6.3.2 1/9 DUTY ................................................................................................................................................................. 15
6.3.3 1/10 DUTY ............................................................................................................................................................... 16
6.4 SERIAL DATA TRANSFER .................................................................................................................................. 17
6.4.1 CASE 1: 1/8 DUTY, WHEN CLK IS TERMINATED AT “LOW” LEVEL .................................................................. 17
6.4.2 CASE 2: 1/8, WHEN CLK IS TERMINATED AT “HIGH” LEVEL ............................................................................. 18
6.4.3 CASE 3: 1/9 DUTY, WHEN CLK IS TERMINATED AT “LOW” LEVEL .................................................................. 19
6.4.4 CASE 4: 1/9 DUTY, WHEN CLK IS TERMINATED AT “HIGH” LEVEL .................................................................. 20
6.4.5 CASE 5: 1/10, WHEN CLK IS TERMINATED AT “LOW” LEVEL ........................................................................... 21
6.4.6 CASE 6: 1/10 DUTY, WHEN CLK IS TERMINATED AT “HIGH” LEVEL ................................................................ 22
6.4.7 1/8 DUTY: DISPLAY DATA & OUTPUT PIN CORRESPONDENCE ...................................................................... 23
6.4.8 1/9 DUTY: DISPLAY DATA & OUTPUT PIN CORRESPONDENCE ...................................................................... 25
6.4.9 1/10 DUTY: DISPLAY DATA & OUTPUT PIN CORRESPONDENCE .................................................................... 27
6.4.10 1/8 DUTY, 1/4 BIAS DRIVE TECHNIQUE ............................................................................................................ 29
6.4.11 1/9 DUTY, 1/4 BIAS DRIVE TECHNIQUE ............................................................................................................ 30
6.4.12 1/10 DUTY, 1/4 BIAS DRIVE TECHNIQUE .......................................................................................................... 31
7. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 32
8. ALLOWABLE OPERATING RANGES .......................................................................................................................... 32
9. ELECTRICAL CHARACTERISTICS FOR THE ALLOWABLE OPERATING RANGES ............................................... 33
10. PACKAGE INFORMATION ......................................................................................................................................... 35
IMPORTANT NOTICE ...................................................................................................................................................... 36
V2.1
2
June 2014
PT6578
1. APPLICATION CIRCUIT
1.1 1/8 DUTY, 1/4 BIAS DRIVE TECHNIQUE
(for Normal Panel Use)
Notes:
1. C  0.047 F
2. If the Variable Resistor is not used for the display contrast adjustment, the VLCD4 in must be connected to the ground.
V2.1
3
June 2014
PT6578
1.2 1/8 DUTY, 1/4 BIAS DRIVE TECHNIQUE
(for Large Panel Use)
Notes:
1. C  0.047 F
2. If the Variable resistor is not used for the display contrast fine adjustment, the VLCD4 pin must be connected to the Ground.
V2.1
4
June 2014
PT6578
1.3 1/9 DUTY, 1/4 BIAS DRIVE TECHNIQUE
(For Normal Panel Use)
Notes:
1. C  0.047 F
2. If the Variable Resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to Ground.
V2.1
5
June 2014
PT6578
1.4 1/9 DUTY, 1/4 BIAS DRIVE TECHNIQUE
(For Large Panel Use)
Notes:
1. C  0.047 F
2. If the Variable Resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to the Ground.
V2.1
6
June 2014
PT6578
1.5 1/10 DUTY, 1/4 BIAS DRIVE TECHNIQUE
(For Normal Panel Use)
Notes:
1. C  0.047 F
2. If the Variable Resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to the ground.
V2.1
7
June 2014
PT6578
1.6 1/10 DUTY, 1/4 BIAS DRIVE TECHNIQUE
(For Large Panel Use)
Notes:
1. C  0.047 F
2. If the Variable Resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to the ground.
V2.1
8
June 2014
PT6578
2. ORDER INFORMATION
Valid Part Number
PT6578LQ
Package Type
100-pin, LQFP
Top Code
PT6578LQ
3. PIN CONFIGURATION
V2.1
9
June 2014
PT6578
4. PIN DESCRIPTION
Pin Name
SG1 ~ SG73
SG74/COM10 ~ SG75/COM9
COM1 ~ COM8
P1 ~ P4
VDD
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VSS
OSC
/INH
CE
CLK
DI
V2.1
I/O
O
O
O
O
I/O
I
I
I
I
Description
Segment driver output pin
Segment/Common driver output pin
Common driver output pin
General purpose output port
Logic power supply
LCD driver block power supply
LCD drive 4/4 bias voltage power supply
LCD drive 3/4 bias voltage power supply
LCD drive 2/4 bias voltage power supply
LCD drive 1/4 bias voltage power supply
LCD drive 0/4 bias voltage power supply
Ground pin
Oscillator input/output pin
Display off control input pin
Chip enable input pin
Clock input pin
Data input pin
10
Pin No.
1 ~ 73
74 ~ 75
83 ~ 76
84 ~ 87
88
89
90
91
92
93
94
95
96
97
98
99
100
June 2014
PT6578
5. INPUT/OUTPUT CONFIGURATION
The schematic diagrams of the input and output circuits of the logic section are shown below:
INPUT PIN: CLK, CE, DI, /INH
OUTPUT PIN: SG1 TO SG73
OUTPUT PIN: P1 TO P4
OUTPUT PIN: COM1/COM8,
SG75/COM9, SG74 TO COM10
V2.1
11
June 2014
PT6578
6. FUNCTION DESCRIPTION
6.1 CONTROL DATA BITS
6.1.1 PC1 TO PC4: GENERAL PURPOSE OUTPUT PORT CONTROL DATA BITS
These control bits are used to select the states of the General Purpose Output Ports P1 to P4. Please refer to the table
below for the setting correspondence.
Output Pin
P1
P2
P3
P4
General Purpose Output Port State Setting Data
PC1
PC2
PC3
PC4
If any of the control bits (PC1 to PC4) are set to “1”, then the corresponding General Purpose Output Port (P1 to P4) will
output high level (VDD). On the other hand, if the control bit is set to “0”, then the corresponding General Purpose Output
Port (P1 to P4) will output low level (Vss).
For clarity, an illustration will be given. IF PC1 and PC2 are both set to “1”, PC3 and PC4 are both set to “0”, the General
Purpose Output Ports – P1 and P2 will output high levels (VDD) while P3 and P4 will output low levels (Vss).
6.1.2 CT0 TO CT3, CTC: DISPLAY CONTRAST CONTROL DATA BITS
These control data bits are used to set the display contrast. CT0 to CT3 are used to set the display contrast in 11 steps,
while CTC is used to set the display contrast circuit. The CT0 to CT3 Display Contrast Setting Data is given below.
CT0
CT1
CT2
CT3
LCD Drive 4/4 Bias Voltage Supply VLCD0 Level
0
0
0
0
0.94VLCD = VLCD - (0.03VLCD x 2)
1
0
0
0
0.91VLCD = VLCD - (0.03VLCD x 3)
0
1
0
0
0.88VLCD = VLCD - (0.03VLCD x 4)
1
1
0
0
0.85VLCD = VLCD - (0.03VLCD x 5)
0
0
1
0
0.82VLCD = VLCD - (0.03VLCD x 6)
1
0
1
0
0.79VLCD = VLCD - (0.03VLCD x 7)
0
1
1
0
0.76VLCD = VLCD - (0.03VLCD x 8)
1
1
1
0
0.73VLCD = VLCD - (0.03VLCD x 9)
0
0
0
1
0.70VLCD = VLCD - (0.03VLCD x 10)
1
0
0
1
0.67VLCD = VLCD - (0.03VLCD x 11)
0
1
0
1
0.64VLCD = VLCD - (0.03VLCD x 12)
The CTC Display Contrast Adjustment Circuit Setting is given in the table below.
CTC
State of the Display Contrast Adjustment Circuit
Display Contrast Adjustment Circuit is DISABLED, the level of the VLCD0 Pin is
0
forced to the VLCD Level.
Display Contrast Adjustment Circuit is ENABLED, Display Contrast can be
1
adjusted.
It is also important to note that fine adjustments to the contrast may also be applied by connecting an external variable
resistor to the VLCD4 pin and changing the value of the VLCD4 pin voltage. In order to do this, the following conditions
must be applied:
(VLCD0 - VLCD4)  4.5 V
1.5 V  VLCD4  0 V
V2.1
12
June 2014
PT6578
6.1.3 SC: SEGMENT ON/OFF CONTROL DATA BIT
This control data bit is used to set the state of the Segments (either ON or OFF). If the SC is set to “0, then the segment
display is enabled. On the other hand, if the SC is set to “1”, then the display is disabled. Please refer to the table below.
SC
Display State
0
ON
1
OFF
It is important to note that if the segments are disabled via the setting of the SC bit to “1”, then the segments are turned
OFF by outputting Segment OFF waveforms from the segment output pins.
6.1.4 BU: NORMAL/POWER SAVING MODE CONTROL DATA BIT
This control data bit is used to select either the Normal Mode or the Power Saving Mode. If BU is set to “0”, the Normal
Mode is active. On the other hand, if the BU is set to “1”, then the Power Saving Mode is active. Under the Power Saving
Mode, the Common and Segment Driver Output Pins are set to the V LCD4 level and the oscillation circuit operation is
terminated. It is important to note that the states of the General Purpose Output Ports – P1 to P4 are set by the states of
PC1 to PC4 respectively in both the Normal Mode and the Power Saving Mode. Please refer to the table below.
BU
Mode
0
Normal Mode
1
Power Saving Mode
6.1.5 DT1, DT2: DISPLAY TECHNIQUE CONTROL DATA BITS
These control data bits are used to set the display techniques. Please refer to the table below.
Output Pin
DT1
DT2
Display Technique
SG75/COM9
SG74/COM10
0
0
1/8 Duty, 1/4 Bias Drive
SG75
SG74
1
0
1/9 Duty, 1/4 Bias Drive
COM9
SG74
0
1
1/10 Duty, 1/4 Bias Drive
COM9
COM10
V2.1
13
June 2014
PT6578
6.2 /INH PIN AND DISPLAY CONTROL
When power is first applied, the PT6578 internal data (display data and control data) are not defined, thus the contents of
the internal data must be cleared. Applications should set the /INH pin to “LOW” level at the same time as the power is
applied to clear the display. This will set the SG1 to SG73, SG74/COM10 and SG75/COM9 pins to the VLCD4 level and
the General Purpose Output Ports – P1 to P4 to the Vss Level. The serial data must be sent to the controller during this
period. The controller then sets the /INH pin to ”HIGH” level after the data transfer has been completed. The above
procedures are recommended to prevent meaningless and random displays during Power ON. Please refer to the
diagrams for 1/8, 1/9, 1/10 Duty found in the following pages.
Notes:
1. t1 ≥ 0
2. t2 > 0
3. t3 ≥ 0 (t2 > t3)
4. tc ….. 10 s minimum
5. tc is determined by the Value of C and R
6.3 POWER ON/OFF
Certain conditions are observed when turning the Power ON or OFF. Please refer to the diagrams for 1/8, 1/9, 1/10 Duty
in the following pages.
The following must be observed when turning the Power ON.
1. Turn Logic Block Power Supply (VDD) ON.
2. Turn LCD Driver Block Power Supply (VLCD) ON.
The following order must be observed when turning the Power OFF.
1. Turn LCD Driver Block Power Supply (VLCD) OFF.
2. Turn Logic Block Power Supply (VDD) OFF.
If both the Logic and the LCD Driver Blocks use the same power supply, then the power may be tuned ON or OFF at the
same time.
V2.1
14
June 2014
PT6578
6.3.1 1/8 DUTY
Figure 1
6.3.2 1/9 DUTY
Figure 2
V2.1
15
June 2014
PT6578
6.3.3 1/10 DUTY
Figure 3
V2.1
16
June 2014
PT6578
6.4 SERIAL DATA TRANSFER
6.4.1 CASE 1: 1/8 DUTY, WHEN CLK IS TERMINATED AT “LOW” LEVEL
The figure below refers to the condition when Display Data is transferred.
The diagram below refers to the condition when the control data is transferred.
where: DD = Direction Data
V2.1
17
June 2014
PT6578
6.4.2 CASE 2: 1/8, WHEN CLK IS TERMINATED AT “HIGH” LEVEL
The diagram below refers to the condition when the Display Data is transferred.
The diagram below refers to the condition when the control data is transferred.
where:
1. DD = Display Data
2. Address: 4BH
V2.1
18
June 2014
PT6578
6.4.3 CASE 3: 1/9 DUTY, WHEN CLK IS TERMINATED AT “LOW” LEVEL
The diagram below refers to the condition when the Display Data is transferred.
The diagram below refers to the condition when the control data is transferred.
where:
1. DD = Display Data
2. Address: 4BH
V2.1
19
June 2014
PT6578
6.4.4 CASE 4: 1/9 DUTY, WHEN CLK IS TERMINATED AT “HIGH” LEVEL
The diagram below refers to the condition when the Display Data is transferred.
The diagram below refers to the condition when the control data is transferred.
where:
1. DD = Display Data
2. Address: 4BH
V2.1
20
June 2014
PT6578
6.4.5 CASE 5: 1/10, WHEN CLK IS TERMINATED AT “LOW” LEVEL
The diagram below refers to the condition when the Display Data is transferred.
0
The diagram below refers to the condition when the control data is transferred.
where: DD = Direction Data
V2.1
21
June 2014
PT6578
6.4.6 CASE 6: 1/10 DUTY, WHEN CLK IS TERMINATED AT “HIGH” LEVEL
The diagram below refers to the condition when the Display Data is transferred.
0
The diagram below refers to the condition when the control data is transferred.
where:
1. DD = Direction Data
2. Address: 4BH
V2.1
22
June 2014
PT6578
6.4.7 1/8 DUTY: DISPLAY DATA & OUTPUT PIN CORRESPONDENCE
Output Pin
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SG14
SG15
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SG23
SG24
SG25
SG26
SG27
SG28
SG29
SG30
SG31
SG32
SG33
SG34
SG35
SG36
SG37
SG38
SG39
SG40
SG41
SG42
SG43
SG44
SG45
SG46
SG47
SG48
SG49
SG50
V2.1
COM1
D1
D9
D17
D25
D33
D41
D49
D57
D65
D73
D81
D89
D97
D105
D113
D121
D129
D137
D145
D153
D161
D169
D177
D185
D193
D201
D209
D217
D225
D233
D241
D249
D257
D265
D273
D281
D289
D297
D305
D313
D321
D329
D337
D345
D353
D361
D369
D377
D385
D393
COM2
D2
D10
D18
D26
D34
D42
D50
D58
D66
D74
D82
D90
D98
D106
D114
D122
D130
D138
D146
D154
D162
D170
D178
D186
D194
D202
D210
D218
D226
D234
D242
D250
D258
D266
D274
D282
D290
D298
D306
D314
D322
D330
D338
D346
D354
D362
D370
D378
D386
D394
COM3
D3
D11
D19
D27
D35
D43
D51
D59
D67
D75
D83
D91
D99
D107
D115
D123
D131
D139
D147
D155
D163
D171
D179
D187
D195
D203
D211
D219
D227
D235
D243
D251
D259
D267
D275
D283
D291
D299
D307
D315
D323
D331
D339
D347
D355
D363
D371
D379
D387
D395
COM4
D4
D12
D20
D28
D36
D44
D52
D60
D68
D76
D84
D92
D100
D108
D116
D124
D132
D140
D148
D156
D164
D172
D180
D188
D196
D204
D212
D220
D228
D236
D244
D252
D260
D268
D276
D284
D292
D300
D308
D316
D324
D332
D340
D348
D356
D364
D372
D380
D388
D396
23
COM5
D5
D13
D21
D29
D37
D45
D53
D61
D69
D77
D85
D93
D101
D109
D117
D125
D133
D141
D149
D157
D165
D173
D181
D189
D197
D205
D213
D221
D229
D237
D245
D253
D261
D269
D277
D285
D293
D301
D309
D317
D325
D333
D341
D349
D357
D365
D373
D381
D389
D397
COM6
D6
D14
D22
D30
D38
D46
D54
D62
D70
D78
D86
D94
D102
D110
D118
D126
D134
D142
D150
D158
D166
D174
D182
D190
D198
D206
D214
D222
D230
D238
D246
D254
D262
D270
D278
D286
D294
D302
D310
D318
D326
D334
D342
D350
D358
D366
D374
D382
D390
D398
COM7
D7
D15
D23
D31
D39
D47
D55
D63
D71
D79
D87
D95
D103
D111
D119
D127
D135
D143
D151
D159
D167
D175
D183
D191
D199
D207
D215
D223
D231
D239
D247
D255
D263
D271
D279
D287
D295
D303
D311
D319
D327
D335
D343
D351
D359
D367
D375
D383
D391
D399
COM8
D8
D16
D24
D32
D40
D48
D56
D64
D72
D80
D88
D96
D104
D112
D120
D128
D136
D144
D152
D160
D168
D176
D184
D192
D200
D208
D216
D224
D232
D240
D248
D256
D264
D272
D280
D288
D296
D304
D312
D320
D328
D336
D344
D352
D360
D368
D376
D384
D392
D400
June 2014
PT6578
Output Pin
SG51
SG52
SG53
SG54
SG55
SG56
SG57
SG58
SG59
SG60
SG61
SG62
SG63
SG64
SG65
SG66
SG67
SG68
SG69
SG70
SG71
SG72
SG73
SG74/COM10
SG75/COM9
COM1
D401
D409
D417
D425
D433
D441
D449
D457
D465
D473
D481
D489
D497
D505
D513
D521
D529
D537
D545
D553
D561
D569
D577
D585
D593
COM2
D402
D410
D418
D426
D434
D442
D450
D458
D466
D474
D482
D490
D498
D506
D514
D522
D530
D538
D546
D554
D562
D570
D578
D586
D594
COM3
D403
D411
D419
D427
D435
D443
D451
D459
D467
D475
D483
D491
D499
D507
D515
D523
D531
D539
D547
D555
D563
D571
D579
D587
D595
COM4
D404
D412
D420
D428
D436
D444
D452
D460
D468
D476
D484
D492
D500
D508
D516
D524
D532
D540
D548
D556
D564
D572
D580
D588
D596
COM5
D405
D413
D421
D429
D437
D445
D453
D461
D469
D477
D485
D493
D501
D509
D517
D525
D533
D541
D549
D557
D565
D573
D581
D589
D597
COM6
D406
D414
D422
D430
D438
D446
D454
D462
D470
D478
D486
D494
D502
D510
D518
D526
D534
D542
D550
D558
D566
D574
D582
D590
D598
COM7
D407
D415
D423
D431
D439
D447
D455
D463
D471
D479
D487
D495
D503
D511
D519
D527
D535
D543
D551
D559
D567
D575
D583
D591
D599
COM8
D408
D416
D424
D432
D440
D448
D456
D464
D472
D480
D488
D496
D504
D512
D520
D528
D536
D544
D552
D560
D568
D576
D584
D592
D600
Note: The above table assumes that the SG74/COM10 and SG75/COM9 are used as Segment Driver Output Pins.
In order to make things clearer, an example will be given in the table below for the Segment Driver Output Pin SG11.
Display Data
State of SG11
D81
D82
D83
D84
D85
D86
D87
D88
0
0
0
0
0
0
0
0
LCD Segments for COM1 to COM8 are OFF.
1
0
0
0
0
0
0
0
LCD Segment for COM1 is ON.
0
1
0
0
0
0
0
0
LCD Segment for COM2 is ON.
0
0
1
0
0
0
0
0
LCD Segment for COM3 is ON.
0
0
0
1
0
0
0
0
LCD Segment for COM4 is ON.
0
0
0
0
1
0
0
0
LCD Segment for COM5 is ON.
0
0
0
0
0
1
0
0
LCD Segment for COM6 is ON.
0
0
0
0
0
0
1
0
LCD Segment for COM7 is ON.
0
0
0
0
0
0
0
1
LCD Segment for COM8 is ON.
1
1
1
1
1
1
1
1
LCD Segment for COM1 to COM 8 are ON.
V2.1
24
June 2014
PT6578
6.4.8 1/9 DUTY: DISPLAY DATA & OUTPUT PIN CORRESPONDENCE
Output Pin
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SG14
SG15
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SG23
SG24
SG25
SG26
SG27
SG28
SG29
SG30
SG31
SG32
SG33
SG34
SG35
SG36
SG37
SG38
SG39
SG40
SG41
SG42
SG43
SG44
SG45
SG46
SG47
SG48
SG49
SG50
V2.1
COM1
D1
D10
D19
D28
D37
D46
D55
D64
D73
D82
D91
D100
D109
D118
D127
D136
D145
D154
D163
D172
D181
D190
D199
D208
D217
D226
D235
D244
D253
D262
D271
D280
D289
D298
D307
D316
D325
D334
D343
D352
D361
D370
D379
D388
D397
D406
D415
D424
D433
D442
COM2
D2
D11
D20
D29
D38
D47
D56
D65
D74
D83
D92
D101
D110
D119
D128
D137
D146
D155
D164
D173
D182
D191
D200
D209
D218
D227
D236
D245
D254
D263
D272
D281
D290
D299
D308
D317
D326
D335
D344
D353
D362
D371
D380
D389
D398
D407
D416
D425
D434
D443
COM3
D3
D12
D21
D30
D39
D48
D57
D66
D75
D84
D93
D102
D111
D120
D129
D138
D147
D156
D165
D174
D183
D192
D201
D210
D219
D228
D237
D246
D255
D264
D273
D282
D291
D300
D309
D318
D327
D336
D345
D354
D363
D372
D381
D390
D399
D408
D417
D426
D435
D444
COM4
D4
D13
D22
D31
D40
D49
D58
D67
D76
D85
D94
D103
D112
D121
D130
D139
D148
D157
D166
D175
D184
D193
D202
D211
D220
D229
D238
D247
D256
D265
D274
D283
D292
D301
D310
D319
D328
D337
D346
D355
D364
D373
D382
D391
D400
D409
D418
D427
D436
D445
25
COM5
D5
D14
D23
D32
D41
D50
D59
D68
D77
D86
D95
D104
D113
D122
D131
D140
D149
D158
D167
D176
D185
D194
D203
D212
D221
D230
D239
D248
D257
D266
D275
D284
D293
D302
D311
D320
D329
D338
D347
D356
D365
D374
D383
D392
D401
D410
D419
D428
D437
D446
COM6
D6
D15
D24
D33
D42
D51
D60
D69
D78
D87
D96
D105
D114
D123
D132
D141
D150
D159
D168
D177
D186
D195
D204
D213
D222
D231
D240
D249
D258
D267
D276
D285
D294
D303
D312
D321
D330
D339
D348
D357
D366
D375
D384
D393
D402
D411
D420
D429
D438
D447
COM7
D7
D16
D25
D34
D43
D52
D61
D70
D79
D88
D97
D106
D115
D124
D133
D142
D151
D160
D169
D178
D187
D196
D205
D214
D223
D232
D241
D250
D259
D268
D277
D286
D295
D304
D313
D322
D331
D340
D349
D358
D367
D376
D385
D394
D403
D412
D421
D430
D439
D448
COM8
D8
D17
D26
D35
D44
D53
D62
D71
D80
D89
D98
D107
D116
D125
D134
D143
D152
D161
D170
D179
D188
D197
D206
D215
D224
D233
D242
D251
D260
D269
D278
D287
D296
D305
D314
D323
D332
D341
D350
D359
D368
D377
D386
D395
D404
D413
D422
D431
D440
D449
COM9
D9
D18
D27
D36
D45
D54
D63
D72
D81
D90
D99
D108
D117
D126
D135
D144
D153
D162
D171
D180
D189
D198
D207
D216
D225
D234
D243
D252
D261
D270
D279
D288
D297
D306
D315
D324
D333
D342
D351
D360
D369
D378
D387
D396
D405
D414
D423
D432
D441
D450
June 2014
PT6578
Output Pin
SG51
SG52
SG53
SG54
SG55
SG56
SG57
SG58
SG59
SG60
SG61
SG62
SG63
SG64
SG65
SG66
SG67
SG68
SG69
SG70
SG71
SG72
SG73
SG74/COM10
COM1
D451
D460
D469
D478
D487
D496
D505
D514
D523
D532
D541
D550
D559
D568
D577
D586
D595
D604
D613
D622
D631
D640
D649
D658
COM2
D452
D461
D470
D479
D488
D497
D506
D515
D524
D533
D542
D551
D560
D569
D578
D587
D596
D605
D614
D623
D632
D641
D650
D659
COM3
D453
D462
D471
D480
D489
D498
D507
D516
D525
D534
D543
D552
D561
D570
D579
D588
D597
D606
D615
D624
D633
D642
D651
D660
COM4
D454
D463
D472
D481
D490
D499
D508
D517
D526
D535
D544
D553
D562
D571
D580
D589
D598
D607
D616
D625
D634
D643
D652
D661
COM5
D455
D464
D473
D482
D491
D500
D509
D518
D527
D536
D545
D554
D563
D572
D581
D590
D599
D608
D617
D626
D635
D644
D653
D662
COM6
D456
D465
D474
D483
D492
D501
D510
D519
D528
D537
D546
D555
D564
D573
D582
D591
D600
D609
D618
D627
D636
D645
D654
D663
COM7
D457
D466
D475
D484
D493
D502
D511
D520
D529
D538
D547
D556
D565
D574
D583
D592
D601
D610
D619
D628
D637
D646
D655
D664
COM8
D458
D467
D476
D485
D494
D503
D512
D521
D530
D539
D548
D557
D566
D575
D584
D593
D602
D611
D620
D629
D638
D647
D656
D665
COM9
D459
D468
D477
D486
D495
D504
D513
D522
D531
D540
D549
D558
D567
D576
D585
D594
D603
D612
D621
D630
D639
D648
D657
D666
In order to make things clearer, an example will be given in the table below for the Segment Driver Output Pin SG11.
Display Data
State of Output Pin (S11)
D91 D92 D93 D94 D95 D96 D97 D98 D99
The LCD Segments for COM1 to COM9 are
0
0
0
0
0
0
0
0
0
OFF.
1
0
0
0
0
0
0
0
0
The LCD Segment for COM1 is ON.
0
1
0
0
0
0
0
0
0
The LCD Segment for COM2 is ON.
0
0
1
0
0
0
0
0
0
The LCD Segment for COM3 is ON.
0
0
0
1
0
0
0
0
0
The LCD Segment for COM4 is ON.
0
0
0
0
1
0
0
0
0
The LCD Segment for COM5 is ON.
0
0
0
0
0
1
0
0
0
The LCD Segment for COM6 is ON.
0
0
0
0
0
0
1
0
0
The LCD Segment for COM7 is ON.
0
0
0
0
0
0
0
1
0
The LCD Segment for COM8 is ON.
0
0
0
0
0
0
0
0
1
The LCD Segment for COM9 is ON.
1
1
1
1
1
1
1
1
1
The LCD Segments for COM1 to COM9 are ON.
V2.1
26
June 2014
PT6578
6.4.9 1/10 DUTY: DISPLAY DATA & OUTPUT PIN CORRESPONDENCE
Output Pin
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SG14
SG15
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SG23
SG24
SG25
SG26
SG27
SG28
SG29
SG30
SG31
SG32
SG33
SG34
SG35
SG36
SG37
SG38
SG39
SG40
SG41
SG42
SG43
SG44
SG45
SG46
SG47
SG48
SG49
SG50
V2.1
COM1
D1
D11
D21
D31
D41
D51
D61
D71
D81
D91
D101
D111
D121
D131
D141
D151
D161
D171
D181
D191
D201
D211
D221
D231
D241
D251
D261
D271
D281
D291
D301
D311
D321
D331
D341
D351
D361
D371
D381
D391
D401
D411
D421
D431
D441
D451
D461
D471
D481
D491
COM2
D2
D12
D22
D32
D42
D52
D62
D72
D82
D92
D102
D112
D122
D132
D142
D152
D162
D172
D182
D192
D202
D212
D222
D232
D242
D252
D262
D272
D282
D292
D302
D312
D322
D332
D342
D352
D362
D372
D382
D392
D402
D412
D422
D432
D442
D452
D462
D472
D482
D492
COM3
D3
D13
D23
D33
D43
D53
D63
D73
D83
D93
D103
D113
D123
D133
D143
D153
D163
D173
D183
D193
D203
D213
D223
D233
D243
D253
D263
D273
D283
D293
D303
D313
D323
D333
D343
D353
D363
D373
D383
D393
D403
D413
D423
D433
D443
D453
D463
D473
D483
D493
COM4
D4
D14
D24
D34
D44
D54
D64
D74
D84
D94
D104
D114
D124
D134
D144
D154
D164
D174
D184
D194
D204
D214
D224
D234
D244
D254
D264
D274
D284
D294
D304
D314
D324
D334
D344
D354
D364
D374
D384
D394
D404
D414
D424
D434
D444
D454
D464
D474
D484
D494
COM5
D5
D15
D25
D35
D45
D55
D65
D75
D85
D95
D105
D115
D125
D135
D145
D155
D165
D175
D185
D195
D205
D215
D225
D235
D245
D255
D265
D275
D285
D295
D305
D315
D325
D335
D345
D355
D365
D375
D385
D395
D405
D415
D425
D435
D445
D455
D465
D475
D485
D495
27
COM6
D6
D16
D26
D36
D46
D56
D66
D76
D86
D96
D106
D116
D126
D136
D146
D156
D166
D176
D186
D196
D206
D216
D226
D236
D246
D256
D266
D276
D286
D296
D306
D316
D326
D336
D346
D356
D366
D376
D386
D396
D406
D416
D426
D436
D446
D456
D466
D476
D486
D496
COM7
D7
D17
D27
D37
D47
D57
D67
D77
D87
D97
D107
D117
D127
D137
D147
D157
D167
D177
D187
D197
D207
D217
D227
D237
D247
D257
D267
D277
D287
D297
D307
D317
D327
D337
D347
D357
D367
D377
D387
D397
D407
D417
D427
D437
D447
D457
D467
D477
D487
D497
COM8
D8
D18
D28
D38
D48
D58
D68
D78
D88
D98
D108
D118
D128
D138
D148
D158
D168
D178
D188
D198
D208
D218
D228
D238
D248
D258
D268
D278
D288
D298
D308
D318
D328
D338
D348
D358
D368
D378
D388
D398
D408
D418
D428
D438
D448
D458
D468
D478
D488
D498
COM9
D9
D19
D29
D39
D49
D59
D69
D79
D89
D99
D109
D119
D129
D139
D149
D159
D169
D179
D189
D199
D209
D219
D229
D239
D249
D259
D269
D279
D289
D299
D309
D319
D329
D339
D349
D359
D369
D379
D389
D399
D409
D419
D429
D439
D449
D459
D469
D479
D489
D499
COM10
D10
D20
D30
D40
D50
D60
D70
D80
D90
D100
D110
D120
D130
D140
D150
D160
D170
D180
D190
D200
D210
D220
D230
D240
D250
D260
D270
D280
D290
D300
D310
D320
D330
D340
D350
D360
D370
D380
D390
D400
D410
D420
D430
D440
D450
D460
D470
D480
D490
D500
June 2014
PT6578
Output Pin
SG51
SG52
SG53
SG54
SG55
SG56
SG57
SG58
SG59
SG60
SG61
SG62
SG63
SG64
SG65
SG66
SG67
SG68
SG69
SG70
SG71
SG72
SG73
COM1
D501
D511
D521
D531
D541
D551
D561
D571
D581
D591
D601
D611
D621
D631
D641
D651
D661
D671
D681
D691
D701
D711
D721
COM2
D502
D512
D522
D532
D542
D552
D562
D572
D582
D592
D602
D612
D622
D632
D642
D652
D662
D672
D682
D692
D702
D712
D722
COM3
D503
D513
D523
D533
D543
D553
D563
D573
D583
D593
D603
D613
D623
D633
D643
D653
D663
D673
D683
D693
D703
D713
D723
COM4
D504
D514
D524
D534
D544
D554
D564
D574
D584
D594
D604
D614
D624
D634
D644
D654
D664
D674
D684
D694
D704
D714
D724
COM5
D505
D515
D525
D535
D545
D555
D565
D575
D585
D595
D605
D615
D625
D635
D645
D655
D665
D675
D685
D695
D705
D715
D725
COM6
D506
D516
D526
D536
D546
D556
D566
D576
D586
D596
D606
D616
D626
D636
D646
D656
D666
D676
D686
D696
D706
D716
D726
The table below gives a list of segment output states for the output pin SG11.
Display Data
D101 D102 D103 D104 D105 D106 D107 D108 D109 D110
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
V2.1
28
COM7
D507
D517
D527
D537
D547
D557
D567
D577
D587
D597
D607
D617
D627
D637
D647
D657
D667
D677
D687
D697
D707
D717
D727
COM8
D508
D518
D528
D538
D548
D558
D568
D578
D588
D598
D608
D618
D628
D638
D648
D658
D668
D678
D688
D698
D708
D718
D728
COM9
D509
D519
D529
D539
D549
D559
D569
D579
D589
D599
D609
D619
D629
D639
D649
D659
D669
D679
D689
D699
D709
D719
D729
COM10
D510
D520
D530
D540
D550
D560
D570
D580
D590
D600
D610
D620
D630
D640
D650
D660
D670
D680
D690
D700
D710
D720
D730
State of Output Pin (SG11)
The LCD Segments for COM1 to
COM10 are OFF.
The LCD Segment for COM1 is ON.
The LCD Segment for COM2 is ON.
The LCD Segment for COM3 is ON.
The LCD Segment for COM4 is ON.
The LCD Segment for COM5 is ON.
The LCD Segment for COM6 is ON.
The LCD Segment for COM7 is ON.
The LCD Segment for COM8 is ON.
The LCD Segment for COM9 is ON.
The LCD Segment for COM10 is ON.
The LCD Segments for COM1 to
COM10 are ON.
June 2014
PT6578
6.4.10 1/8 DUTY, 1/4 BIAS DRIVE TECHNIQUE
where: T = 1/fosc
V2.1
29
June 2014
PT6578
6.4.11 1/9 DUTY, 1/4 BIAS DRIVE TECHNIQUE
where: T = 1/fosc
V2.1
30
June 2014
PT6578
6.4.12 1/10 DUTY, 1/4 BIAS DRIVE TECHNIQUE
where: T = 1/fosc
V2.1
31
June 2014
PT6578
7. ABSOLUTE MAXIMUM RATINGS
(Ta = 25℃, VSS = 0V)
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDDmax
VLCD
VIN1
VIN2
VIN3
VOUT1
VOUT2
IOUT1
IOUT2
IOUT3
Pd max
Topr
Tstg
Conditions
VDD
VLCD
CE, CLK, DI, /INH
OSC
VLCD1, VLCD2, VLCD3, VLCD4
OSC, P1 to P4
VLCD0 , SG1 to SG75, COM1 to COM10
SG1 to SG75
COM1 to COM10
P1 to P4
Ta = 85℃
-
Ratings
-0.3 to +7.0
-0.3 to +12.0
-0.3 to VDD+0.3
-0.3 to VDD+0.3
-0.3 to VLCD+0.3
-0.3 to VDD+0.3
-0.3 to VLCD+0.3
300
3
5
200
-40 to +85
-65 to +150
Unit
V
V
V
μA
mA
mW
℃
℃
8. ALLOWABLE OPERATING RANGES
(Ta = 25℃, VSS = 0V)
Parameter
Supply voltage
Output voltage
Input voltage
Input high-level voltage
Input low-level voltage
Hysteresis
Recommended external
resistance
Recommended external
capacitance
Guaranteed oscillation range
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
/INH switching time
V2.1
Symbol
VDD
VLCD0
Conditions
VDD
VLCD, when the display
contrast adjustment
circuit is used
VLCD, when the display
contrast adjustment
circuit is not used
VLCD0
VLCD1
VLCD1
-
VLCD2
VLCD2
-
VLCD3
VLCD3
-
VLCD4
VIH
VIL
VH
VLCD4
CE, CLK, DI, /INH
CE, CLK, DI, /INH
CE, CLK, DI, /INH
ROSC
OSC
-
43
-
KΩ
COSC
OSC
-
680
-
pF
FOSC
tds
tdh
tcp
tcs
tch
tOH
tOL
tc
OSC
CLK, DI: figure 4
CLK, DI: figure 4
CE, CLK: figure 4
CE, CLK: figure 4
CE, CLK: figure 4
CLK
CLK
/INH, CE: figures 1, 2, 3
25
160
160
160
160
160
160
160
10
-
150
-
KHz
ns
ns
ns
ns
ns
ns
ns
s
VLCD
32
Min.
2.7
Typ.
-
Max.
6.0
7.0
-
11.0
Unit
V
4.5
-
11.0
VLCD4+4.5
VLCD
0
0.8VDD
0
-
3/4 (VLCD0 –
VLCD4)
2/4 (VLCD0 –
VLCD4)
1/4 (VLCD0 –
VLCD4)
0.1VDD
1.5
6.0
0.2VDD
-
V
V
V
V
VLCD0
VLCD0
V
VLCD0
June 2014
PT6578
9. ELECTRICAL CHARACTERISTICS FOR THE
ALLOWABLE OPERATING RANGES
(Ta = 25℃, VSS = 0V)
Parameter
Input high-level current
Input low-level current
Output high-level voltage
Output low-level voltage
Output middle-level
voltage *
Oscillator frequency
Symbol
IIH
IIL
VOH1
VOH2
VOH3
VOL1
VOL2
VOL3
VMID1
SG1 to SG75: IO = ±20 μA
VMID2
COM1 to COM10: IO = ±100 μA
VMID3
COM1 to COM10: IO = ±100 A
FOSC
IDD1
IDD2
ILCD1
Current drain
Conditions
CE, CLK, DI, /INH: VI = VDD
CE, CLK, DI, /INH: VI = 0V
SG1 to SG75: IO = -20 μA
COM1 to COM10: IO = -100 μA
P1 to P4: IO = -1 mA
SG1 to SG75: IO = 20 μA
COM1 to COM10: IO = 100 μA
P1 to P4: IO = 1 mA
ILCD2
ILCD3
OSC: ROSC = 43 KΩ,
COSC = 680 pF
VDD: Power saving mode
VDD: VDD = 6.0 V, outputs open,
fosc = 50 KHz
VLCD: Power saving mode
VLCD: VLCD = 11.0V, outputs
open, Fosc = 50 KHz
When the display contrast
adjustment circuit is used.
VLCD: VLCD = 11.0 V, outputs
open, Fosc=50 KHz
When the display contrast
adjustment circuit is not used.
Min.
-5.0
VLCD0 – 0.6
VLCD0 – 0.6
VDD – 1.0
2/4(VLCD0 –
VLCD4) – 0.6
3/4(VLCD0 –
VLCD4) – 0.6
1/4(VLCD0 –
VLCD4) – 0.6
Typ.
-
Max.
5.0
VLCD4 + 0.6
VLCD4 + 0.6
1.0
2/4(VLCD0 –
VLCD4) + 0.6
3/4(VLCD0 –
VLCD4) + 0.6
1/4(VLCD0 –
VLCD4) + 0.6
Unit
μA
μA
40
50
60
KHz
-
-
5
-
200
400
-
-
V
V
V
5
-
500
1000
-
250
500
μA
Note: * = Excluding the bias voltage generation divider resistor built into VLCD0, VLCD1, VLCD2, VLCD3, and VLCD4
V2.1
33
June 2014
PT6578
When CLK is stopped at the low level:
When CLK is stopped at the high level:
Figure 4
V2.1
34
June 2014
PT6578
10. PACKAGE INFORMATION
100 PINS, LQFP PACKAGE
Symbol
A
A1
A2
b
c
D
D1
E
E1
e
L1
θ
Min.
0.05
1.35
0.17
0.09
Nom.
1.40
0.22
16.00 BSC
14.00 BSC
16.00 BSC
14.00 BSC
0.50 BSC
1.00 REF
3.5°
0°
Max.
1.60
0.15
1.45
0.27
0.20
7°
Notes:
1. All controlling dimensions are in millimeters.
2. Refer to JEDEC MS-026BED
V2.1
35
June 2014
PT6578
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.
Princeton Technology Corp.
2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw
V2.1
36
June 2014