PCS3P7101A September 2006 rev 0.1 Low Power Peak EMI Reducing clock synthesizer Product Description Features The PCS3P7101A is a low cost, single-output, clock • Generates a 4x low EMI clock at the output synthesizer. The PCS3P7101A generates a 4x output clock • Input frequency: 25 MHz from a 25 MHz standard fundamental mode, inexpensive • Integrated loop filter components. • Frequency deviation: ±0.25% (Typ) center spread device employs Spread Spectrum technique to reduce • Operates with a 3.3V Supply. system electro-magnetic interference (EMI). • Low power CMOS design. • Available in 8-pin SOIC package. • Pin compatible with ICS 341-22 crystal, or clock. It can replace multiple crystals and oscillators, saving valuable board space and cost. The The device also has a power-down feature that tri-state the clock output and turns off the PLL when the PD pin is taken low. Block Diagram VDD PD PLL Modulation XIN/CLKIN XOUT Crystal Oscillator Frequency Divider Feedback Divider Phase Detector Loop Filter VCO Output Divider VSS PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. ModOUT PCS3P7101A September 2006 rev 0.1 Pin Configuration CLKIN/XIN 1 8 XOUT VDD 2 7 PD PCS3P7101A VSS 3 NC 4 Pin Description Pin # Pin Name Type 6 NC 5 ModOUT Description 1 CLKIN/XIN I 2 VDD P Crystal connection or external reference frequency input. This pin has dual functions. It can be connected either to an external crystal or to an external reference clock. Power supply for the entire chip. 3 VSS P Ground connection 4 NC - No Connection 5 ModOUT O Spread spectrum low EMI 4x clock output. 6 NC - 7 PD I 8 XOUT O No Connection Powers down entire chip. Tri-states CLK outputs when low. Has an Internal pull-up resistor. Crystal connection. If using an external reference, this pin must be left unconnected Absolute Maximum Ratings Symbol VDD, VIN TSTG TA Rating Unit Voltage on any pin with respect to Ground Parameter -0.5 to +4.6 V Storage temperature -65 to +125 °C 0 to +70 °C Operating temperature Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 KV TDV Static Discharge Voltage (As per JEDEC STD 22- A114-B) Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Recommended Operating Conditions1 Parameter Supply voltage, VDD Min Typ Max Unit 3.15 3.3 3.45 V Low-level input voltage, VIL VDD = 3.15V to3.45V - - 0.8 V High-level input voltage, VIH VDD = 3.15V to3.45V 2 - - V High-level output current, IOH VDD = 3.15V to3.45V - - 12 mA Low-level output current, IOL VDD = 3.15V to3.45V - - 12 mA 0 - 70 °C Operating free-air temperature, TA Note:1 Unused inputs must be held high or low to prevent them from floating. Low Power Peak EMI Reducing clock synthesizer Notice: The information in this document is subject to change without notice. 2 of 7 PCS3P7101A September 2006 rev 0.1 DC Electrical Characteristics Symbol Parameter Min Typ Max Unit VIL Input low voltage VSS - 0.3 - 0.8 V VIH Input high voltage 2.0 - VDD + 0.5 V IIL Input low current - - -35 µA IIH Input high current - - 35 µA VOL Output low voltage (VDD = 3.3 V, IOL = 12 mA) - - 0.4 V VOH Output high voltage (VDD = 3.3 V, IOH = 12 mA) 2.4 - - V IDD Static supply current* - 50 _ uA ICC Dynamic supply current (3.3V, 25MHz and no load) - TBD - VDD Operating voltage 3.15 3.3 3.45 V ZOUT Output impedance - 20 - Ω Input Capacitance - 4 - pF - 250 - KΩ - 525 - kΩ CIN RPD RPUP Internal pull-up resistor PD CLK output * XIN/CLKIN pin and PD pin are pulled low AC Electrical Characteristics for 3.3V Supply Symbol Min Typ Max Unit Input frequency - 25 - MHz Output frequency - 100 - MHz tLH* Output rise time (measured from 0.8 to 2.0V) - 1 - nS tHL* Output fall time (measured at 2.0V to 0.8V) - 1 - nS tPU Power-up time( PLL lock time from power-up) - 4 10 mS tON Power-up time (first locked cycle after power-up)** - 4 7 mS Synthesis Error(Output Frequency) - 0 - ppm tJC Jitter (cycle to cycle) - TBD - pS tJP Period Jitter - TBD - pS tD Output duty cycle 40 50 60 % tja Maximum Absolute Jitter - TBD - pS CLKIN/XIN ModOUT Parameter *tLH and tHL are measured into a capacitive load of 15pF ** VDD and XIN/CLKIN input are stable, PD pin is made high from low. Low Power Peak EMI Reducing clock synthesizer Notice: The information in this document is subject to change without notice. 3 of 7 PCS3P7101A September 2006 rev 0.1 Typical Crystal Oscillator Circuit R1 = 510Ω C1 = 27 pF C2 = 27 pF Typical Crystal Specifications Fundamental AT cut parallel resonant crystal Nominal frequency 25MHz Frequency tolerance ± 50 ppm or better at 25°C Operating temperature range -25°C to +85°C Storage temperature -40°C to +85°C Load capacitance 18pF Shunt capacitance 7pF maximum ESR 25Ω Low Power Peak EMI Reducing clock synthesizer Notice: The information in this document is subject to change without notice. 4 of 7 PCS3P7101A September 2006 rev 0.1 Package Information 8-Pin SOIC Package H E D A2 A C A1 D θ e L B Dimensions Symbol Millimeters Inches Min Max Min Max A1 0.004 0.010 0.10 0.25 A 0.053 0.069 1.35 1.75 A2 0.049 0.059 1.25 1.50 B 0.012 0.020 0.31 0.51 C 0.007 0.010 0.18 0.25 D 0.193 BSC 4.90 BSC E 0.154 BSC 3.91 BSC e 0.050 BSC 1.27 BSC H 0.236 BSC 6.00 BSC L 0.016 0.050 0.41 1.27 θ 0° 8° 0° 8° Low Power Peak EMI Reducing clock synthesizer Notice: The information in this document is subject to change without notice. 5 of 7 PCS3P7101A September 2006 rev 0.1 Ordering Information Part Number Marking Package Type Temperature PCS3P7101AG-08SR 3P7101AG 8-Pin SOIC, TAPE & REEL, Green Commercial PCS3P7101AG-08ST 3P7101AG 8-Pin SOIC, TUBE, Green Commercial Device Ordering Information P C S 3 P 7 1 0 1 A G - 0 8 S R R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent Nos 5,488,627 and 5,631,920. Low Power Peak EMI Reducing clock synthesizer Notice: The information in this document is subject to change without notice. 6 of 7 PCS3P7101A September 2006 rev 0.1 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Part Number: PCS3P7101A Document Version: v0.1 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. Low Power Peak EMI Reducing clock synthesizer Notice: The information in this document is subject to change without notice. 7 of 7