TI SNJ54ABTH32316HT

SN54ABTH32316, SN74ABTH32316
16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS179E – JUNE 1992 – REVISED MAY 1997
D
D
D
D
D
D
Members of the Texas Instruments
Widebus+ Family
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
UBE  (Universal Bus Exchanger)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D
D
D
D
D
High-Impedance State During Power Up
and Power Down
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include 80-Pin Plastic
Thin Quad Flat (PN) Package With
12 × 12-mm Body Using 0.5-mm Lead Pitch
and 84-Pin Ceramic Quad Flat (HT) Package
C11
C10
C9
A1
SELA
OEA
OEC
SELC
LEC
CLKC
CLKENC
NC
VCC
GND
C16
C15
C14
C13
C12
GND
’ABTH32316 . . . PN PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
A2
A3
A4
GND
A5
A6
A7
A8
A9
VCC
GND
A10
A11
A12
A13
A14
GND
A15
A16
NC
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
41
20
C8
C7
C6
GND
C5
C4
C3
C2
C1
VCC
GND
B16
B15
B14
B13
B12
GND
B11
B10
B9
CLKENA
CLKA
LEA
OEB
SELB
LEB
CLKB
CLKENB
NC
VCC
GND
B1
B2
B3
B4
B5
GND
B6
B7
B8
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, EPIC-ΙΙB, and UBE are trademarks of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN54ABTH32316, SN74ABTH32316
16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS179E – JUNE 1992 – REVISED MAY 1997
GND
C11
C10
C9
A1
SELA
OEA
OEC
SELC
LEC
CLKC
CLKENC
NC
VCC
NC
GND
C16
C15
C14
C13
C12
SN54ABTH32316 . . . HT PACKAGE
(TOP VIEW)
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
A2
A3
A4
GND
A5
A6
A7
A8
A9
VCC
NC
GND
A10
A11
A12
A13
A14
GND
A15
A16
NC
1
63
2
62
3
61
4
60
5
59
6
58
7
57
8
56
9
55
10
54
11
53
12
52
13
51
14
50
15
49
16
48
17
47
18
46
19
45
20
44
21
43
C8
C7
C6
GND
C5
C4
C3
C2
C1
VCC
NC
GND
B16
B15
B14
B13
B12
GND
B11
B10
B9
B8
CLKENA
CLKA
LEA
OEB
SELB
LEB
CLKB
CLKENB
NC
VCC
NC
GND
B1
B2
B3
B4
B5
GND
B6
B7
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
NC – No internal connection
description
The ’ABTH32316 consist of three 16-bit registered input/output (I/O) ports. These registers combine D-type
latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be
exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations
of real-time and stored data can be exchanged among the three ports.
Data flow in each direction is controlled by the output-enable (OEA, OEB, and OEC), select-control (SELA,
SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock (CLKA, CLKB, and CLKC) inputs. The A data
register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLKA is held
at a high or low logic level. If LEA and clock-enable A (CLKENA) are low, data is stored on the low-to-high
transition of CLKA. Output data selection is accomplished by the select-control pins. All three ports have
active-low output enables, so when the output-enable input is low, the outputs are active; when the
output-enable input is high, the outputs are in the high-impedance state.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
2
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SN54ABTH32316, SN74ABTH32316
16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS179E – JUNE 1992 – REVISED MAY 1997
description (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH32316 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH32316 is characterized for operation from –40°C to 85°C.
Function Tables
STORAGE†
INPUTS
OUTPUT
CLKENA
CLKA
LEA
A
H
X
L
X
L
↑
L
L
L
L
↑
L
H
H
X
H
L
X
Q0‡
X
L
L
X
Q0‡
Q0‡
X
X
H
L
L
X
X
H
H
H
† A-port register shown. B and C ports are similar
but use CLKENB, CLKENC, CLKB, CLKC, LEB,
and LEC.
‡ Output level before the indicated steady-state
input conditions were established
A-PORT OUTPUT
INPUTS
OEA
OUTPUT A
SELA
H
X
Z
L
H
Output of C register
L
L
Output of B register
B-PORT OUTPUT
INPUTS
OEB
OUTPUT B
SELB
H
X
Z
L
H
Output of A register
L
L
Output of C register
C-PORT OUTPUT
INPUTS
OUTPUT C
OEC
SELC
H
X
L
H
Output of B register
L
L
Output of A register
Z
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3
SN54ABTH32316, SN74ABTH32316
16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS179E – JUNE 1992 – REVISED MAY 1997
logic diagram (positive logic)
OEC
SELC
CLKC
CLKENC
LEC
C1
OEB
SELB
CLKB
CLKENB
LEB
B1
OEA
SELA
CLKA
CLKENA
LEA
A1
77
76
74
CLK
73
C
75
CE
52
24
25
27
CLK
28
C
26
CE
32
78
79
22
CLK
21
C
23
CE
80
1 of 16 Channels
Pin numbers shown are for the PN package.
4
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SN54ABTH32316, SN74ABTH32316
16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS179E – JUNE 1992 – REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABTH32316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABTH32316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): PN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH32316
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
–55
High-level input voltage
SN74ABTH32316
MIN
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
VCC
–24
V
V
0.8
0
UNIT
VCC
–32
V
V
mA
48
64
mA
10
10
ns/V
µs/V
200
125
–40
85
°C
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
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SN54ABTH32316, SN74ABTH32316
16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS179E – JUNE 1992 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
II = –18 mA
IOH = –3 mA
VCC = 5 V,
IOH = –3 mA
IOH = –24 mA
–1.2
II(hold)
I(h ld)
3
3
A, B, or C ports
VCC = 0 to 5.5 V,
VCC = 2.1 V to 5.5 V,
VI = VCC or GND
VI = VCC or GND
A B
A,
B, or C ports
VCC = 4
4.5
5V
VI = 0.8 V
VI = 2 V
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X
Ioff
ICEX
IO§
VCC = 0,
VCC = 5.5 V, VO = 5.5 V
VI or VO ≤ 4.5 V
Outputs high
VCC = 5.5 V,
VO = 2.5 V
Outputs high
ICC
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
∆ICC¶
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
Control inputs
V
2
0.55
0.55
100
Control inputs
UNIT
V
2
IOL = 64 mA
IOZPU‡
IOZPD‡
Ci
–1.2
2.5
Vhys
II
MIN
2.5
IOH = –32 mA
IOL = 48 mA
VCC = 4
4.5
5V
SN74ABTH32316
TYP†
MAX
MIN
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4
4.5
5V
VOL
SN54ABTH32316
TYP†
MAX
TEST CONDITIONS
100
±1
±1
±20
100
–100
–100
–100
Outputs disabled
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
±50
µA
±50
±50
µA
±100
±100
µA
50
50
µA
–180
mA
–180
Outputs low
µA
µA
±50
–50
mV
±100
100
V
–50
–100
2
2
40
40
1
1
1
0.5
3
mA
mA
3
pF
Cio
A, B, or C ports
11.5
11.5
† All typical values are at VCC = 5 V, TA = 25°C.
‡ This parameter is specified by characterization.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABTH32316
fclock
Clock frequency
tw
Pulse duration
tsu
th
6
Setup time
Hold time
SN74ABTH32316
MIN
MAX
MIN
MAX
0
150
0
150
LE high
3.3
3.3
CLK high or low
3.3
3.3
A, B, or C before CLK↑
2.6
2.4
A or B before LE↓
2.5
2.1
CLKEN before CLK↑
3.5
3.2
A, B, or C after CLK↑
1.8
1.4
A or B after LE↓
2.4
2.1
CLKEN after CLK↑
1.5
1.1
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UNIT
MHz
ns
ns
ns
SN54ABTH32316, SN74ABTH32316
16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS179E – JUNE 1992 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
SN54ABTH32316
MIN
MAX
150
A B
A,
B, or C
C B
C,
B, or A
SEL
A B
A,
B, or C
LE
A B
A,
B, or C
CLK
A B
A,
B, or C
OE
A B
A,
B, or C
OE
A B
A,
B, or C
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SN74ABTH32316
MIN
MAX
150
UNIT
MHz
0.8
6.5
1.4
6.1
0.5
6.8
1.1
6.6
0.8
6.7
1.4
6.5
0.8
6.8
1.8
6.5
1.5
8
2.6
7.5
1.5
7.4
2.6
6.9
1.5
8
2.5
7.5
1.5
7.2
2.5
6.7
0.8
6.7
1.5
6.4
1.5
7.1
2.4
6.8
0.8
7.2
1.5
6
0.8
6.4
1.9
6.1
ns
ns
ns
ns
ns
ns
7
SN54ABTH32316, SN74ABTH32316
16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS179E – JUNE 1992 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
1.5 V
Input
1.5 V
0V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
Output
3V
Output
Control
tPHL
tPLH
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-9680801QXA
ACTIVE
CFP
HT
84
1
TBD
SN74ABTH32316PN
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
POST-PLATE N / A for Pkg Type
CU NIPDAU
Level-3-260C-168 HR
SN74ABTH32316PNG4
ACTIVE
LQFP
PN
80
119
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SNJ54ABTH32316HT
ACTIVE
CFP
HT
84
1
TBD
POST-PLATE N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP015 – OCTOBER 1994
HT (S-CQFP-F84)
CERAMIC QUAD FLATPACK
1.465 (37,21)
SQ
1.420 (36,07)
0.665 (16,89)
SQ
0.635 (16,13)
84
64
63
1
0.500 (12,70) TYP
21
43
0.105 (2,67) MAX
22
42
84
(0,305)
0.012
0.006 (0,152)
0.018 (0,46) MAX
0.025 (0,64)
0.014 (0,36)
0.008 (0,20)
0.004 (0,10)
0.002 (0,05)
At Braze Pads
0.130 (3,30) MAX
4040169-2 / B 03/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package is hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MO -090 AA
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1
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
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