SCES490B − SEPTEMBER 2003 − REVISED MAY 2004 D Qualification in Accordance With D D D D D D D D OR PW PACKAGE (TOP VIEW) AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Operates From 1.65 V to 3.6 V Max tpd of 3 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per JESD 17 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y † Contact factory for details. Q100 qualification data available on request. description/ordering informatiom The SN74ALVC00 quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation. The device performs the Boolean function Y = A • B or Y = A + B in positive logic. ORDERING INFORMATION −40°C to 85°C ORDERABLE PART NUMBER PACKAGE‡ TA TOP-SIDE MARKING SOIC − D Tape and reel SN74ALVC00IDRQ1 ALVC00I TSSOP − PW Tape and reel SN74ALVC00IPWRQ1 VA00I ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H L L X H X L H logic diagram, each gate (positive logic) A Y B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !"# $"%&! '#( '"! ! $#!! $# )# # #* "# '' +,( '"! $!#- '# #!#&, !&"'# #- && $##( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES490B − SEPTEMBER 2003 − REVISED MAY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO IOH IOL ∆t/∆v MIN MAX 1.65 3.6 Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V High-level output current VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.7 V VCC = 3 V Input transition rise or fall rate V 0.65 × VCC 1.7 V 2 0.35 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V Low-level input voltage UNIT 0.7 V 0.8 0 3.6 V 0 VCC −4 V −12 −12 mA −24 4 12 12 mA 24 5 ns/V TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES490B − SEPTEMBER 2003 − REVISED MAY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −100 µA IOH = −4 mA MIN 1.65 V to 3.6 V VCC−0.2 1.2 1.65 V IOH = −6 mA VOH IOH = −12 mA IOH = −24 mA IOL = 100 µA IO = 0 Other inputs at VCC or GND ∆ICC Ci VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. 1.7 2.7 V 2.2 3V 2.4 3V 2 UNIT V 1.65 V 0.45 2.3 V 0.4 2.3 V 0.7 IOL = 24 mA VI = VCC or GND VI = VCC or GND, One input at VCC − 0.6 V, 2 2.3 V 0.2 IOL = 12 mA II ICC 2.3 V MAX 1.65 V to 3.6 V IOL = 4 mA IOL = 6 mA VOL TYP† VCC 2.7 V 0.4 3V 0.55 V 3.6 V ±5 µA 3.6 V 10 µA 3 V to 3.6 V 750 µA 3.3 V 4.5 pF switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX 1 4.4 1 2.8 VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V MAX MIN MAX 3.2 0.5 3 UNIT ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate CL = 0, POST OFFICE BOX 655303 VCC = 1.8 V TYP f = 10 MHz • DALLAS, TEXAS 75265 20 VCC = 2.5 V TYP 21 VCC = 3.3 V TYP 23 UNIT pF 3 SCES490B − SEPTEMBER 2003 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test VLOAD Open S1 GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V ± 0.15 V 2.5 ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V tw VI Timing Input VM VM VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VM VM 0V tPLH Output Control (low-level enabling) VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLZ VLOAD/2 VM tPZH tPHL VOH VM VI VM tPZL VI Input VOLTAGE WAVEFORMS PULSE DURATION th VI Data Input VM 0V 0V tsu Output VI VM Input VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VOH VM VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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