TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 FS PACKAGE (TOP VIEW) description The TMS3471C is a monolithic integrated circuit designed to supply timing signals for the Texas Instruments (TI) 11-mm diagonal TC241 monochrome CCD image sensor. The TMS3471C supplies both CCD drive signals and NTSC television synchronization signals at standard video rates. It requires a single 5-V supply voltage and a 14.318-MHz crystal-oscillator input. The TMS3471C provides several options, including multiple antiblooming modes, clamp-pulse selection, and delayed horizontal transfer. BCP1 FI E/L VDS BCPS1 BCPS0 GT3 GT2 GT1 X2 X1 NTSC-Timing Operation Solid-State Reliability Monochrome Operation Eight Selectable-Antiblooming Modes Surface-Mount Package Clamp-Pulse Select Option 44 43 42 41 40 39 38 37 36 35 34 BCP2 CP2 CP1 CSYNC CBLK BF SC SC(90) ABS0 ABS1 ABS2 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 23 11 GND SH1 SH2,3 PI ABIN GT PS PD S2,3 S1 T 12 13 14 15 16 17 18 19 20 21 22 HIGH I/N SB GP VD WHTA WHTB VGATE HGATE CLK2M V CC • • • • • • The TMS3471C is used in conjunction with level-shifting devices such as the TI TMS3473B parallel driver and the TI TMS3472A serial driver. It also supplies sample-and-hold signals for the TI TL1593 three-channel sample-and-hold and multiplex signals for the TI TL1051 video preprocessor. The TMS3471C NTSC synchronization-signal outputs include composite sync, composite blank, clamp, subcarrier, subcarrier delayed by 90 degrees, and burst flag. The TMS3471C is supplied in a 44-pin plastic flat package and is characterized for operation from – 20°C to 45°C. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. TI is a trademark of Texas Instruments Incorporated. Copyright 1991, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 functional block diagram 14.318 MHz 34 X1 35 X2 CLK2M 21 Oscillator Divide by 7 Divide by 4 3.58 MHz 2.045 MHz 7 8 SC SC(90) Horizontal Counter Vertical Counter PD GT PS PI T VDS I/N GP 26 28 27 30 23 41 13 15 29 ABIN 11 ABS2 10 ABS1 ABS0 9 SB 2 Decoder Clock Generator Antiblooming Generator Serial/ Sample-and -Hold Generator 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 18 16 20 19 5 4 3 2 44 1 6 43 39 40 24 25 32 31 36 37 38 42 WHTA WHTB VD HGATE VGATE CBLK CSYNC CP1 CP2 BCP1 BCP2 BF FI BCPS0 BCPS1 S1 S2,3 SH1 SH2,3 GT1 GT2 GT3 E/L TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION ABIN 29 O Antiblooming in. ABIN drives the ABG input of the TC240/TC241 CCD image sensors. ABS0 9 I ABS1 10 I ABS2 11 I BCP1 44 O Optical black clamp pulse 1 BCP2 1 O Optical black clamp pulse 2 BCPS0 39 I BCPS1 40 I The levels on BCPS0 and BCPS1 determine the placement and duration of the BCP1 and BCP2 pulses relative to the horizontal scan timing (see Figure 4 for the truth table for BCPS0 and BCPS1 and for the corresponding BCP1 and BCP2 pulse placements). BF 6 O Burst flag CBLK 5 O Composite blank CLK2M 21 O 2-MHz clock CP1 3 O Clamp CP2 2 O Clamp CSYNC 4 O Composite sync E/L 42 I Delay select for S1 and S2,3. When E/L is high, the two serial-transfer pulses occur early relative to the sample-and-hold pulses SH1 and SH2,3. When E/L is low, the two serial-transfer pulses occur late relative to the sample-and-hold pulses. FI 43 O Field index GND 33 GP 15 I Exposure control: GP gates PS and PI GT 28 O TMS3473B parallel-driver MIDSEL input switch GT1 36 O Y gate 1 GT2 37 O Y gate 2 GT3 38 O Y gate 3 HGATE 20 O Decoded H count signal. HGATE is a test point and is not used in normal operation. HIGH 12 I Not used (tie high) I/N 13 I Interlace select. If high, interlace mode is selected; if low, noninterlace mode is selected. PD 26 O Power down. A low-logic level on PD causes the device to enter a low power-consumption mode. PI 30 O Parallel-image-area gate clock PS 27 O Parallel-storage-area gate clock SB 14 I Standby-mode select. When SB is high, normal operation is selected; when SB is low, the power-down mode is selected. SC 7 O Subcarrier (3.58 MHz) SC(90) 8 O Subcarrier phase shifted by 90 degrees SH1 32 O Sample-and-hold pulse 1 SH2,3 31 O Sample-and-hold pulse 2, 3 The levels on these three terminals determine which of the eight antiblooming modes is selected: MODE ABS2 ABS1 ABS0 Operation 0 L L L No ABG pulses 1 L L H 250-kHz clocking during flyback only 2 L H L 1-MHz clocking during flyback only 3 L H H 2.2-MHz clocking during flyback only 4 H L L 250-kHz continuous clocking 5 H L H 500-kHz continuous clocking 6 H H L 1-MHz continuous clocking 7 H H H 2.2-MHz continuous clocking Ground POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION S1 24 O Serial clock 1 S2,3 25 O Serial clock 2, 3 T 23 O Transfer-gate clock VCC VD 22 16 O Vertical drive VDS 41 I Vertical-dump speed. When VDS is high, the vertical-dump frequency is 2 MHz; when VDS is low, the vertical-dump frequency is 1 MHz. VDS can also function as a timer reset by dropping the voltage on VDS from VCC to VCC/2 and then raising it back to VCC. VGATE 19 O Decoded V count signal. VGATE is a test point and is not used in normal operation. WHTA 17 O WHTA is a test point and is not used in normal operation. WHTB 18 O WHTB is a test point and is not used in normal operation. X1 34 X2 35 DC power Crystal oscillator (see Figure 1) TMS3471C X1 X2 34 35 C1 ≈ 40 pF C2 ≈ 40 pF NOTE: The TMS3471C is designed for use with a crystal oscillator. The X1 and X2 terminals should not connect directly to external driver outputs. Figure 1. Connection of an External Crystal Oscillator to the TMS3471C 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Continuous total power dissipation: TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 mW TA = 45°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 mW TA = 75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 mW Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20°C to 45°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 3 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. recommended operating conditions MIN Supply voltage, VCC 4.5 NOM 5 MAX 5.5 High-level input voltage, VIH UNIT V V Low-level input voltage, VIL 0.8 Operating frequency 14.31818 Power-up time µs 300 Operating free-air temperature, TA – 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V MHz 45 °C 5 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature, VCC = 5 V (unless otherwise noted)† PARAMETER VOH VOL TEST CONDITIONS IOH < 1 µA IOL < 1 µA High-level output voltage Low-level output voltage IIH‡ High level input current High-level VCC = 5 V VCC = 4.5 V IIL Low level input current Low-level VCC = 5.5 V VCC = 5 V High-level output current TYP 0.05 75 225 200 S2,3, PD – 0.2 SH1, GT1, GT2, GT3 – 2.5 –1 – 0.6 – 0.3 All other outputs VOH = 4.6 V – 0.5 S1, T, ABIN, PS, PI, GT 0.1 S2,3, PD 0.2 SH1, GT1, GT2, GT3 2.5 SH2,3 5 BCP1, BCP2 VOL = 0.4 V 1 SC, SC(90) 0.3 CP2 0.6 CLK2M 0.3 All other outputs mA 0.5 Average supply current 40 mA Standby supply current 15 mA † The SB input is a Schmitt-trigger input with 0.5-V to 1-V hysteresis. ‡ All inputs have pullup-current sources. 6 mA –3 CLK2M ICC(AV) ICC(S) µA –5 5V VOH = 3 3.5 CP2 Low-level output current V µA 65 – 0.1 BCP1, BCP2 UNIT V SC, SC(90) IOL MAX S1, T, ABIN, PS, PI, GT SH2,3 IOH MIN 4.95 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 switching characteristics over recommended operating free-air temperature range, VCC = 5 V PARAMETER TEST CONDITIONS 10 S2,3 CL = 40 pF 10 CL = 40 pF 10 BCP1, BCP2 CL = 50 pF 100 SC, SC(90) CL = 15 pF 30 CL = 20 pF 8 S2,3 CL = 40 pF 8 Fall time 30 CL = 20 pF GT1, GT2, GT3, SH1 tf 200 S1 ABIN, GT, PD, PI, PS, T 8 SH2,3 CL = 40 pF 8 BCP1, BCP2 CL = 50 pF 100 SC, SC(90) CL = 15 pF 30 CLK2M 100 ±5 S1 rising edge to S2,3 rising edge tsk(o) k( ) tw – tc /2 Skew time Pulse duration compared to pulse duration at 50% duty cycle† ns 50 CL = 50 pF All other outputs ns 50 CL = 50 pF All other outputs UNIT 10 SH2,3 CLK2M MAX 30 CL = 20 pF GT1, GT2, GT3, SH1 Rise time TYP CL = 20 pF ABIN, GT, PD, PI, PS, T tr MIN S1 S1 falling edge to SH1 falling edge –3 –8 –13 S1 rising edge to GT1 falling edge –3 –8 –13 ±5 SH2,3 rising edge to GT1 rising edge S2,3 falling edge to SH2,3 falling edge –3 –8 –13 S2,3 falling edge to GT2 rising edge –3 –8 –13 SH2,3 falling edge to GT2 rising edge ±5 SH2,3 rising edge to GT3 falling edge ±5 S1 or S2, 3 ±5 ns ns † The S1 and S2,3 outputs ideally exhibit a 50% duty cycle. This parameter indicates how much the duty cycle may shift while a constant cycle time is maintained. For example, for a 210-ns cycle time, tw(H) = 110 ns and tw(L) = 100 ns are possible. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 PARAMETER MEASUREMENT INFORMATION 1 Line = 63.55 µs (525) Vertical Scale† 521 523 0 5 0 10 15 20 25 30 256 260 6 265 262.5 VD 270 6H Odd Field, 262.5 H Even Field 10H 524 280 268.5 6H 0 FI 275 10H 262 9 272 CP1 0 20 CP2 VS 3H VS 3H EQ 3H EQ 3H EQ 3H EQ 3H CSYNC 20H 20H CBLK 10H 10H BF BCP1 BCP2 SC,SC(90) Continuous 0 S1 0 S2,3 0 9 0 9 0 9 GT1 GT2 GT3 SH1 4.77273 MHz SH2,3 244 Pulses‡ PI 244 Pulses‡ GT ABIN PS,T 524 244 Pulses‡ 17 262 244 Pulses‡ 279 † 525 intervals equal 33.3 ms equals 1 TV frame ‡ The frequency of these pulses is either 2.04545 MHz or 1.02273 MHz and is determined by the logic level on the VDS input. Figure 2. Vertical Timing 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 288 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 Horizontal Scale† 95 120 125 (130) 0 5 10 15 3 20 25 30 56 60 65 70 75 13 CP1 0 20.5 CP2 3 13 CSYNC 22 0 CBLK 14 20 BF BCP1 BCP2 HGATE PI 13 PS 1 3 5 7 9 11 T S1 S2, 3 SH1 SH2, 3 GT1 GT2 GT3 OUT1 1/2 Active Output From CCD Image Sensor OUT2 1/2 Active OUT3 Dummy Dark 6X3 8 X 3 –1 Active 252 X 3 – 2 = 754 † 130 intervals equal 63.55 µs equals one horizontal-scan line Figure 3. Horizontal Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 850 870 (910) 0 890 20 40 60 80 100 120 140 160 180 200 220 † 122 124 126 (130) 0 2 128 4 6 8 10 12 14 16 18 20 22 24 26 28 30 ‡ CBLK MODE 0 BCP1 126 133 MODE 1 MODE 2 119 140 MODE 3 122.5 136.5 MODE 0 BCP2 129.5 MODE 1 143.5 MODE 2 MODE 3 MODE 0 MODE 1 ABIN MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7 † 910 intervals equal 63.55 µs equals one horizontal-scan line ‡ 130 intervals equal 63.55 µs equals one horizontal-scan line MODE 0 1 2 3 MODE 0 1 2 3 4 5 6 7 BCPS1 L L H H ABS2 L L L L H H H H BCPS0 L H L H ABS1 L L H H L L H H ABS0 L H L H L H L H Figure 4. ABIN, BCP1, BCP2 Timing at the Start of H 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 Vertical-Dump Frequency (2.04545 MHz or 1.02273 MHz) (see Note A) 1 2 243 244 1 2 243 244 GP T PS PI GT ABIN Even Field tr ≤ 2H DPI Odd Field (see Note B) DAB NOTES: A. When the vertical-dump frequency is 1.02273 MHz, PI, PS, and T have a 50% duty cycle. B. If I/N is low, the DPI waveform is always as shown for the odd-field case. Figure 5. PI, PS, T, and ABIN Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 Horizontal Scale† 83 96 100 125 (130) 0 5 10 15 20 25 52 55 60 65 65 CP1 3 123 13 VS 3 8 EQ 13 CSYNC 0 22 CBLK 14 20 BF 0 20.5 CP2 17 20 BCP1 17.5 20.5 BCP2 0 SH1, SH2,3 1 3 5 7 9 11 T PI 11 13 PS 0 14 S1, S2,3 97 3 HGATE 20.5 100 20.5 WHTA 83 20.5 WHTB Vertical Scale‡ 125 128 130 175 178 192 195 260 262 WHTA WHTB 262.5 VD 258.5 VGATE † 130 intervals equal 63.55 µs equals one horizontal-scan line ‡ 525 intervals equal 33.33 ms equals one TV frame Figure 6. H Timing and WHTA, WHTB (V,H) Timing 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 Power-Up Operation Power SB (see Note A) PD GP VD (see Note B) Refresh Pulses (see Note C) 256 Pulses 0.5 H PI PS, T 244 Pulses 244 256 S1, S2,3 GT ABIN Standby Operation See Note D SB GP VD (see Note B) Refresh Pulses (see Note C) 0.5 H PI PS, T 6.5 H 256 Pulses 244 Pulses 256 244 S1, S2,3 GT ABIN PD NOTES: A. B. C. D. A 0.1-µF capacitor is connected between SB and GND. The VD output is fed back to GP. The 256 CCD refresh pulses are generated on PI, PS, and T even if VD is not fed back to GP. When SB is low, PI, PS, T, S1, S2,3, GT, and PD are all low and ABIN is high. Figure 7. Power-Up and Standby Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 When VD is High 0 5 10 15 20 SB VCC VDS 1/2 VCC 0.5 H GND VD 1 field 256 Pulses PI PS ABIN S1, S2,3 GT PD When VD is Low 0 5 10 15 20 VCC VDS 1/2 VCC GND 6H VD 0.5 H 244 Pulses PI PS ABIN S1, S2,3 GT PD Figure 8. Timing for VDS in the Reset Mode 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 30 35 25 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 VD GP 6.5H PI 244 Pulses (see Note A) 0.5H 256 Pulses (see Note B) PS, T GT ABIN BCP1, BCP2 (operation mode) Normal Operation Clear Operation NOTES: A. When VD is low and GP goes low, 244 pulses are generated on PI, PS, and T. B. If VD is high and not fed back to GP, then pulsing GP results in 256 pulses being generated on PI, PS, and T. This can be useful in clearing the imager. An external logic circuit is used to pulse GP. Figure 9. GP Timing for Normal and Clear Modes POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 0 5 10 15 20 25 260 262 265 270 275 280 285 Vertical Scale† VCC DPI (interlace) Vmid VSS DPI (noninterlace) VCC VSS VCC DPS VSS VCC DS1, 2, 3 VSS VABG+ DAB ABmid VABG – 0 4 11 15 Horizontal Scale ‡ VABG– DAB (mode 0) VABG+ DAB (mode 1– mode 3) VABG – VABG+ DAB (mode 4 – mode 7) VABG – † 525 intervals equal 33.33 ms equals one TV frame ‡ 130 intervals equal 63.55 µs equals one horizontal-scan line Figure 10. DPI, DPS, DS, and DAB Drive Timing 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 20 22 25 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 100 105 110 † S1 E/L: H S2,3 S1 E/L: L S2,3 8 ± 5 ns 8 ± 5 ns SH1 8 ± 5 ns 8 ± 5 ns SH2,3 ± 5 ns GT1 ± 5 ns GT2 ± 5 ns ± 5 ns GT3 Acceptable † Each interval equals one master clock interval equals 69.84 ns. Figure 11. S1, S2,3, SH1, SH2,3, and GTn Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TMS3471C 2/3-INCH NTSC TIMER SOCS028B – AUGUST 1991 MECHANICAL DATA FS/S-PQFP-G44 PLASTIC QUAD FLATPACK 33 23 34 22 1,00 TYP 44 12 1 0,55 MAX 0,20 0,10 11 14,20 MAX SQ 2,20 MAX 18,20 SQ 17,40 0,10 MIN Seating Plane 2,30 MAX 0°– 10° 1,50 1,10 0,10 4040160/A–10/93 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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