SST SST39VF3201C

32 Mbit (x16) Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
The SST39VF3201C and SST39VF3202C devices are 2M x16, CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST's proprietary, high performance
CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate
approaches. The SST39VF3201C and SST39VF3202C write (Program or Erase)
with a 2.7-3.6V power supply. This device conforms to JEDEC standard pinouts
for x16 memories.
Features
• Organized as 2M x16
• Security-ID Feature
– SST: 128 bits; User: 128 words
• Single Voltage Read and Write Operations
• Fast Read Access Time:
– 2.7-3.6V
– 70 ns
• Superior Reliability
• Latched Address and Data
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 6 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Uniform 2 KWord sectors
• Block-Erase Capability
– Flexible block architecture
– Eight 4-KWord blocks, 63 32-KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
©2011 Silicon Storage Technology, Inc.
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 35 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Top Block-Protection (top two 4-KWord blocks)
for SST39VF3202C
– Bottom Block-Protection (bottom two 4-KWord blocks)
for SST39VF3201C
• Sector-Erase Capability
• Fast Erase and Word-Program:
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
– RY/BY# Pin
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pin Assignments
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
• All devices are RoHS compliant
www.microchip.com
DS25020A
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Product Description
The SST39VF3201C and SST39VF3202C devices are 2M x16 CMOS Multi-Purpose Flash Plus
(MPF+) manufactured with SST’s proprietary, high-performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39VF3201C/3202C write (Program or Erase) with a 2.73.6V power supply. These devices conform to JEDEC standard pin assignments for x16 memories.
Featuring high performance Word-Program, the SST39VF3201C/3202C devices provide a typical
Word-Program time of 7 µsec. These devices use Toggle Bit, Data# Polling, or RY/BY# pin to indicate
the completion of Program operation. To protect against inadvertent write, they have on-chip hardware
and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data
retention is rated at greater than 100 years.
The SST39VF3201C/3202C devices are suited for applications that require convenient and economical
updating of program, configuration, or data memory. For all system applications, they significantly
improve performance and reliability, while lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for program, data, and configuration storage
applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet high-density, surface mount requirements, the SST39VF3201C/3202C devices are offered in
48-lead TSOP and 48-ball TFBGA packages. See Figure 2 and Figure 3 for pin assignments.
©2011 Silicon Storage Technology, Inc.
DS25020A
2
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Block Diagram
X-Decoder
Memory Address
CE#
OE#
WE#
WP#
RESET#
RY/BY#
SuperFlash
Memory
Address Buffer Latches
Y-Decoder
Control Logic
I/O Buffers and Data Latches
DQ15 - DQ0
1410 B1.0
Figure 1: Functional Block Diagram
©2011 Silicon Storage Technology, Inc.
DS25020A
3
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Pin Assignments
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Standard Pinout
Top View
Die Up
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
1410 48-tsop EK P1.0
Figure 2: Pin Assignments for 48-lead TSOP
TOP VIEW (balls facing down)
6
5
4
3
2
1
A13 A12 A14
A15 A16 NC DQ15 VSS
A8
A10
A11 DQ7 DQ14 DQ13 DQ6
WE# RST#
NC
A19 DQ5 DQ12 VDD DQ4
RY/BY# WP# A18
A20 DQ2 DQ10 DQ11 DQ3
A9
A7
A17
A6
A5
DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# VSS
A B C D E F G H
1410 4-tfbga B1K P2.0
Figure 3: Pin assignments for 48-ball TFBGA
©2011 Silicon Storage Technology, Inc.
DS25020A
4
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Table 1: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
RST#
Reset
To reset and return the device to Read mode.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD
Power Supply
To provide power supply voltage: 2.7-3.6V
VSS
Ground
To protect the top/bottom boot block from Erase/Program operation when
grounded.
NC
No Connection
Unconnected pins.
RY/BY#
Ready/Busy#
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
T1.0 25020
1. AMS = Most significant address
AMS = A20 for SST39VF3201C/3202C
©2011 Silicon Storage Technology, Inc.
DS25020A
5
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Table 2: Top / Bottom Boot Block Address (1 of 2)
Top Boot Block Address SST39VF3202C
#
Size
(KWord)
70
4
1FF000H-1FFFFFH
69
4
1FE000H-1FEFFFH
68
4
1FD000H-1FDFFFH
67
4
1FC000H-1FCFFFH
66
4
65
4
64
63
62
61
60
32
1E0000H-1E7FFFH
59
32
1D8000H-1DFFFFH
58
32
1D0000H-1D7FFFH
57
32
1C8000H-1CFFFFH
56
32
55
32
54
53
Bottom Boot Block Address SST39VF3201C
Size
(KWord)
Address Range
70
32
1F8000H-1FFFFFH
69
32
1F0000H-1F7FFFH
68
32
1E8000H-1EFFFFH
67
32
1E0000H-1E7FFFH
1FB000H-1FBFFFH
66
32
1D8000H-1DFFFFH
1FA000H-1FAFFFH
65
32
1D0000H-1D7FFFH
4
1F9000H-1F9FFFH
64
32
1C8000H-1CFFFFH
4
1F8000H-1F8FFFH
63
32
1C0000H-1C7FFFH
32
1F0000H-1F7FFFH
62
32
1B8000H-1BFFFFH
32
1E8000H-1EFFFFH
61
32
1B0000H-1B7FFFH
60
32
1A8000H-1AFFFFH
59
32
1A0000H-1A7FFFH
58
32
198000H-19FFFFH
57
32
190000H-197FFFH
1C0000H-1C7FFFH
56
32
188000H-18FFFFH
1B8000H-1BFFFFH
55
32
180000H-187FFFH
32
1B0000H-1B7FFFH
54
32
178000H-17FFFFH
32
1A8000H-1AFFFFH
53
32
170000H-177FFFH
52
32
1A0000H-1A7FFFH
52
32
168000H-16FFFFH
51
32
198000H-19FFFFH
51
32
160000H-167FFFH
50
32
190000H-197FFFH
50
32
158000H-15FFFFH
49
32
188000H-18FFFFH
49
32
150000H-157FFFH
48
32
180000H-187FFFH
48
32
148000H-14FFFFH
47
32
178000H-17FFFFH
47
32
140000H-147FFFH
46
32
170000H-177FFFH
46
32
138000H-13FFFFH
45
32
168000H-16FFFFH
45
32
130000H-137FFFH
44
32
160000H-167FFFH
44
32
128000H-12FFFFH
43
32
158000H-15FFFFH
43
32
120000H-127FFFH
42
32
150000H-157FFFH
42
32
118000H-11FFFFH
41
32
148000H-14FFFFH
41
32
110000H-117FFFH
40
32
140000H-147FFFH
40
32
108000H-10FFFFH
39
32
138000H-13FFFFH
39
32
100000H-107FFFH
38
32
130000H-137FFFH
38
32
0F8000H-0FFFFFH
37
32
128000H-12FFFFH
37
32
0F0000H-0F7FFFH
36
32
120000H-127FFFH
36
32
0E8000H-0EFFFFH
35
32
118000H-11FFFFH
35
32
0E0000H-0E7FFFH
34
32
110000H-117FFFH
34
32
0D8000H-0DFFFFH
33
32
108000H-10FFFFH
33
32
0D0000H-0D7FFFH
32
32
100000H-107FFFH
32
32
0C8000H-0CFFFFH
31
32
0F8000H-0FFFFFH
31
32
0C0000H-0C7FFFH
Address Range
©2011 Silicon Storage Technology, Inc.
#
DS25020A
6
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Table 2: Top / Bottom Boot Block Address (Continued) (2 of 2)
30
32
0F0000H-0F7FFFH
30
32
0B8000H-0BFFFFH
29
32
0E8000H-0EFFFFH
29
32
0B0000H-0B7FFFH
28
32
0E0000H-0E7FFFH
28
32
0A8000H-0AFFFFH
27
32
0D8000H-0DFFFFH
27
32
0A0000H-0A7FFFH
26
32
0D0000H-0D7FFFH
26
32
098000H-09FFFFH
25
32
0C8000H-0CFFFFH
25
32
090000H-097FFFH
24
32
0C0000H-0C7FFFH
24
32
088000H-08FFFFH
23
32
0B8000H-0BFFFFH
23
32
080000H-087FFFH
22
32
0B0000H-0B7FFFH
22
32
078000H-07FFFFH
21
32
0A8000H-0AFFFFH
21
32
070000H-077FFFH
20
32
0A0000H-0A7FFFH
20
32
068000H-06FFFFH
19
32
098000H-09FFFFH
19
32
060000H-067FFFH
18
32
090000H-097FFFH
18
32
058000H-05FFFFH
17
32
088000H-08FFFFH
17
32
050000H-057FFFH
16
32
080000H-087FFFH
16
32
048000H-04FFFFH
15
32
078000H-07FFFFH
15
32
040000H-047FFFH
14
32
070000H-077FFFH
14
32
038000H-03FFFFH
13
32
068000H-06FFFFH
13
32
030000H-037FFFH
12
32
060000H-067FFFH
12
32
028000H-02FFFFH
11
32
058000H-05FFFFH
11
32
020000H-027FFFH
10
32
050000H-057FFFH
10
32
018000H-01FFFFH
9
32
048000H-04FFFFH
9
32
010000H-017FFFH
8
32
040000H-047FFFH
8
32
008000H-00FFFFH
7
32
038000H-03FFFFH
7
4
007000H-007FFFH
6
32
030000H-037FFFH
6
4
006000H-006FFFH
5
32
028000H-02FFFFH
5
4
005000H-005FFFH
4
32
020000H-027FFFH
4
4
004000H-004FFFH
3
32
018000H-01FFFFH
3
4
003000H-003FFFH
2
32
010000H-017FFFH
2
4
002000H-002FFFH
1
32
008000H-00FFFFH
1
4
001000H-001FFFH
0
32
000000H-007FFFH
0
4
000000H-000FFFH
T2.25020
©2011 Silicon Storage Technology, Inc.
DS25020A
7
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST39VF3201C/3202C also have the Auto Low Power mode which puts the device in a near
standby mode after data has been accessed with a valid Read operation. This reduces the IDD active
read current from typically 9 mA to typically 4 µA. The Auto Low Power mode reduces the typical IDD
active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition used to initiate another Read cycle, with
no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with
CE# held steadily low, until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF3201C/3202C is controlled by CE# and OE#, both have to be low
for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details (Figure 5).
Word-Program Operation
The SST39VF3201C/3202C are programmed on a word-by-word basis. Before programming, the sector
where the word exists must be fully erased. The Program operation is accomplished in three steps.
The first step is the three-byte load sequence for Software Data Protection. The second step is to load
word address and word data. During the Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of
either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation,
once initiated, will be completed within 10 µs. See Figure 6 and Figure 7 for WE# and CE# controlled
Program operation timing diagrams and Figure 21 for flowcharts. During the Program operation, the
only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is
free to perform additional tasks. Any commands issued during the internal Program operation are
ignored. During the command sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF3201C/3202C offer both Sector-Erase and Block-Erase mode. The
sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on
block sizes of 4 and 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The
Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the
falling edge of the sixth WE# pulse, while the command (50H or 30H) is latched on the rising edge of
the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase
operation can be determined using either Data# Polling or Toggle Bit methods. See Figure 11 and Fig-
©2011 Silicon Storage Technology, Inc.
DS25020A
8
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
ure 12 for timing waveforms and Figure 25 for the flowchart. Any commands issued during the Sectoror Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with EraseSuspend command (B0H). The device automatically enters read mode typically within 10 µs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue
Erase Resume command. The operation is executed by issuing one byte command sequence with
Erase Resume command (30H) at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF3201C/3202C provide a Chip-Erase operation, which allows the user to erase the entire
memory array to the “1” state. This is useful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is
Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 10 for timing diagram, and
Figure 25 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When
WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39VF3201C/3202C provide two software means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two
status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled
after the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
©2011 Silicon Storage Technology, Inc.
DS25020A
9
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Data# Polling (DQ7)
When the SST39VF3201C/3202C are in the internal Program operation, any attempt to read DQ7 will
produce the complement of the true data. Once the Program operation is completed, DQ7 will produce
true data. Note that even though DQ7 may have valid data immediately following the completion of an internal
Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in
subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt
to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 8 for Data# Polling timing diagram and Figure 22 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle.
An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check
whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status
bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 9 for Toggle Bit timing diagram and Figure 22 for a flowchart.
Table 3: Write Operation Status
Status
Normal Operation
Erase-Suspend
Mode
DQ7
DQ6
DQ2
RY/BY#
DQ7#
Toggle
No
Toggle
0
Standard Erase
0
Toggle
Toggle
0
Read from Erase-Suspended Sector/Block
1
1
Toggle
1
Read from Non- EraseSuspended Sector/Block
Data
Data
Data
1
Program
DQ7#
Toggle
N/A
0
Standard Program
T3.0 25020
Note: DQ7, DQ6 and DQ2 require a valid address when reading status information.
©2011 Silicon Storage Technology, Inc.
DS25020A
10
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain output, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising
edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.
When RY/BY# is high (Ready), the devices may be read or left in standby mode.
Data Protection
The SST39VF3201C/3202C provide both hardware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Hardware Block Protection
The SST39VF3202C support top hardware block protection, which protects the top two 4-KWord
blocks of the device. The SST39VF3201C support bottom hardware block protection, which protects
the bottom two 4-KWord blocks of the device. The Boot Block address ranges are described in Table 4.
Program and Erase operations are prevented on the two 4-KWord blocks when WP# is low. If WP# is
left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling
Program and Erase operations on that block.
Table 4: Boot Block Address Ranges
Product
Address Range
Bottom Boot Block
SST39VF3201C
000000H-001FFFH
Top Boot Block
SST39VF3202C
1FE000H-1FFFFFH
T4.0 25020
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When
no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST#
is driven high before a valid Read can take place. See Figure 17.
The Erase or Program operation that has been interrupted needs to be re-initiated after the device
resumes normal operation mode to ensure data integrity.
©2011 Silicon Storage Technology, Inc.
DS25020A
11
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Software Data Protection (SDP)
The SST39VF3201C/3202C provide the JEDEC approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the
three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or powerdown. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped
with the Software Data Protection permanently enabled. See Table 7 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode
within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command
sequence.
Common Flash Memory Interface (CFI)
The SST39VF3201C/3202C also contain the CFI information to describe the characteristics of the
device. In order to enter the CFI Query mode, the system must write the three-byte sequence, same as
product ID entry command with 98H (CFI Query command) to address 555H in the last byte sequence.
The system can also enter the CFI Query mode, by using the one-byte sequence with 55H on Address
and 98H on Data Bus. Once the device enters the CFI Query mode, the system can read CFI data at
the addresses given in Tables 8 through 10. The system must write the CFI Exit command to return to
Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as the SST39VF3201Cand SST39VF3202C, and
the manufacturer as SST. This mode may be accessed through software operations. Users may use
the Software Product Identification operation to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details, see Table 7 for software operation, Figure 13
for the Software ID Entry and Read timing diagram and Figure 23 for the Software ID Entry command
sequence flowchart.
Table 5: Product Identification
Address
Data
0000H
BFH
SST39VF3201C
0001H
235F
SST39VF3202C
0001H
235E
Manufacturer’s ID
Device ID
T5.0 25020
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to
the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program
or Erase operation. See Table 7 for software command codes, Figure 15 for timing waveform, and Figure 23 and Figure 24 for flowcharts.
©2011 Silicon Storage Technology, Inc.
DS25020A
12
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Security ID
The SST39VF3201C/3202C devices offer a 136 word Security ID space. The Secure ID space is
divided into two segments - one factory programmed segment and one user programmed segment.
The first segment is programmed and locked at SST with a random 128-bit number. The 128-word
user segment is left un-programmed for the customer to program as desired.
To program the user segment of the Security ID, the user must use the Security ID Word-Program
command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once
this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables
any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID
command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 7 for more details.
©2011 Silicon Storage Technology, Inc.
DS25020A
13
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Operations
Table 6: Operation Modes Selection
Mode
CE#
OE#
WE#
DQ
Address
Read
VIL
VIL
VIH
DOUT
AIN
Program
VIL
VIH
VIL
DIN
AIN
VIL
X1
Sector or block address,
XXH for Chip-Erase
Erase
VIL
Standby
VIH
X
X
High Z
X
X
VIL
X
High Z/ DOUT
X
X
X
VIH
High Z/ DOUT
X
VIL
VIL
VIH
Write Inhibit
VIH
Product Identification
Software Mode
See Table 7
T6.0 25020
1. X can be VIL or VIH, but no other value.
Table 7: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
Addr1
Addr1
Data2 Addr1 Data2 Addr1
Data2
Data
AAH
Data2
3rd Bus
Write Cycle
4th Bus
Write Cycle
Word-Program
555H
AAH
2AAH
55H
555H
A0H
WA3
Sector-Erase
555H
AAH
2AAH
55H
555H
80H
555H
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
Data2 Addr1 Data2
2AAH
55H
SAX4
4
50H
Block-Erase
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
BAX
30H
Chip-Erase
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
555H
10H
Erase-Suspend
XXXXH
B0H
Erase-Resume
XXXXH
30H
ID5
555H
AAH
2AAH
55H
555H
88H
User Security ID
Word-Program
555H
AAH
2AAH
55H
555H
A5H
WA6
Data
User Security ID
Program Lock-Out
555H
AAH
2AAH
55H
555H
85H
XXH6
0000H
Software ID
Entry7,8
555H
AAH
2AAH
55H
555H
90H
CFI Query Entry
555H
AAH
2AAH
55H
555H
98H
CFI Query Entry
55H
98H
Software ID Exit9,10
/CFI Exit/Sec ID
Exit
555H
AAH
2AAH
55H
555H
F0H
Software ID Exit9,10
/CFI Exit/Sec ID
Exit
XXH
F0H
Query Sec
T7.0 25020
1. Address format A10-A0 (Hex).
Addresses A11- A20 can be VIL or VIH, but no other value, for Command sequence for SST39VF3201C/3202C.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A20 for SST39VF3201C/3202C
©2011 Silicon Storage Technology, Inc.
DS25020A
14
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000008H to 000087H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H to 000087H.
7. The device does not remain in Software Product ID Mode if powered down.
8. For Manufacture ID
With AMS-A0 =0;SST Manufacturer ID = 00BFH is read
For Device ID Device ID can be read either in one cycle (address 01H) or in three cycles (addresses 01H, 0EH and 0FH)
One-cycle method With AMS-A1=0, A0=1; SST39VF3201C/3202C Device ID = 235F/235E is read
Three-cycle method With AMS-A1=0, A0=1; SST39VF3201C/3202C Device ID = 235F/235E is read (cycle 1)
With AMS-A4=0; A3-A1=1; A0=0; SST39VF3201C/3202C Device ID additional info = 1A/1A is read (Note: 1A = 32 Mbit)
(cycle 2)
With AMS-A4=0; A3-A0=1; SST39VF3201C/3202C Device ID additional info = 00/01 is read (00/01 = Bottom/Top Boot)
(cycle 3)
AMS = Most significant address
AMS = A20 for SST39VF3201C/3202C
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1)
using the Sec ID mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are
from 000000H-000007H and 000008H to 000087H.
Table 8: CFI Query Identification String1 for SST39VF3201C/3202C
Address
Data
10H
0051H
11H
0052H
12H
0059H
13H
0002H
14H
0000H
15H
0000H
16H
0000H
17H
0000H
18H
0000H
19H
0000H
1AH
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T8.0 25020
1. Refer to CFI publication 100 for more details.
©2011 Silicon Storage Technology, Inc.
DS25020A
15
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Table 9: System Interface Information for SST39VF3201C/3202C
Address
Data
1BH
0027H
1CH
0036H
Data
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
0000H
VPP min. (00H = no VPP pin)
1EH
0000H
VPP max. (00H = no VPP pin)
1FH
0003H
Typical time out for Word-Program 2N µs (23 = 8 µs)
20H
0000H
Typical time out for min. size buffer program 2N µs (00H = not supported)
21H
0004H
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H
0005H
Typical time out for Chip-Erase 2N ms (25 = 32 ms)
23H
0001H
Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
24H
0000H
Maximum time out for buffer program 2N times typical
25H
0001H
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H
0001H
Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T9.0 25020
Table 10:Device Geometry Information for SST39VF3201C/3202C
Address
Data
Data
27H
0016H
Device size = 2N Bytes (16H = 22; 222 = 4MByte)
28H
0001H
Flash Device Interface description; 0001H = x16-only asynchronous interface
29H
0000H
2AH
0000H
2BH
0000H
2CH
0003H
Number of Erase Sector/Block sizes supported by device
2DH
0007H
Erase Block1 region information.
2EH
0000H
2FH
0020H
30H
0000H
31H
003EH
32H
0000H
33H
0000H
34H
0001H
35H
0000H
36H
0000H
37H
0000H
38H
0000H
39H
0000H
3AH
0000H
3BH
0000H
3CH
0000H
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Erase Block2 region information.
Erase Block3 region information.
Erase Block4 region information.
T10.0 25020
©2011 Silicon Storage Technology, Inc.
DS25020A
16
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
Table 11:Operating Range
Range
Commercial
Industrial
Ambient Temp
VDD
0°C to +70°C
2.7-3.6V
-40°C to +85°C
2.7-3.6V
T11.1 25020
Table 12:AC Conditions of Test1
Input Rise/Fall Time
Output Load
5ns
CL = 30 pF
T12.1 25020
1. See Figures 19 and 20
©2011 Silicon Storage Technology, Inc.
DS25020A
17
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Power Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100
ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware
reset is required. The recommended VDD power-up to RESET# high time should be greater than 100
µs to ensure a proper reset.
TPU-READ 10 0 µs
VDD min
VDD
0V
VIH
RESET#
TRHR 50 ns
CE#
1410 F24.0
Figure 4: Power-Up Diagram
Table 13:DC Operating Characteristics VDD = 2.7-3.6V1
Limits
Symbol Parameter
IDD
Power Supply Current
Max
Units
Read3
Program and Erase
Standby VDD Current
Auto Low Power
15
45
50
50
mA
mA
µA
µA
ILI
ILIW
Input Leakage Current
Input Leakage Current
on WP# pin and RST#
1
10
µA
µA
Test Conditions
Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
CE#=VIL, OE#=WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
CE#=VIHC, VDD=VDD Max
CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
VIN=GND to VDD, VDD=VDD Max
WP#=GND to VDD or RST#=GND to VDD
ILO
VIL
VILC
VIH
VIHC
VOL
VOH
Output Leakage Current
Input Low Voltage
Input Low Voltage (CMOS)
Input High Voltage
0.7VDD
Input High Voltage (CMOS) VDD-0.3
Output Low Voltage
Output High Voltage
VDD-0.2
1
0.8
0.3
µA
V
V
V
V
V
V
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VDD=VDD Max
VDD=VDD Max
VDD=VDD Max
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
ISB
IALP
Min
0.2
T13.0 25020
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 19
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
©2011 Silicon Storage Technology, Inc.
DS25020A
18
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Table 14:Recommended System Power-up Timings
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
µs
Power-up to Program/Erase Operation
100
µs
TPU-WRITE
1
T14.0 25020
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 15:Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter
CI/O
1
CIN1
Description
Test Condition
Maximum
I/O Pin Capacitance
VI/O = 0V
10 pF
Input Capacitance
VIN = 0V
10 pF
T15.0 25020
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 16:Reliability Characteristics
Symbol
NEND1,2
TDR1
ILTH1
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
10,000
100
100 + IDD
Units
Cycles
Years
mA
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
T16.0 25020
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would
result in a higher minimum specification.
©2011 Silicon Storage Technology, Inc.
DS25020A
19
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
AC Characteristics
Table 17:Read Cycle Timing Parameters VDD = 2.7-3.6V
Symbol
Parameter
Min
Max
Units
TRC
Read Cycle Time
TCE
Chip Enable Access Time
70
70
ns
ns
TAA
Address Access Time
70
ns
TOE
Output Enable Access Time
35
ns
1
CE# Low to Active Output
0
ns
TOLZ1
OE# Low to Active Output
0
ns
TCHZ1
CE# High to High-Z Output
16
ns
TOHZ1
OE# High to High-Z Output
16
ns
TCLZ
1
0
ns
TRP1
RST# Pulse Width
500
ns
TRHR1
RST# High before Read
50
TRY1,2
RST# Pin Low to Read Mode
TOH
Output Hold from Address Change
ns
20
µs
T17.0 25020
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
Table 18:Program/Erase Cycle Timing Parameters
Symbol
Parameter
TBP
Word-Program Time
Min
Max
Units
10
µs
TAS
Address Setup Time
0
ns
TAH
Address Hold Time
30
ns
TCS
WE# and CE# Setup Time
0
ns
TCH
WE# and CE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
10
ns
TCP
CE# Pulse Width
40
ns
TWP
WE# Pulse Width
40
ns
TWPH1
TCPH1
WE# Pulse Width High
30
ns
CE# Pulse Width High
30
ns
TDS
Data Setup Time
30
ns
TDH1
Data Hold Time
0
ns
TIDA1
Software ID Access and Exit Time
150
ns
TSE
Sector-Erase
25
ms
TBE
Block-Erase
25
ms
TSCE
Chip-Erase
50
ms
TBY1,2
TBR1
RY/BY# Delay Time
0
µs
90
Bus Recovery Time
ns
T18.0 25020
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
©2011 Silicon Storage Technology, Inc.
DS25020A
20
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
TRC
TAA
ADDRESS AMS-0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
TCLZ
DQ15-0
TCHZ
TOH
HIGH-Z
DATA VALID
HIGH-Z
DATA VALID
1410 F03.0
Note: AMS = Most significant address
AMS = A20 for SST39VF3201C/3202C
Figure 5: Read Cycle Timing Diagram
TBP
ADDRESSES
555
2AA
555
ADDR
TAH
TWP
WE#
TWPH
TAS
OE#
TCH
CE#
TCS
TBY
TBR
RY/BY#
TDS
DQ15-0
XXAA
XX55
XXA0
TDH
DATA
WORD
(ADDR/DATA)
VALID
1410 F04.0
Note: WP# must be held in proper logic state (VIL or
VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 6: WE# Controlled Program Cycle Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25020A
21
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
TBP
ADDRESSES
555
2AA
555
ADDR
TAH
TCP
WE#
TAS
TCPH
OE#
TCH
CE#
TCS
TBY
TBR
RY/BY#
TDS
DQ15-0
XXAA
XX55
XXA0
TDH
DATA
VALID
WORD
(ADDR/DATA)
1410 F05.0
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 7: CE# Controlled Program Cycle Timing Diagram
ADDRESS A19-0-AMS-0
TCE
CE#
TOEH
TOES
OE#
TOE
WE#
TBY
RY/BY#
DQ7
DATA#
DATA
DATA#
DATA
1410 F06.0
Note: AMS = Most significant address
AMS = A20 for SST39VF3201C/3202C
Figure 8: Data# Polling Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25020A
22
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
ADDRESS AMS-0
TCE
CE#
TOEH
TOES
TOE
OE#
WE#
DQ6 and DQ2
TWO READ CYCLES
WITH SAME OUTPUTS
1410 F07.0
Note: AMS = Most significant address
AMS = A20 for SST39VF3201C/3202C
Figure 9: Toggle Bits Timing Diagram
TSCE
SIX-BYTE CODE FOR CHIP-ERASE
ADDRESSES
555
2AA
555
555
2AA
555
CE#
OE#
TOEH
WE#
TBY
TBR
RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
1410 F08.0
Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 18)
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 10:WE# Controlled Chip-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25020A
23
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
TBE
SIX-BYTE CODE FOR BLOCK-ERASE
ADDRESSES
555
2AA
555
555
2AA
BAX
CE#
OE#
TWP
WE#
TBR
TBY
RY/BY#
DQ15-0
XXAA
XX55
XXAA
XX80
XX55
XX30
VALID
1410 F09.0
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 18).
BAX = Block Address
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 11:WE# Controlled Block-Erase Timing Diagram
TSE
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESSES
555
2AA
555
555
2AA
SAX
CE#
OE#
TWP
WE#
TBY
TBR
RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
1410 F10.0
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 18).
SAX = Block Address
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 12:WE# Controlled Sector-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25020A
24
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Three-Byte Sequence for Software ID Entry
ADDRESS
555
2AA
555
0000
0001
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX90
SW0
SW1
SW2
00BF
Device ID
1410 F11.0
Note: Device ID = 235E for SST39VF3201Cand 235E for SST39VF3202C
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 13:Software ID Entry and Read
Three-Byte Sequence for CFI Query Entry
ADDRESS
555
2AA
555
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX98
SW0
SW1
SW2
1410 F12.0
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 14:CFI Query Entry and Read
©2011 Silicon Storage Technology, Inc.
DS25020A
25
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
DQ15-0
555
2AA
XXAA
555
XX55
XXF0
TIDA
CE#
OE#
TWP
WE#
TWHP
SW0
SW1
SW2
1410 F13.0
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 15:Software ID Exit/CFI Exit
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS AMS-0
555
2AA
555
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX88
SW0
SW1
SW2
1410 F14.0
Note: AMS = Most significant address
AMS = A20 for SST39VF3201C/3202C
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 16:Sec ID Entry
©2011 Silicon Storage Technology, Inc.
DS25020A
26
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
RY/BY#
0V
TRP
RST#
TRHR
CE#/OE#
1410 F15.0
Figure 17:RST# Timing Diagram (When no internal operation is in progress)
TRY
RY/BY#
TRP
RST#
CE#
TBR
OE#
1410 F16.0
Figure 18:RST# Timing Diagram (During Program or Erase operation)
©2011 Silicon Storage Technology, Inc.
DS25020A
27
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1410 F17.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall
times (10%  90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
Figure 19:AC Input/Output Reference Waveforms
TO TESTER
TO DUT
CL
1410 F18.0
Figure 20:A Test Load Example
©2011 Silicon Storage Technology, Inc.
DS25020A
28
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load Word
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
X can be VIL or VIH, but no other value
1410 F19.0
Figure 21:Word-Program Algorithm
©2011 Silicon Storage Technology, Inc.
DS25020A
29
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Internal Timer
Toggle Bit
Data# Polling
RY/BY#
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Wait TBP,
TSCE, TSE
or TBE
Read word
Read DQ7
Read RY/BY#
Read same
word
Program/Erase
Completed
No
Is DQ7 =
true data
No
Is
RY/BY# = 1
Yes
Yes
No
Does DQ6
match
Program/Erase
Completed
Program/Erase
Completed
Yes
Program/Erase
Completed
1410 F20.0
Figure 22:Wait Options
©2011 Silicon Storage Technology, Inc.
DS25020A
30
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
CFI Query Entry
Command Sequence
Sec ID Query Entry Software Product ID Entry
Command Sequence
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XX98H
Address: 55H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Wait TIDA
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX98H
Address: 555H
Read CFI data
Load data: XX88H
Address: 555H
Load data: XX90H
Address: 555H
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI data
Read Sec ID
Read Software ID
X can be VIL or VIH, but no other value
1410 F21.0
Figure 23:Software ID/CFI Entry Command Flowcharts
©2011 Silicon Storage Technology, Inc.
DS25020A
31
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAH
Wait TIDA
Load data: XXF0H
Address: 555H
Return to normal
operation
Wait TIDA
Return to normal
operation
X can be VIL or VIH, but no other value
1410 F22.0
Figure 24:Software ID/CFI Exit Command Flowcharts
©2011 Silicon Storage Technology, Inc.
DS25020A
32
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Chip-Erase
Command Sequence
Sector-Erase
Command Sequence
Block-Erase
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX50H
Address: SAX
Load data: XX30H
Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
X can be VIL or VIH, but no other value
1410 F23.0
Figure 25:Erase Command Sequence
©2011 Silicon Storage Technology, Inc.
DS25020A
33
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Product Ordering Information
SST
39 VF
XX XX
3201C XXXXX -
70 XX -
4I
XX
-
EKE
XXX
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Package Type
E = TSOP (type1, die up, 12mm x
20mm)
B3 = TFBGA (6mm x 8mm, 0.8mm
pitch)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
320= 32Mbit
Voltage
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash Plus
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid Combinations for SST39VF3201C
SST39VF3201C-70-4I-EKE
SST39VF3201C-70-4C-EKE
SST39VF3201C-70-4I-B3KE
SST39VF3201C-70-4C-B3KE
Valid Combinations for SST39VF3202C
SST39VF3202C-70-4I-EKE
SST39VF3202C-70-4C-EKE
SST39VF3202C-70-4I-B3KE
SST39VF3202C-70-4C-B3KE
Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST
sales representative to confirm availability of valid combinations and to determine availability of new combinations.
©2011 Silicon Storage Technology, Inc.
DS25020A
34
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Packaging Diagrams
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0°- 5°
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
1mm
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
0.70
0.50
48-tsop-EK-8
Figure 26:48-lead Thin Small Outline Package (TSOP) 12mm x 20mm,
SST Package Code: EK
©2011 Silicon Storage Technology, Inc.
DS25020A
35
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
TOP VIEW
BOTTOM VIEW
5.60
8.00 0.10
0.45 0.05
(48X)
0.80
6
6
5
5
4.00
4
4
6.00 0.10
3
3
2
2
1
1
0.80
A B C D E F G H
A1 CORNER
SIDE VIEW
H G F E D C B A
A1 CORNER
1.10 0.10
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-5
Figure 27:48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm,
SST Package Code: B3K
©2011 Silicon Storage Technology, Inc.
DS25020A
36
06/11
32 Mbit Multi-Purpose Flash Plus
SST39VF3201C / SST39VF3202C
A Microchip Technology Company
Preliminary Specifications
Table 19:Revision History
Number
00
01
A
Description
•
•
•
•
•
Initial release
Revised ISB and IALP in Table 13 on page 19
Applied new document format
Released document under letter revision system
Updated spec number from S71410 to DS25020
Date
Nov 2009
Aug 2010
Jun 2011
ISBN:978-1-61341-239-8
© 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.
SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and
registered trademarks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current
package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale.
For sales office(s) location and information, please see www.microchip.com.
Silicon Storage Technology, Inc.
A Microchip Technology Company
www.microchip.com
©2011 Silicon Storage Technology, Inc.
DS25020A
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06/11