MICROCHIP SST39VF200A

2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash
A Microchip Technology Company
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
The SST39LF200A/400A/800A and SST39VF200A/400A/800A devices are 128K
x16 / 256K x16 / 512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with
SST proprietary, high-performance CMOS SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF200A/400A/800A
write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF200A/400A/
800A write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories.
Features:
• Organized as 128K x16 / 256K x16 / 512K x16
• Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF200A/400A/800A
– 2.7-3.6V for SST39VF200A/400A/800A
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
(typical values at 14 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Fast Read Access Time
– 55 ns for SST39LF200A/400A/800A
– 70 ns for SST39VF200A/400A/800A
• Latched Address and Data
• Fast Erase and Word-Program
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time:
2 seconds (typical) for SST39LF/VF200A
4 seconds (typical) for SST39LF/VF400A
8 seconds (typical) for SST39LF/VF800A
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)
– 48-bump XFLGA (4mm x 6mm) – 4 and 8Mbit
• All non-Pb (lead-free) devices are RoHS compliant
©2011 Silicon Storage Technology, Inc.
www.microchip.com
DS25001A
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
Product Description
The SST39LF200A/400A/800A and SST39VF200A/400A/800A devices are 128K x16 / 256K x16 /
512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST proprietary, high-performance
CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate approaches. The SST39LF200A/400A/800A
write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF200A/400A/800A write (Program
or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16
memories.
Featuring high-performance Word-Program, the SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices provide a typical Word-Program time of 14 µsec. The devices use Toggle Bit or Data#
Polling to detect the completion of the Program or Erase operation. To protect against inadvertent
write, they have on-chip hardware and software data protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at greater than 100 years.
The SST39LF200A/400A/800A and SST39VF200A/400A/800A devices are suited for applications that
require convenient and economical updating of program, configuration, or data memory. For all system
applications, they significantly improve performance and reliability, while lowering power consumption.
They inherently use less energy during Erase and Program than alternative flash technologies. When
programming a flash device, the total energy consumed is a function of the applied voltage, current,
and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39LF200A/400A/800A and SST39VF200A/400A/800A
are offered in 48-lead TSOP packages and 48-ball TFBGA packages as well as Micro-Packages. See
Figures 2, 3, and 4 for pin assignments.
© 2011 Silicon Storage Technology, Inc.
DS25001A
2
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Block Diagram
X-Decoder
Memory Address
SuperFlash
Memory
Address Buffer Latches
Y-Decoder
CE#
I/O Buffers and Data Latches
Control Logic
OE#
WE#
DQ15 - DQ0
1117 B1.2
Figure 1: Functional Block Diagram
Pin Assignments
800A
400A
SST39LF/VF200A
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
SST39LF/VF200A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
Top View
Die Up
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
400A
800A
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
1117 48-tsop P01.3
Figure 2: Pin Assignments for 48-Lead TSOP
© 2011 Silicon Storage Technology, Inc.
DS25001A
3
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
TOP VIEW (balls facing down)
6
5
A15 A16 NC DQ15 VSS
A9
A8
A10
A11 DQ7 DQ14 DQ13 DQ6
WE# NC
NC
NC DQ5 DQ12 VDD DQ4
NC
NC
NC
NC DQ2 DQ10 DQ11 DQ3
A7
NC
A6
A5
DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# VSS
A
B
C
D
E
3
2
1
F
G
H
TOP VIEW (balls facing down)
TOP VIEW (balls facing down)
SST39LF/VF800A
SST39LF/VF400A
5
4
3
2
1
A13 A12 A14
A9
A8
WE# NC
NC
A7
NC
A17
A10
NC
NC
A6
6
A15 A16 NC DQ15 VSS
5
A11 DQ7 DQ14 DQ13 DQ6
4
NC DQ5 DQ12 VDD DQ4
3
NC DQ2 DQ10 DQ11 DQ3
A5
1117 48-tfbga P02 4.0
6
DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# VSS
A
B
C
D
E
F
G
H
2
1
A13 A12 A14
A15 A16 NC DQ15 VSS
A9
A8
A10
A11 DQ7 DQ14 DQ13 DQ6
WE# NC
NC
NC DQ5 DQ12 VDD DQ4
NC
NC
A18
NC DQ2 DQ10 DQ11 DQ3
A7
A17
A6
A5
DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# VSS
A
B
C
D
E
F
G
1117 48-tfbga P02 8.0
4
A13 A12 A14
1117 48-tfbga P02 2.0
SST39LF/VF200A
H
Figure 3: Pin Assignments for 48-Ball TFBGA
© 2011 Silicon Storage Technology, Inc.
DS25001A
4
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
TOP VIEW (balls facing down)
SST39VF200A
6
A2
A4
A6
NC
A1
A3
A7
NC
A0
A5
NC
NC
NC
WE#
NC
A9
A11
NC
A10
A13
A14
A8
A12
A15
5
4
3
DQ8 DQ10
VSS
OE# DQ9
DQ4 DQ11 A16
NC
NC
DQ5 DQ6 DQ7
1
DQ0 DQ1 DQ2 DQ3
A
B
C
D
E
VDD DQ12 DQ13 DQ14 DQ15 VSS
F
G
H
J
K
NC
A9
A11
NC
A10
A13
A14
A8
A12
A15
1117 48-xflga P03 2.0
CE#
2
L
TOP VIEW (balls facing down)
SST39LF/VF400A
6
A2
A4
A6
A17
A1
A3
A7
NC
A0
A5
NC
NC
NC
WE#
5
4
3
DQ8 DQ10
VSS
OE# DQ9
DQ4 DQ11 A16
NC
NC
DQ5 DQ6 DQ7
1
DQ0 DQ1 DQ2 DQ3
A
B
C
D
E
VDD DQ12 DQ13 DQ14 DQ15 VSS
F
G
H
J
K
NC
A9
A11
NC
A10
A13
A14
A8
A12
A15
1117 48-xflga P03 4.0
CE#
2
L
TOP VIEW (balls facing down)
SST39LF/VF800A
6
A2
A4
A6
A17
A1
A3
A7
NC
A0
A5
A18
NC
NC
WE#
5
4
3
DQ8 DQ10
VSS
OE# DQ9
DQ4 DQ11 A16
NC
NC
DQ5 DQ6 DQ7
1
DQ0 DQ1 DQ2 DQ3
A
B
C
D
E
VDD DQ12 DQ13 DQ14 DQ15 VSS
F
G
H
J
K
1117 48-xflga P03 8.0
CE#
2
L
Figure 4: Pin Assignments for 48-Ball WFBGA and 48-Bump XFLGA
© 2011 Silicon Storage Technology, Inc.
DS25001A
5
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Table 1: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses. During Sector-Erase AMS-A11 address lines will
select the sector. During Block-Erase AMS-A15 address lines will select the
block.
DQ15-DQ0
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD
Power Supply
To provide power supply voltage:
VSS
Ground
NC
No Connection
3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39VF200A/400A/800A
Unconnected pins.
T1.2 25001
1. AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A, and A18 for SST39LF/VF800A
© 2011 Silicon Storage Technology, Inc.
DS25001A
6
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39LF200A/400A/800A and SST39VF200A/400A/800A is controlled by
CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE#
is the output control and is used to gate data from the output pins. The data bus is in high impedance
state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure
5).
Word-Program Operation
The SST39LF200A/400A/800A and SST39VF200A/400A/800A are programmed on a word-by-word
basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data
Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the
internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever
occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 6 and 7
for WE# and CE# controlled Program operation timing diagrams and Figure 18 for flowcharts. During
the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal
Program operation are ignored.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39LF200A/400A/800A and SST39VF200A/400A/800A offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord.
The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector
address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The
sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H
or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 11 and 12 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored.
Chip-Erase Operation
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the “1” state. This is useful when the entire device
must be quickly erased.
© 2011 Silicon Storage Technology, Inc.
DS25001A
7
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid
read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored.
Write Operation Status Detection
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide two software means to detect
the completion of a write (Program or Erase) cycle, in order to optimize the system write cycle time.
The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-ofWrite detection mode is enabled after the rising edge of WE#, which initiates the internal Program or
Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the write cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST39LF200A/400A/800A and SST39VF200A/400A/800A are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data
immediately following the completion of an internal Write operation, the remaining data outputs may
still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after
an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once
the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the
rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling
timing diagram and Figure 19 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is
completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle
Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Blockor Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for
Toggle Bit timing diagram and Figure 19 for a flowchart.
Data Protection
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
© 2011 Silicon Storage Technology, Inc.
DS25001A
8
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program
operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to
initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g.,
during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte
sequence. This group of devices are shipped with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH,
but no other value, during any SDP command sequence.
Common Flash Memory Interface (CFI)
The SST39LF200A/400A/800A and SST39VF200A/400A/800A also contain the CFI information to
describe the characteristics of the device. In order to enter the CFI Query mode, the system must write
three-byte sequence, same as Software ID Entry command with 98H (CFI Query command) to
address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 5 through 9. The system must write the CFI Exit
command to return to Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as the SST39LF/VF200A, SST39LF/VF400A
and SST39LF/VF800A and manufacturer as SST. This mode may be accessed by software operations.
Users may use the Software Product Identification operation to identify the part (i.e., using the device
ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 13 for the Software ID Entry and Read timing diagram, and Figure 20 for the Software ID
Entry command sequence flowchart.
Table 2: Product Identification
Address
Data
0000H
00BFH
SST39LF/VF200A
0001H
2789H
SST39LF/VF400A
0001H
2780H
SST39LF/VF800A
0001H
2781H
Manufacturer’s ID
Device ID
T2.3 25001
© 2011 Silicon Storage Technology, Inc.
DS25001A
9
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to
the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program
or Erase operation. See Table 4 for software command codes, Figure 15 for timing waveform, and Figure 20 for a flowchart.
Operations
Table 3: Operation Modes Selection
Mode
CE#
OE#
WE#
DQ
Address
Read
VIL
VIL
VIH
DOUT
AIN
Program
VIL
VIH
VIL
DIN
AIN
Erase
VIL
VIH
VIL
X1
Sector or Block address,
XXH for Chip-Erase
Standby
VIH
X
X
High Z
X
X
VIL
X
High Z/ DOUT
X
X
X
VIH
High Z/ DOUT
X
VIL
VIL
VIH
Write Inhibit
Product Identification
Software Mode
See Table 4
T3.4 25001
1. X can be VIL or VIH, but no other value.
Table 4: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
Addr
Data
1
2
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
Data
Addr
Data
Addr
Data
Addr1
2
1
2
1
2
5th Bus
Write Cycle
6th Bus
Write Cycle
Data
Addr
Data
Addr1
2
1
2
Word-Program
5555H AAH
2AAAH
55H
5555H
A0H
WA3
Data
Sector-Erase
5555H AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SAX4
30H
Block-Erase
5555H AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
BAX4
50H
Chip-Erase
5555H AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
Software ID
Entry5,6
5555H AAH
2AAAH
55H
5555H
90H
CFI Query Entry5
5555H AAH
2AAAH
55H
5555H
98H
2AAAH
55H
5555H
F0H
Software ID Exit7/
CFI Exit
XXH
F0H
Software ID Exit7/ 5555H AAH
CFI Exit
T4.3 25001
1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.
AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A, and A18 for SST39LF/VF800A
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence
3. WA = Program word address
© 2011 Silicon Storage Technology, Inc.
DS25001A
10
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX for Block-Erase; uses AMS-A15 address lines
5. The device does not remain in Software Product ID mode if powered down.
SST Manufacturer’s ID = 00BFH, is read with A0 = 0,
6. With AMS-A1 = 0;
SST39LF/VF200A Device ID = 2789H, is read with A0 = 1.
SST39LF/VF400A Device ID = 2780H, is read with A0 = 1.
SST39LF/VF800A Device ID = 2781H, is read with A0 = 1.
7. Both Software ID Exit operations are equivalent
Table 5: CFI Query Identification String1 for SST39LF200A/400A/800A and
SST39VF200A/400A/800A
Address
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Data
0051H
0052H
0059H
0001H
0007H
0000H
0000H
0000H
0000H
0000H
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T5.0 25001
1. Refer to CFI publication 100 for more details.
Table 6: System Interface Information for SST39LF200A/400A/800A and SST39VF200A/
400A/800A
Address
Data
1BH
0027H1
Data
VDD Min (Program/Erase)
0030H1
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
0000H
VPP min (00H = no VPP pin)
1EH
0000H
VPP max (00H = no VPP pin)
1FH
0004H
Typical time out for Word-Program 2N µs (24 = 16 µs)
20H
0000H
Typical time out for min size buffer program 2N µs (00H = not supported)
21H
0004H
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H
0006H
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
23H
0001H
Maximum time out for Word-Program 2N times typical (21 x 24 = 32 µs)
24H
0000H
Maximum time out for buffer program 2N times typical
25H
0001H
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H
0001H
Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T6.2 25001
1. 0030H for SST39LF200A/400A/800A and 0027H for SST39VF200A/400A/800A
© 2011 Silicon Storage Technology, Inc.
DS25001A
11
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Table 7: Device Geometry Information for SST39LF/VF200A
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Data
0012H
0001H
0000H
0000H
Data
Device size = 2N Byte (12H = 18; 218 = 256 KByte)
Flash Device Interface description; 0001H = x16-only asynchronous interface
0002H
003FH
0000H
0010H
0000H
0003H
0000H
0000H
0001H
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 63 + 1 = 64 sectors (003FH = 63)
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 3 + 1 = 4 blocks (0003H = 3)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T7.2 25001
Table 8: Device Geometry Information for SST39LF/VF400A
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Data
0013H
0001H
0000H
0000H
0000H
0002H
007FH
0000H
0010H
0000H
0007H
0000H
0000H
0001H
Data
Device size = 2N Byte (13H = 19; 219 = 512 KByte)
Flash Device Interface description; 0001H = x16-only asynchronous interface
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 127 + 1 = 128 sectors (007FH = 127)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 7 + 1 = 8 blocks (0007H = 7)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T8.1 25001
© 2011 Silicon Storage Technology, Inc.
DS25001A
12
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Table 9: Device Geometry Information for SST39LF/VF800A
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Data
0014H
0001H
0000H
0000H
0000H
0002H
00FFH
0000H
0010H
0000H
000FH
0000H
0000H
0001H
Data
Device size = 2N Bytes (14H = 20; 220 = 1 MByte)
Flash Device Interface description; 0001H = x16-only asynchronous interface
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 255 + 1 = 256 sectors (00FFH = 255)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 15 + 1 = 16 blocks (000FH = 15)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T9.0 25001
© 2011 Silicon Storage Technology, Inc.
DS25001A
13
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest
information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range: SST39LF200A/400A/800A
Range
Commercial
Ambient Temp
VDD
0°C to +70°C
3.0-3.6V
T9.1 25001
Operating Range: SST39VF200A/400A/800A
Range
Ambient Temp
Commercial
Industrial
VDD
0°C to +70°C
2.7-3.6V
-40°C to +85°C
2.7-3.6V
T9.1 25001
Table 10:AC Conditions of Test1
Input Rise/Fall Time
Output Load
SST39LF200A/400A/800A
Output Load
SST39VF200A/400A/800A
5ns
CL = 30 pF
CL = 100 pF
T10.1 25001
1. See Figures 16 and 17
© 2011 Silicon Storage Technology, Inc.
DS25001A
14
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Table 11:DC Operating Characteristics –VDD = 3.0-3.6V for SST39LF200A/400A/800A and
2.7-3.6V for SST39VF200A/400A/800A1
Limits
Symbol Parameter
Min
Max
Units
Power Supply Current
IDD
Test Conditions
Address input=VILT/VIHT, at f=1/TRC
Min, VDD=VDD Max
Read2
30
mA
CE#=VIL, OE#=WE#=VIH, all I/Os
open
Program and Erase
30
mA
CE#=WE#=VIL, OE#=VIH
ISB
Standby VDD Current
20
µA
CE#=VIHC, VDD=VDD Max
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
10
µA
VOUT=GND to VDD, VDD=VDD Max
VIL
Input Low Voltage
VIH
Input High Voltage
0.7VDD
V
VDD=VDD Max
VIHC
Input High Voltage (CMOS)
VDD-0.3
VOL
Output Low Voltage
VOH
Output High Voltage
0.8
0.2
VDD-0.2
VDD=VDD Min
V
VDD=VDD Max
V
IOL=100 µA, VDD=VDD Min
V
IOH=-100 µA, VDD=VDD Min
T11.7 25001
1. Typical conditions for the Active Current shown on page 1 are average values at 25°C (room temperature),
and VDD = 3V for VF devices. Not 100% tested.
2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.
Table 12:Recommended System Power-up Timings
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
µs
TPU-WRITE1
Power-up to Program/Erase Operation
100
µs
T12.0 25001
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 13:Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter Description
CI/O1
1
CIN
Test Condition
Maximum
I/O Pin Capacitance
VI/O = 0V
12 pF
Input Capacitance
VIN = 0V
6 pF
T13.0 25001
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 14:Reliability Characteristics
Symbol
Parameter
Minimum Specification
Units
Test Method
NEND1,2
Endurance
10,000
Cycles
JEDEC Standard A117
TDR1
Data Retention
100
Years
JEDEC Standard A103
ILTH1
Latch Up
100 + IDD
mA
JEDEC Standard 78
T14.2 25001
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would
result in a higher minimum specification.
© 2011 Silicon Storage Technology, Inc.
DS25001A
15
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
AC Characteristics
Table 15:Read Cycle Timing Parameters VDD = 3.0-3.6V
SST39LF200A/400A/800A55
Symbol
Parameter
TRC
Read Cycle Time
TCE
Chip Enable Access Time
55
ns
TAA
Address Access Time
55
ns
TOE
Output Enable Access Time
30
ns
TCLZ1
CE# Low to Active Output
0
1
OE# Low to Active Output
0
TOLZ
TCHZ1
CE# High to High-Z Output
1
OE# High to High-Z Output
TOHZ
TOH1
Min
Max
Units
55
ns
ns
ns
15
ns
15
Output Hold from Address Change
ns
0
ns
T15.7 25001
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 16:Read Cycle Timing Parameters VDD = 2.7-3.6V
SST39VF200A/400A/800A70
Min
Symbol Parameter
Max
Unit
s
TRC
Read Cycle Time
TCE
Chip Enable Access Time
70
ns
TAA
Address Access Time
70
ns
TOE
Output Enable Access Time
TCLZ1
CE# Low to Active Output
0
TOLZ1
OE# Low to Active Output
0
TCHZ1
CE# High to High-Z Output
1
OE# High to High-Z Output
TOHZ
TOH1
70
ns
35
ns
ns
ns
20
ns
20
Output Hold from Address Change
ns
0
ns
T16.7 25001
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
© 2011 Silicon Storage Technology, Inc.
DS25001A
16
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Table 17:Program/Erase Cycle Timing Parameters
Symbol Parameter
Min
Max
Units
20
µs
TBP
Word-Program Time
TAS
Address Setup Time
0
ns
TAH
Address Hold Time
30
ns
TCS
WE# and CE# Setup Time
0
ns
TCH
WE# and CE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
10
ns
TCP
CE# Pulse Width
40
ns
TWP
WE# Pulse Width
40
ns
TWPH1
WE# Pulse Width High
30
ns
TCPH1
CE# Pulse Width High
30
ns
TDS
Data Setup Time
30
ns
TDH1
Data Hold Time
0
ns
TIDA1
Software ID Access and Exit Time
TSE
Sector-Erase
TBE
Block-Erase
25
ms
TSCE
Chip-Erase
100
ms
150
ns
25
ms
T17.0 25001
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
© 2011 Silicon Storage Technology, Inc.
DS25001A
17
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
TRC
TAA
ADDRESS AMS-0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
TCLZ
HIGH-Z
DQ15-0
Note:
TCHZ
TOH
DATA VALID
HIGH-Z
DATA VALID
AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
1117 F03.2
Figure 5: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
ADDRESS AMS-0
2AAA
5555
ADDR
TAH
TDH
TWP
WE#
TAS
TDS
TWPH
OE#
TCH
CE#
TCS
DQ15-0
Note:
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
X can be VIL or VIH, but no other value.
1117 F04.4
Figure 6: WE# Controlled Program Cycle Timing Diagram
© 2011 Silicon Storage Technology, Inc.
DS25001A
18
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
ADDRESS AMS-0
2AAA
5555
ADDR
TAH
TDH
TCP
CE#
TAS
TCPH
TDS
OE#
TCH
WE#
TCS
DQ15-0
Note:
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
X can be VIL or VIH, but no other value.
1117 F05.4
Figure 7: CE# Controlled Program Cycle Timing Diagram
ADDRESS AMS-0
TCE
CE#
TOEH
TOES
OE#
TOE
WE#
DQ7
Note:
DATA
DATA#
DATA#
DATA
AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
1117 F06.3
Figure 8: Data# Polling Timing Diagram
© 2011 Silicon Storage Technology, Inc.
DS25001A
19
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
ADDRESS AMS-0
TCE
CE#
TOEH
TOE
TOES
OE#
WE#
DQ6
TWO READ CYCLES
WITH SAME OUTPUTS
Note:
AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
1117 F07.3
Figure 9: Toggle Bit Timing Diagram
TSCE
SIX-BYTE CODE FOR CHIP-ERASE
ADDRESS AMS-0
5555
2AAA
5555
5555
2AAA
5555
CE#
OE#
TWP
WE#
DQ15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 16)
AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
X can be VIL or VIH, but no other value.
1117 F08.7
Figure 10:WE# Controlled Chip-Erase Timing Diagram
© 2011 Silicon Storage Technology, Inc.
DS25001A
20
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
TBE
SIX-BYTE CODE FOR BLOCK-ERASE
ADDRESS AMS-0
5555
2AAA
5555
5555
2AAA
BAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
SW0
SW1
SW2
SW3
SW4
SW5
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 16)
BAX = Block Address
AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
X can be VIL or VIH, but no other value.
1117 F17.9
Figure 11:WE# Controlled Block-Erase Timing Diagram
TSE
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESS AMS-0
5555
2AAA
5555
5555
2AAA
SAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
SW0
SW1
SW2
SW3
SW4
SW5
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 16)
SAX = Sector Address
AMS = Most significant address
AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A
X can be VIL or VIH, but no other value.
1117 F18.8
Figure 12:WE# Controlled Sector-Erase Timing Diagram
© 2011 Silicon Storage Technology, Inc.
DS25001A
21
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A14-0
5555
2AAA
5555
0000
0001
CE#
OE#
TWP
TIDA
WE#
TWPH
DQ15-0
XXAA
SW0
XX55
SW1
TAA
XX90
SW2
00BF
Device ID
Device ID = 2789H for SST39LF/VF200A, 2780H for SST39LF/VF400A and 2781H for SST39LF/VF800A
Note:
X can be VIL or VIH, but no other value.
1117 F09.4
Figure 13:Software ID Entry and Read
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A14-0
5555
2AAA
5555
CE#
OE#
TIDA
TWP
WE#
TAA
TWPH
DQ15-0
XXAA
SW0
XX55
SW1
XX98
SW2
Note: X can be VIL or VIH, but no other value.
1117 F20.1
Figure 14:CFI Query Entry and Read
© 2011 Silicon Storage Technology, Inc.
DS25001A
22
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
DQ15-0
5555
2AAA
XXAA
5555
XX55
XXF0
TIDA
CE#
OE#
TWP
TWHP
WE#
SW0
Note:
SW1
SW2
X can be VIL or VIH, but no other value.
1117 F10.1
Figure 15:Software ID Exit/CFI Exit
© 2011 Silicon Storage Technology, Inc.
DS25001A
23
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1117 F11.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise
and fall times (10%  90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
Figure 16:AC Input/Output Reference Waveforms
TO TESTER
TO DUT
CL
1117 F12.1
Figure 17:A Test Load Example
© 2011 Silicon Storage Technology, Inc.
DS25001A
24
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
Note:
X can be VIL or VIH, but no other value.
1117 F13.4
Figure 18:Word-Program Algorithm
© 2011 Silicon Storage Technology, Inc.
DS25001A
25
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Wait TBP,
TSCE, TSE
or TBE
Read word
Read DQ7
Read same
word
Program/Erase
Completed
No
Is DQ7 =
true data
Yes
No
Does DQ6
match
Program/Erase
Completed
Yes
Program/Erase
Completed
1117 F14.0
Figure 19:Wait Options
© 2011 Silicon Storage Technology, Inc.
DS25001A
26
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
CFI Query Entry
Command Sequence
Software ID Entry
Command Sequence
Software ID Exit/CFI Exit
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Wait TIDA
Load data: XX98H
Address: 5555H
Load data: XX90H
Address: 5555H
Load data: XXF0H
Address: 5555H
Return to normal
operation
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI data
Read Software ID
Return to normal
operation
1117 F15.4
Note:
X can be VIL or VIH, but no other value.
Figure 20:Software ID/CFI Command Flowcharts
© 2011 Silicon Storage Technology, Inc.
DS25001A
27
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
Chip-Erase
Command Sequence
Sector-Erase
Command Sequence
Block-Erase
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Address: SAX
Load data: XX50H
Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
Note:
X can be VIL or VIH, but no other value.
1117 F16.5
Figure 21:Erase Command Sequence
© 2011 Silicon Storage Technology, Inc.
DS25001A
28
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Product Ordering Information
SST
39 VF
XX XX
200A XXXX -
70 XX -
4C
XX
-
B3KE
XXXX
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 leads or balls
Q = 48 balls or bumps (66 possible positions)
Package Type
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)
C1 = XFLGA (0.5mm pitch, 4mm x 6mm)
E = TSOP (type 1, die up, 12mm x 20mm)
M1 = WFBGA (0.5mm pitch, 4mm x 6mm)
MA = WFBGA (0.5mm pitch, 4mm x 6mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
55 = 55 ns
70 = 70 ns
Version
A = Special Feature Version
Device Density
800 = 8 Mbit
400 = 4 Mbit
200 = 2 Mbit
Voltage
L = 3.0-3.6V
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
© 2011 Silicon Storage Technology, Inc.
DS25001A
29
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
Valid combinations for SST39LF200A
SST39LF200A-55-4C-EKE
SST39LF200A-55-4C-B3KE
Valid combinations for SST39VF200A
SST39VF200A-70-4C-EKE
SST39VF200A-70-4C-MAQE
SST39VF200A-70-4I-EKE
SST39VF200A-70-4I-MAQE
SST39VF200A-70-4C-B3KE
SST39VF200A-70-4C-M1QE
SST39VF200A-70-4I-B3KE
SST39VF200A-70-4I-M1QE
Valid combinations for SST39LF400A
SST39LF400A-55-4C-EKE
SST39LF400A-55-4C-B3KE
SST39LF400A-55-4C-MAQE
Valid combinations for SST39VF400A
SST39VF400A-70-4C-EKE
ST39VF400A-70-4C-M1QE
SST39VF400A-70-4I-EKE
SST39VF400A-70-4I-M1QE
SST39VF400A-70-4C-B3KE
SST39VF400A-70-4C-MAQE
SST39VF400A-70-4I-B3KE
SST39VF400A-70-4I-MAQE
SST39VF400A-70-4C-C1QE
SST39VF400A-70-4I-C1QE
Valid combinations for SST39LF800A
SST39LF800A-55-4C-EKE
SST39LF800A-55-4C-B3KE
SST39LF800A-55-4C-MAQE
Valid combinations for SST39VF800A
SST39VF800A-70-4C-EKE
SST39VF800A-70-4C-M1QE
SST39VF800A-70-4I-EKE
SST39VF800A-70-4I-M1QE
SST39VF800A-70-4C-B3KE
SST39VF800A-70-4C-MAQE
SST39VF800A-70-4I-B3KE
SST39VF800A-70-4I-MAQE
SST39VF800A-70-4C-C1QE
SST39VF800A-70-4I-C1QE
Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST
sales representative to confirm availability of valid combinations and to determine availability of new combinations.
© 2011 Silicon Storage Technology, Inc.
DS25001A
30
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Packaging Diagrams
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0°- 5°
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
1mm
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
0.70
0.50
48-tsop-EK-8
Figure 22:48-Lead Thin Small Outline Package (TSOP) 12mm x 20mm
SST Package Code: EK
© 2011 Silicon Storage Technology, Inc.
DS25001A
31
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
TOP VIEW
BOTTOM VIEW
5.60
8.00 0.10
0.45 0.05
(48X)
0.80
6
6
5
5
4.00
4
4
6.00 0.10
3
3
2
2
1
1
0.80
A B C D E F G H
A1 CORNER
SIDE VIEW
H G F E D C B A
A1 CORNER
1.10 0.10
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-5
Figure 23:48-Ball Thin-Profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K
© 2011 Silicon Storage Technology, Inc.
DS25001A
32
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
TOP VIEW
BOTTOM VIEW
6.00
0.08
5.00
0.32
0.05
(48X)
0.50
6
5
4
3
2
1
4.00
0.08
6
5
4
3
2
1
2.50
0.50
A B C D E F G H J K L
L K J H G F E D C B A
A1 INDICATOR4
A1 CORNER
0.63 0.10
DETAIL
SIDE VIEW
0.08
SEATING PLANE
0.20
0. 06
Note:
1.
2.
3.
4.
5.
1mm
Complies with JEDEC Publication 95, MO-207, Variant C2B-4, dimensions except nominal ball width is larger.
All linear dimensions are in millimeters.
Coplanarity: 0.08 mm.
No ball is present in position A1; a gold-colored indicator is present.
Ball opening size is 0.29 mm ( 0.05 mm).
48-wfbga-M1Q-4x6-32mic-6.0
Figure 24:48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 4mm x 6mm
SST Package Code: M1Q
© 2011 Silicon Storage Technology, Inc.
DS25001A
33
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
TOP VIEW
BOTTOM VIEW
5.00
6.00
0.08
6
5
4
3
2
1
0.50
4.00
0.08
0.50
A1 CORNER
DETAIL
6
5
4
3
2
1
2.50
A B C D E F G H J K L
0.32 0.05
(48X)
L K J H G F E D C B A
A1 INDICATOR
0.73 max.
0.636 nom.
SIDE VIEW
0.08
SEATING PLANE
0.20 0.06
Note:
1mm
1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger
and bottom side A1 indicator is triangle at corner.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. Ball opening size is 0.29 mm ( 0.05 mm)
48-wfbga-MAQ-4x6-32mic-2.0
Figure 25:48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 4mm x 6mm
SST Package Code: MAQ
© 2011 Silicon Storage Technology, Inc.
DS25001A
34
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
TOP VIEW
BOTTOM VIEW
6.00
0.08
5.00
0.29
0.05
(48X)
0.50
6
5
4
3
2
1
4.00
0.08
2.50
0.50
A B C D E F G H J K L
A1 CORNER
DETAIL
6
5
4
3
2
1
L K J H G F E D C B A
A1 INDICATOR
0.52 max.
0.473 nom.
4
SIDE VIEW
0.05
SEATING PLANE
0.04
+0.025/-0.015
Note: 1.
2.
3.
4.
5.
1mm
Complies with JEDEC Publication 95, MO-207, variant CZB-4, dimensions except bump height is much less.
All linear dimensions are in millimeters.
Coplanarity: 0.05 mm.
No ball is present at A1; a gold-colored indicator is present.
Bump opening size is 0.29 ( 0.05 mm).
48-xflga-C1Q-4x6-29mic-6.0
Figure 26: 48-Bump Extremely-Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) 4mm x 6mm
SST Package Code: C1Q
© 2011 Silicon Storage Technology, Inc.
DS25001A
35
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
A Microchip Technology Company
Data Sheet
Table 18:Revision History
Revision
04
05
Description
•
•
•
•
•
06
•
07
•
•
•
•
•
•
08
•
09
•
11
•
•
•
•
12
•
13
•
•
•
•
•
10
A
Date
2002 Data Book
Added footnotes for MPF power usage and Typical conditions to Table 11
on page 15
Clarified the Test Conditions for Power Supply Current and Read parameters in Table 11 on page 15
Part number changes - see page 30 for additional information
New Micro-Package part numbers added for SST39VF400A and
SST39VF800A
New Micro-Package part numbers added for SST39VF400A / 800A (see
page 30)
2004 Data Book
Updated the B3K, M1Q, and C1Q package diagrams
Added non-Pb MPNs and removed footnote (see page 30)
Added M1Q/M1QE MPNs for the SSTVF200A device on page 30
Removed 90ns MPNs and footnote for the SSTVFx00A devices on page 30
Added RoHS compliance information on page 1 and in the “Product Ordering Information” on page 29
Clarified the solder temperature profile under “Absolute Maximum Stress
Ratings” on page 14.
Removed valid combinations SST39LF400A-45-4C-EK, SST39LF400A-454C-B3K,
SST39LF400A-45-4C-EKE, and SST39LF400A-45-4C-B3KE due to EOL
Applied new format styles.
Add Y1QE package
Removed all pb parts
EOL of all Y1QE parts. Replacement parts are M1QE parts in this document.
EOL of SST39LF200A-45-4C-EKE and SST39LF200A-45-4C-B3KE. See
S71117(12). Replacement parts are SST39LF200A-55-4C-EKE and
SST39LF200A-55-4C-B3KE found in this document.
Added MAQE package information
Applied new document format
Released document under letter revision system.
Updated Spec number from S71117 to DS25001.
Updated TIDA value in Table 17 on page 17 from max 150 ns to min 150 ns.
© 2011 Silicon Storage Technology, Inc.
May 2002
Mar 2003
Oct 2003
Nov 2003
Apr 2005
Feb 2007
Aug 2007
Dec 2009
Apr 2010
Nov 2010
Mar 2011
DS25001A
36
03/11
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
ISBN:978-1-61341-026-4
© 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.
SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and
registered trademarks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale.
For sales office(s) location and information, please see www.microchip.com.
Silicon Storage Technology, Inc.
A Microchip Technology Company
www.microchip.com
© 2011 Silicon Storage Technology, Inc.
DS25001A
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03/11