LMZ10505EXT 5A SIMPLE SWITCHER® Power Module with 5.5V Maximum Input Voltage for Military and Rugged Applications Easy to Use 7 Pin Package Performance Benefits ● Operates at high ambient temperatures ● Low radiated emissions (EMI) complies with EN55022 class B standard (Note 2) ● Passes 10V/m radiated immunity EMI test standard EN61000 4-3 ● Passes vibration standard 30118302 TO-PMOD 7 Pin Package 10.16 x 13.77 x 4.57 mm (0.4 x 0.39 x 0.18 in) θJA = 20°C/W, θJC = 1.9°C/W (Note 1) RoHS Compliant MIL-STD-883 Method 2007.2 Condition A JESD22-B103B Condition 1 ● Passes drop standard MIL-STD-883 Method 2002.3 Condition B JESD22-B110 Condition B Electrical Specifications ● ● ● ● ● ● 25W maximum total output power Up to 5A output current Input voltage range 2.95V to 5.5V Output voltage range 0.8V to 5V ±1.63% feedback voltage accuracy over temperature Efficiency up to 96% System Performance Current Derating (VOUT = 3.3V) Key Features ● Integrated shielded inductor ● Flexible startup sequencing using external soft-start, tracking, and precision enable ● Protection against in-rush currents and faults such as input ● ● ● ● ● ● UVLO and output short-circuit -55°C to +125°C junction temperature operating range Single exposed pad and standard pinout for easy mounting and manufacturing Pin-to-pin compatible with LMZ10503EXT (3A/15W max) LMZ10504EXT (4A/20W max) Fully enable for WEBENCH® and Power Designer Low output voltage ripple of 10 mV allows for powering noise-sensitive transceiver and signaling ICs Fast transient response for powering FPGAs and ASICs 30118371 Applications ● ● ● ● 30118313 Efficiency (VOUT = 3.3V) Radiated Emissions (EN 55022, Class B) Point-of-load conversions from 3.3V and 5V rails Space constrained applications Extreme temperatures/no air flow environments Noise sensitive applications (i.e. transceiver, medical) 30118312 Note 1: θ JA measured on a 2.25” x 2.25” (5.8 cm x 5.8 cm) four layer board. Refer to PCB Layout Diagrams or Evaluation Board Application Note: AN-2074. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 301183 SNVS669D Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT Note 2: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See Figure 5 and layout for information on device under test. Typical Application Circuit 30118301 Connection Diagram 30118372 Top View 7-Lead TO-PMOD Ordering Information 2 Order Number Supplied As Package Type NSC Package Drawing Package Marking LMZ10505EXTTZ 250 Units in Tape and Reel TO-PMOD-7 TZA07A LMZ10505EXT LMZ10505EXTTZX 500 Units in Tape and Reel LMZ10505EXTTZE 45 Units in a Rail Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT Pin Descriptions Pin Number Name Description 1 VIN A low ESR input capacitance should be located as close as possible to VIN pin and GND pin. 2 EN Active high enable input for the device. 3 SS Soft-start control pin. An internal 2 uA current source charges and external capacitor connected between this pin and GND (pin 4) to set the output voltage ramp rate during startup. This pin can also be used to configure the tracking feature. 4 GND Power ground and signal ground. Connect the bottom feedback resistor between this pin and the feedback pin. Feedback pin. This is the inverting input of the error amplifier used for sensing the output voltage. 5 FB 6, 7 VOUT This is the output of the internal inductor. Connect an external resistor voltage divider from VOUT to FB to ground. EP Exposed Pad Exposed pad thermal connection. Connect this pad to the PC board ground plane in order to reduce thermal resistance value. It also provides an electrical connection to the input and output capacitors ground terminals. Copyright © 1999-2012, Texas Instruments Incorporated 3 LMZ10505EXT Absolute Maximum Ratings (Note 5) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. VIN, VOUT, EN, FB, SS to GND -0.3V to 6.0V ESD Susceptibility (Note 6) ±2 kV Power Dissipation Internally Limited Junction Temperature 150°C Storage Temperature Range -65°C to 150°C Peak Reflow Case Temperature 245°C (30 sec) For soldering specifications, refer to the following document: www.ti.com/lit/snoa549c Operating Ratings (Note 5) VIN to GND Junction Temperature (TJ) 2.95V to 5.5V -55°C to 125°C Electrical Characteristics Specifications with standard typeface are for TJ = 25°C only; limits in bold face type apply over the operating junction temperature range TJ of -55°C to 125°C. Minimum and maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = VEN = 3.3V, unless otherwise indicated in the conditions column. Symbol Parameter Conditions Min (Note 7) Typ (Note 8) Max (Note 7) Units SYSTEM PARAMETERS V FB Total Feedback Voltage Variation Including Line and Load Regulation VIN = 2.95V to 5.5V VOUT = 2.5V IOUT = 0A to 5A 0.78 0.8 0.82 V V FB Feedback Voltage Variation VIN = 3.3V, VOUT = 2.5V IOUT = 0A 0.787 0.8 0.812 V V FB Feedback Voltage Variation VIN = 3.3V, VOUT = 2.5V IOUT = 5A 0.785 0.798 0.81 V 2.6 2.95 V 1.55 3 mA 267 500 µA 7.3 8.7 A VIN(UVLO) Input UVLO Threshold (Measured at VIN Rising pin) Falling ISS Soft-Start Current Charging Current IQ Non-Switching Input Current VFB = 1V ISD Shut Down Quiescent Current VIN = 5.5V, VEN = 0V IOCL Output Current Limit (Average Current) VOUT = 2.5V fFB Frequency Fold-back In current limit 1.95 2.4 2 5.1 µA 250 kHz PWM SECTION fSW Drange Switching Frequency 700 PWM Duty Cycle Range 1000 0 1160 kHz 100 % 1.8 V ENABLE CONTROL VEN-IH EN Pin Rising Threshold VEN-IF EN Pin Falling Threshold 1.23 1.06 V TJ for Thermal Shutdown 145 °C Hysteresis for Thermal Shutdown 10 °C 0.8 THERMAL CONTROL TSD TSD-HYS THERMAL RESISTANCE 4 θJA Junction to Ambient (Note 1) 20 °C/W θJC Junction to Case No air flow 1.9 °C/W Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT Electrical Characteristics Specifications with standard typeface are for TJ = 25°C only; limits in bold face type apply over the operating junction temperature range TJ of -55°C to 125°C. Minimum and maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = VEN = 3.3V, unless otherwise indicated in the conditions column. Symbol Parameter Conditions Min (Note 7) Typ (Note 8) Max (Note 7) Units PERFORMANCE PARAMETERS ΔVOUT Output Voltage Ripple Refer to Table 3 VOUT = 2.5V Bandwidth Limit = 2 MHz 10 mVpk-pk ΔVOUT Output Voltage Ripple Refer to Table 5 Bandwidth Limit = 20 MHz 5 mVpk-pk Feedback Voltage Line Regulation ΔVIN = 2.95V to 5.5V 0.04 % 0.04 % ΔVFB / VFB IOUT = 0A ΔVOUT / VOUT Output Voltage Line Regulation ΔVIN = 2.95V to 5.5V IOUT = 0A, VOUT = 2.5V ΔVFB / VFB ΔVOUT / VOUT Feedback Voltage Load Regulation IOUT = 0A to 5A 0.25 % Output Voltage Load Regulation IOUT = 0A to 5A VOUT = 2.5V 0.25 % VOUT = 3.3V 96.1 VOUT = 2.5V 94.8 VOUT = 1.8V 93.1 VOUT = 1.5V 92 VOUT = 1.2V 90.4 VOUT = 0.8V 86.8 VOUT = 2.5V 95.7 VOUT = 1.8V 94.1 VOUT = 1.5V 93.0 VOUT = 1.2V 91.6 VOUT = 0.8V 88.3 VOUT = 3.3V 93.1 VOUT = 2.5V 91.2 VOUT = 1.8V 88.5 VOUT = 1.5V 86.7 VOUT = 1.2V 84.1 VOUT = 0.8V 78.2 VOUT = 2.5V 89.8 VOUT = 1.8V 86.9 VOUT = 1.5V 85.1 VOUT = 1.2V 82.5 VOUT = 0.8V 76.2 Efficiency η η η η Peak Efficiency (1A) VIN = 5V Peak Efficiency (1A) VIN = 3.3V Full Load Efficiency (5A) VIN = 5V Full Load Efficiency (5A) VIN = 3.3V % % % % Note 3: θ JA measured on a 2.25” x 2.25” (5.8 cm x 5.8 cm) four layer board, with one ounce copper, thirty six 10mil thermal vias, no air flow, and 1W power dissipation. Refer to or Evaluation Board Application Note: AN-2074. Note 4: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See and layout for information on device under test. Note 5: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 6: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD22-AI14S. Note 7: Min and Max limits are 100% production tested at an ambient temperature (TA) of 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 8: Typical numbers are at 25°C and represent the most likely parametric norm. Copyright © 1999-2012, Texas Instruments Incorporated 5 LMZ10505EXT Typical Performance Characteristics Unless otherwise specified, the following conditions apply: VIN = VEN = 5.0V, CIN is 47 µF 10V X5R ceramic capacitor; TAMBIENT = 25°C for efficiency curves and waveforms. Load Transient Response VIN = 3.3V, VOUT = 2.5V, IOUT = 0.5A to 4.5A to 0.5A step 20 MHz Bandwidth Limited Refer to Table 5 for BOM, includes optional components Load Transient Response VIN = 5.0V, VOUT = 2.5V, IOUT = 0.5A to 4.5A to 0.5A step 20 MHz Bandwidth Limited Refer to Table 5 for BOM, includes optional components 30118362 Output Voltage Ripple VIN = 3.3V, VOUT = 2.5V, IOUT = 5A, 20 mV/DIV Refer to Table 5 for BOM 30118363 Output Voltage Ripple VIN = 5.0V, VOUT = 2.5V, IOUT = 5A, 20 mV/DIV Refer to Table 5 for BOM 30118365 30118364 Efficiency VOUT = 3.3V Efficiency VOUT = 2.5V 30118371 6 30118370 Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT Efficiency VOUT = 1.8V Efficiency VOUT = 1.5V 30118369 Efficiency VOUT = 1.2V 30118311 Efficiency VOUT = 0.8V 30118368 Current Derating VIN = 5V, θJA = 20°C / W Current Derating VIN = 3.3V, θJA = 20°C / W 30118314 Copyright © 1999-2012, Texas Instruments Incorporated 30118367 30118315 7 LMZ10505EXT Radiated Emissions (EN 55022, Class B) VIN = 5V, VOUT = 2.5V, IOUT = 5A Evaluation Board Startup VOUT = 2.5V, IOUT = 0A 30118356 30118312 Pre-biased Startup VOUT = 2.5V, IOUT = 0A 30118355 8 Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT Block Diagram 30118317 General Description The LMZ10505EXT SIMPLE SWITCHER® power module is a complete, easy-to-use DC-DC solution capable of driving up to a 5A load with exceptional power conversion efficiency, output voltage accuracy, line and load regulation. The LMZ10505EXT is available in an innovative package that enhances thermal performance and allows for hand or machine soldering. The LMZ10505EXT can accept an input voltage rail between 2.95V and 5.5V and deliver an adjustable and highly accurate output voltage as low as 0.8V. One megahertz fixed frequency PWM switching provides a predictable EMI characteristic. Two external compensation components can be adjusted to set the fastest response time, while allowing the option to use ceramic and/or electrolytic output capacitors. Externally programmable soft-start capacitor facilitates controlled startup. The LMZ10505EXT is a reliable and robust solution with the following features: lossless cycle-by-cycle peak current limit to protect for over current or shortcircuit fault, thermal shutdown, input under-voltage lock-out, and pre-biased startup. Design Guideline And Operating Description Design Steps LMZ10505EXT is fully supported by Webench® and offers the following: component selection, performance, electrical, and thermal simulations as well as the Build-It board, for a reduced design time. On the other hand, all external components can be calculated by following the design procedure below. 1. Determine the input voltage and output voltage. Also, make note of the ripple voltage and voltage transient requirements. 2. Determine the necessary input and output capacitance. 3. Calculate the feedback resistor divider. 4. Select the optimized compensation component values. 5. Estimate the power dissipation and board thermal requirements. 6. Follow the PCB design guideline. 7. Learn about the LMZ10505EXT features such as enable, input UVLO, soft-start, tracking, pre-biased startup, current limit, and thermal shutdown. Design Example For this example the following application parameters exist. • VIN = 5V • VOUT = 2.5V • IOUT = 5A • ΔVOUT = 20 mVpk-pk • ΔVo_tran = ±20 mVpk-pk Copyright © 1999-2012, Texas Instruments Incorporated 9 LMZ10505EXT Input Capacitor Selection A 22 µF or 47 µF high quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum input voltage is typically sufficient. The input capacitor must be placed as close as possible to the VIN pin and GND exposed pad to substantially eliminate the parasitic effects of any stray inductance or resistance on the PC board and supply lines. Neglecting capacitor equivalent series resistance (ESR), the resultant input capacitor AC ripple voltage is a triangular waveform. The minimum input capacitance for a given peak-to-peak value (ΔVIN) of VIN is specified as follows: where the PWM duty cycle, D, is given by: If ΔVIN is 1% of VIN, this equals to 50 mV and fSW = 1 MHz A second criteria before finalizing the Cin bypass capacitor is the RMS current capability. The necessary RMS current rating of the input capacitor to a buck regulator can be estimated by With this high AC current present in the input capacitor, the RMS current rating becomes an important parameter. The maximum input capacitor ripple voltage and RMS current occur at 50% duty cycle. Select an input capacitor rated for at least the maximum calculated ICin(RMS). Additional bulk capacitance with higher ESR may be required to damp any resonance effects of the input capacitance and parasitic inductance. Output Capacitor Selection In general, 22 µF to 100 µF high quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum output voltage is sufficient given the optimal high frequency characteristics and low ESR of ceramic dielectrics. Although, the output capacitor can also be of electrolytic chemistry for increased capacitance density. Two output capacitance equations are required to determine the minimum output capacitance. One equation determines the output capacitance (CO) based on PWM ripple voltage. The second equation determines CO based on the load transient characteristics. Select the largest capacitance value of the two. The minimum capacitance, given the maximum output voltage ripple (ΔVOUT) requirement, is determined by the following equation: Where the peak to peak inductor current ripple (ΔiL) is equal to: RESR is the total output capacitor ESR, L is the inductance value of the internal power inductor, where L = 1.5 µH, and fSW = 1 MHz. Therefore, per the design example: 10 Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT The minimum output capacitance requirement due to the PWM ripple voltage is: Three miliohms is a typical RESR value for ceramic capacitors. The following equation provides a good first pass capacitance requirement for a load transient: Where Istep is the peak to peak load step (10% to 90% of the maximum load for this example), VFB = 0.8V, and ΔVo_tran is the maximum output voltage deviation, which is ±20 mV. Therefore the capacitance requirement for the given design parameters is: In this particular design the output capacitance is determined by the load transient requirements. Table 1 lists some examples of commercially available capacitors that can be used with the LMZ10505EXT. Copyright © 1999-2012, Texas Instruments Incorporated 11 LMZ10505EXT TABLE 1. Recommended Output Filter Capacitors CO (µF) Voltage (V), RESR (mΩ) Make Manufacturer Part Number Case Size 22 6.3, < 5 Ceramic, X5R TDK C3216X5R0J226M 1206 47 6.3, < 5 Ceramic, X5R TDK C3216X5R0J476M 1206 47 6.3, < 5 Ceramic, X5R TDK C3225X5R0J476M 1210 1210 47 10.0, < 5 Ceramic, X5R TDK C3225X5R1A476M 100 6.3, < 5 Ceramic, X5R TDK C3225X5R0J107M 1210 100 6.3, 50 Tantalum AVX TPSD157M006#0050 D, 7.5 x 4.3 x 2.9 mm 100 6.3, 25 Organic Polymer Sanyo 6TPE100MPB2 B2, 3.5 x 2.8 x 1.9 mm 150 6.3, 18 Organic Polymer Sanyo 6TPE150MIC2 C2, 6.0 x 3.2 x 1.8 mm 330 6.3, 18 Organic Polymer Sanyo 6TPE330MIL D3L, 7.3 x 4.3 x 2.8 mm 470 6.3, 23 Niobium Oxide AVX NOME37M006#0023 E, 7.3 x 4.3 x 4.1 mm Output Voltage Setting A resistor divider network from VOUT to the FB pin determines the desired output voltage as follows: Rfbt is defined based on the voltage loop requirements and Rfbb is then selected for the desired output voltage. Resistors are normally selected as 0.5% or 1% tolerance. Higher accuracy resistors such as 0.1% are also available. The feedback voltage (at VOUT = 2.5V) is accurate to within -2.5% / +2.5% over temperature and over line and load regulation. Additionally, the LMZ10505EXT contains error nulling circuitry to substantially eliminate the feedback voltage variation over temperature as well as the long term aging effects of the internal amplifiers. In addition the zero nulling circuit dramatically reduces the 1/f noise of the bandgap amplifier and reference. The manifestation of this circuit action is that the duty cycle will have two slightly different but distinct operating points, each evident every other switching cycle. Loop Compensation The LMZ10505EXT preserves flexibility by integrating the control components around the internal error amplifier while utilizing three small external compensation components from VOUT to FB. An integrated type II (two pole, one zero) voltage-mode compensation network is featured. To ensure stability, an external resistor and small value capacitor can be added across the upper feedback resistor as a pole-zero pair to complete a type III (three pole, two zero) compensation network. The compensation components recommended in Table 2 provide type III compensation at an optimal control loop performance. The typical phase margin is 45° with a bandwidth of 80 kHz. Calculated output capacitance values not listed in Table 2 should be verified before designing into production. A detailed application note is available to provide verification support, AN-2013. In general, calculated output capacitance values below the suggested value will have reduced phase margin and higher control loop bandwidth. Output capacitance values above the suggested values will experience a lower bandwidth and increased phase margin. Higher bandwidth is associated with faster system response to sudden changes such as load transients. Phase margin changes the characteristics of the response. Lower phase margin is associated with underdamped ringing and higher phase margin is associated with overdamped response. Losing all phase margin will cause the system to be unstable; an optimized area of operation is 30° to 60° of phase margin, with a bandwidth of 100 kHz ±20 kHz. 30118308 12 Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT TABLE 2. LMZ10505EXT Compensation Component Values VIN CO (µF) (V) 5.0 3.3 ESR (mΩ) Rfbt Min Max (kΩ) Ccomp (pF) Rcomp 22 2 20 200 27 1.5 47 2 20 124 56 1.4 100 1 10 82.5 120 1 150 1 5 63.4 180 1.21 150 10 25 63.4 220 16.5 150 26 50 44.2 220 23.7 220 15 30 63.4 220 23.7 220 31 60 76.8 220 57.6 22 2 20 118 39 9.09 47 2 20 76.8 82 8.45 100 1 10 49.9 180 4.12 150 1 5 40.2 330 2.0 150 10 25 43.2 330 11.5 150 26 50 49.9 270 25.5 220 15 30 40.2 390 15.4 220 31 60 48.7 330 35.7 (kΩ) Note: In the special case where the output voltage is 0.8V, it is recommended to remove Rfbb and keep Rfbt, Rcomp, and Ccomp for a type III compensation. Estimate Power Dissipation And Board Thermal Requirements Use the current derating curves in the typical performance characteristics section to obtain an estimate of power loss (PIC_LOSS). For the design case of VIN = 5V, VOUT = 2.5V, IOUT = 5A, TA(MAX) = 85°C , and TJ(MAX) = 125°C, the device must see a thermal resistance from case to ambient (θCA) of less than: Given the typical thermal resistance from junction to case (θJC) to be 1.9°C/W (typ.). Continuously operating at a TJ greater than 125°C will have a shorten life span. To reach θCA = 27.5°C/W, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a good estimate of the required board area covered by 1oz. copper on both the top and bottom metal layers is: As a result, approximately 18 square cm of 1oz. copper on top and bottom layers is required for the PCB design. The PCB copper heat sink must be connected to the exposed pad (EP). Approximately thirty six, 10mils (254 μm) thermal vias spaced 59mils (1.5 mm) apart must connect the top copper to the bottom copper. For an extended discussion and formulations of thermal rules of thumb, refer to AN-2020. For an example of a high thermal performance PCB layout with θJA of 20°C/W, refer to the evaluation board application note AN-2074 and for results of a study of the effects of the PCB designs, refer to AN-2026. PC Board Layout Guidelines PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. Copyright © 1999-2012, Texas Instruments Incorporated 13 LMZ10505EXT 30118353 FIGURE 1. High Current Loops 1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths. The high current that does not overlap contains high di/dt, see Figure 1. Therefore physically place input capacitor (Cin1) as close as possible to the LMZ10505EXT VIN pin and GND exposed pad to avoid observable high frequency noise on the output pin. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad (EP). 2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components should be routed only to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly placed, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP. 3. Minimize trace length to the FB pin. Both feedback resistors, Rfbt and Rfbb, and the compensation components, Rcomp and Ccomp, should be located close to the FB pin. Since the FB node is high impedance, keep the copper area as small as possible. This is most important as relatively high value resistors are used to set the output voltage. 4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made at the load. Doing so will correct for voltage drops and provide optimum output accuracy. 5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 x 6 via array with minimum via diameter of 10mils (254 μm) thermal vias spaced 59mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C. 14 Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT Additional Features ENABLE The LMZ10505EXT features an enable (EN) pin and associated comparator to allow the user to easily sequence the LMZ10505EXT from an external voltage rail, or to manually set the input UVLO threshold. The turn-on or rising threshold and hysteresis for this comparator are typically 1.23V and 0.15V respectively. The precise reference for the enable comparator allows the user to guarantee that the LMZ10505EXT will be disabled when the system demands it to be. The EN pin should not be left floating. For always-on operation, connect EN to VIN. ENABLE AND UVLO Using a resistor divider from VIN to EN as shown in the schematic diagram below, the input voltage at which the part begins switching can be increased above the normal input UVLO level according to For example, suppose that the required input UVLO level is 3.69V. Choosing Renb = 10 kΩ, then we calculate Rent = 20 kΩ. 30118344 Alternatively, the EN pin can be driven from another voltage source to cater to system sequencing requirements commonly found in FPGA and other multi-rail applications. The following schematic shows an LMZ10505EXT that is sequenced to start based on the voltage level of a master system rail (VOUT1). 30118345 SOFT-START The LMZ10505EXT begins to operate when both the VIN and EN, voltages exceed the rising UVLO and enable thresholds, respectively. A controlled soft-start eliminates inrush currents during startup and allows the user more control and flexibility when sequencing the LMZ10505EXT with other power supplies. In the event of either VIN or EN decreasing below the falling UVLO or enable threshold respectively, the voltage on the soft-start pin is collapsed by discharging the soft-start capacitor by a 14 µA (typ.) current sink to ground. SOFT-START CAPACITOR Determine the soft-start capacitance with the following relationship where VFB is the internal reference voltage (nominally 0.8V), ISS is the soft-start charging current (nominally 2 µA) and CSS is the external soft-start capacitance. Thus, the required soft-start capacitor per unit output voltage startup time is given by CSS = 2.5 nF / ms Copyright © 1999-2012, Texas Instruments Incorporated 15 LMZ10505EXT For example, a 4 ms soft-start time will yield a 10 nF capacitance. The minimum soft-start capacitance is 680 pF. TRACKING The LMZ10505EXT can track the output of a master power supply during soft-start by connecting a resistor divider to the SS pin. In this way, the output voltage slew rate of the LMZ10505EXT will be controlled by a master supply for loads that require precise sequencing. When the tracking function is used, a small value soft-start capacitor should be connected to the SS pin to alleviate output voltage overshoot when recovering from a current limit fault. 30118357 TRACKING - EQUAL SOFT-START TIME One way to use the tracking feature is to design the tracking resistor divider so that the master supply output voltage, VOUT1, and the LMZ10505EXT output voltage, VOUT2, both rise together and reach their target values at the same time. This is termed ratiometric startup. For this case, the equation governing the values of tracking divider resistors Rtrkb and Rtrkt is given by The above equation includes an offset voltage, of 200 mV, to ensure that the final value of the SS pin voltage exceeds the reference voltage of the LMZ10505EXT. This offset will cause the LMZ10505EXT output voltage to reach regulation slightly before the master supply. A value of 33 kΩ 1% is recommended for Rtrkt as a compromise between high precision and low quiescent current through the divider while minimizing the effect of the 2 µA soft-start current source. For example, if the master supply voltage VOUT1 is 3.3V and the LMZ10505EXT output voltage was 1.8V, then the value of Rtrkb needed to give the two supplies identical soft-start times would be 14.3 kΩ. A timing diagram for this example, the equal soft-start time case, is shown below. 30118359 TRACKING - EQUAL SLEW RATES Alternatively, the tracking feature can be used to have similar output voltage ramp rates. This is referred to as simultaneous startup. In this case, the tracking resistors can be determined based on the following equation and to ensure proper overdrive of the SS pin VOUT2 < 0.8 x V OUT1 16 Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT For the example case of VOUT1 = 5V and VOUT2 = 2.5V, with Rtrkt set to 33 kΩ as before, Rtrkb is calculated from the above equation to be 15.5 kΩ. A timing diagram for the case of equal slew rates is shown below. 30118361 PRE-BIAS STARTUP CAPABILITY At startup, the LMZ10505EXT is in a pre-biased state when the output voltage is greater than zero. This often occurs in many multirail applications such as when powering an ASIC, FPGA, or DSP. The output can be pre-biased in these applications through parasitic conduction paths from one supply rail to another. Even though the LMZ10505EXT is a synchronous converter, it will not pull the output low when a pre-bias condition exists. The LMZ10505EXT will not sink current during startup until the soft-start voltage exceeds the voltage on the FB pin. Since the device does not sink current it protects the load from damage that might otherwise occur if current is conducted through the parasitic paths of the load. CURRENT LIMIT When a current greater than the output current limit (IOCL) is sensed, the on-time is immediately terminated and the low side MOSFET is activated. The low side MOSFET stays on for the entire next four switching cycles. During these skipped pulses, the voltage on the soft-start pin is reduced by discharging the soft-start capacitor by a current sink on the soft-start pin of nominally 14 µA. Subsequent over-current events will drain more and more charge from the soft-start capacitor, effectively decreasing the reference voltage as the output droops due to the pulse skipping. Reactivation of the soft-start circuitry ensures that when the overcurrent situation is removed, the part will resume normal operation smoothly. OVER-TEMPERATURE PROTECTION When the LMZ10505EXT senses a junction temperature greater than 145°C (typ.), both switching MOSFETs are turned off and the part enters a standby state. Upon sensing a junction temperature below 135°C (typ.), the part will re-initiate the soft-start sequence and begin switching once again. Copyright © 1999-2012, Texas Instruments Incorporated 17 LMZ10505EXT LMZ10505EXT Application Circuit Schematic and BOMs This section provides several application solutions with an associated bill of materials. The compensation for each solution was optimized to work over the full input range. Many applications have a fixed input voltage rail. It is possible to modify the compensation to obtain a faster transient response for a given input voltage operating point. 30118354 FIGURE 2. TABLE 3. Bill of Materials, VIN = 3.3V to 5V, VOUT = 2.5V, IOUT (MAX) = 5A, Optimized for Electrolytic Input and Output Capacitance Designator Description Case Size Manufacturer Manufacturer P/N Quantity U1 SIMPLE SWITCHER ® TO-PMOD-7 National Semiconductor LMZ10505EXTTZ 1 Cin1 150 µF, 6.3V, 18 mΩ C2, 6.0 x 3.2 x 1.8 mm Sanyo 6TPE150MIC2 1 CO1 330 µF, 6.3V, 18 mΩ D3L, 7.3 x 4.3 x 2.8 mm Sanyo 6TPE330MIL 1 Rfbt 100 kΩ 0603 Vishay Dale CRCW0603100KFKEA 1 Rfbb 47.5 kΩ 0603 Vishay Dale CRCW060347K5FKEA 1 Rcomp 15 kΩ 0603 Vishay Dale CRCW060315K0FKEA 1 Ccomp 330 pF, ±5%, C0G, 50V 0603 TDK C1608C0G1H331J 1 CSS 10 nF, ±10%, X7R, 16V 0603 Murata GRM188R71C103KA01 1 TABLE 4. Bill of Materials, VIN = 3.3V, VOUT = 0.8V, IOUT (MAX) = 5A, Optimized for Solution Size and Transient Response Designator Description Case Size Manufacturer Manufacturer P/N Quantity U1 SIMPLE SWITCHER ® TO-PMOD-7 National Semiconductor LMZ10505EXTTZ 1 Cin1, CO1 47 µF, X5R, 6.3V 1206 TDK C3216X5R0J476M 2 Rfbt 110 kΩ 0402 Vishay Dale CRCW0402100KFKED 1 Rcomp 1.0 kΩ 0402 Vishay Dale CRCW04021K00FKED 1 Ccomp 27 pF, ±5%, C0G, 50V 0402 Murata GRM1555C1H270JZ01 1 CSS 10 nF, ±10%, X7R, 16V 0402 Murata GRM155R71C103KA01 1 In the case where the output voltage is 0.8V, it is recommended to remove Rfbb and keep Rfbt, Rcomp, and Ccomp for a type III compensation. 18 Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT 30118381 FIGURE 3. TABLE 5. Bill of Materials, VIN = 3.3V to 5V, VOUT = 2.5V, IOUT (MAX) = 5A, Optimized for Low Input and Output Ripple Voltage and Fast Transient Response Designator Description Case Size Manufacturer Manufacturer P/N Quantity U1 SIMPLE SWITCHER® TO-PMOD-7 National Semiconductor LMZ10505EXTTZ 1 Cin1 22 µF, X5R, 10V 1210 AVX 1210ZD226MAT 2 Cin2 220 µF, 10V, AL-Elec E Panasonic EEE1AA221AP 1* CO1 4.7 µF, X5R, 10V 0805 AVX 0805ZD475MAT 1* CO2 22 µF, X5R, 6.3V 1206 AVX 12066D226MAT 1* CO3 100 µF, X5R, 6.3V 1812 AVX 18126D107MAT 1 Rfbt 75 kΩ 0402 Vishay Dale CRCW040275K0FKED 1 Rfbb 34.8 kΩ 0402 Vishay Dale CRCW040234K8FKED 1 Rcomp 1.0 kΩ 0402 Vishay Dale CRCW04021K00FKED 1 Ccomp 100 pF, ±5%, C0G, 50V 0402 Murata GRM1555C1H101JZ01 1 CSS 10 nF, ±10%, X7R, 16V 0402 Murata GRM155R71C103KA01 1 * Optional components, include for low input and output voltage ripple. TABLE 6. Output Voltage Setting (Rfbt = 75 kΩ) VOUT Rfbb 2.5 V 34.8 kΩ 1.8 V 59 kΩ 1.5 V 84.5 kΩ 1.2 V 150 kΩ 0.9 V 590 kΩ Copyright © 1999-2012, Texas Instruments Incorporated 19 LMZ10505EXT 30118380 FIGURE 4. TABLE 7. Bill of Materials, VIN = 3.3V to 5V, VOUT = 2.5V, IOUT (MAX) = 5A Designator Description Case Size Manufacturer Manufacturer P/N Quantity U1 SIMPLE SWITCHER® TO-PMOD-7 National Semiconductor LMZ10505EXTTZ 1 Cin1 1 µF, X7R, 16V 0805 TDK C2012X7R1C105K 1 Cin2, CO1 4.7 µF, X5R, 6.3V 0805 TDK C2012X5R0J475K 2 Cin3, CO2 22 µF, X5R, 16V 1210 TDK C3225X5R1C226M 2 Cin4 47 µF, X5R, 6.3V 1210 TDK C3225X5R0J476M 1 Cin5 220 µF, 10V, AL-Elec E Panasonic EEE1AA221AP 1 CO3 100 µF, X5R, 6.3V 1812 TDK C4532X5R0J107M 1 Rfbt 75 kΩ 0805 Vishay Dale CRCW080575K0FKEA 1 Rfbb 34.8 kΩ 0805 Vishay Dale CRCW080534K8FKEA 1 Rcomp 1.1 kΩ 0805 Vishay Dale CRCW08051K10FKEA 1 Ccomp 180 pF, ±5%, C0G, 50V 0603 TDK C1608C0G1H181J 1 Ren1 100 kΩ 0805 Vishay Dale CRCW0805100KFKEA 1 CSS 10 nF, ±5%, C0G, 50V 0805 TDK C2012C0G1H103J 1 TABLE 8. Output Voltage Setting (Rfbt = 75 kΩ) 20 VOUT Rfbb 2.5 V 34.8 kΩ 1.8 V 59 kΩ 1.5 V 84.5 kΩ 1.2 V 150 kΩ 0.9 V 590 kΩ Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT 30118316 FIGURE 5. TABLE 9. Bill of Materials, VIN = 5V, VOUT = 2.5V, IOUT (MAX) = 5A, Complies with EN55022 Class B Radiated Emissions Designator Description Case Size Manufacturer Manufacturer P/N Quantity U1 SIMPLE SWITCHER® TO-PMOD-7 National Semiconductor LMZ10505EXTTZ 1 Cin1 1 µF, X7R, 16V 0805 TDK C2012X7R1C105K 1 Cin2 4.7 µF, X5R, 6.3V 0805 TDK C2012X5R0J475K 1 Cin3 47 µF, X5R, 6.3V 1210 TDK C3225X5R0J476M 1 CO1 100 µF, X5R, 6.3V 1812 TDK C4532X5R0J107M 1 Rfbt 75 kΩ 0805 Vishay Dale CRCW080575K0FKEA 1 Rfbb 34.8 kΩ 0805 Vishay Dale CRCW080534K8FKEA 1 Rcomp 1.1 kΩ 0805 Vishay Dale CRCW08051K10FKEA 1 Ccomp 180 pF, ±5%, C0G, 50V 0603 TDK C1608C0G1H181J 1 CSS 10 nF, ±5%, C0G, 50V 0805 TDK C2012C0G1H103J 1 TABLE 10. Output Voltage Setting (Rfbt = 75 kΩ) VOUT Rfbb 3.3 V 23.7 kΩ 2.5 V 34.8 kΩ 1.8 V 59 kΩ 1.5 V 84.5 kΩ 1.2 V 150 kΩ 0.9 V 590 kΩ Copyright © 1999-2012, Texas Instruments Incorporated 21 LMZ10505EXT PCB Layout Diagrams The PCB design is available in the LMZ10505EXT product folder at www.national.com. 30118376 FIGURE 6. Top Copper 22 Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT 30118377 FIGURE 7. Internal Layer 1 (Ground) 30118378 FIGURE 8. Internal Layer 2 (Ground and Signal Traces) Copyright © 1999-2012, Texas Instruments Incorporated 23 LMZ10505EXT 30118379 FIGURE 9. Bottom Copper 24 Copyright © 1999-2012, Texas Instruments Incorporated LMZ10505EXT Physical Dimensions inches (millimeters) unless otherwise noted TO-PMOD-7 Pin Package NS Package Number TZA07A Copyright © 1999-2012, Texas Instruments Incorporated 25 Notes Copyright © 1999-2012, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated