LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 15A High Efficiency Point of Load Synchronous Buck Regulator Check for Samples: LM21215 FEATURES APPLICATIONS • • 1 2 • • • • • • • • • • • Integrated 7.0 mΩ High Side and 4.3 mΩ Low Side FET Switches Adjustable Current Limit Adjustable Output Voltage From 0.6V to VIN (100% Duty Cycle Capable), ±1% Reference Input Voltage Range 2.95V to 5.5V 500 kHz Fixed Switching Frequency Startup Into Pre-Biased Loads Output Voltage Tracking Capability Wide Bandwidth Voltage Loop Error Amplifier Adjustable Soft-Start With External Capacitor Precision Enable Pin With Hysteresis Integrated OVP, OTP, UVLO and Power-Good Thermally Enhanced HTSSOP-20 Exposed Pad Package • • Broadband, Networking and Wireless Communications High-Performance FPGAs, ASICs and Microprocessors Simple to Design, High Efficiency Point of Load Regulation From a 5V or 3.3V Bus DESCRIPTION The LM21215 is a monolithic synchronous point of load buck regulator that is capable of delivering up to 15A of continuous output current while producing an output voltage down to 0.6V with outstanding efficiency. The device is optimized to work over an input voltage range of 2.95V to 5.5V, making it suited for a wide variety of low voltage systems. The voltage mode control loop provides high noise immunity, narrow duty cycle capability and can be compensated to be stable with any type of output capacitance, providing maximum flexibility and ease of use. Simplified Application Circuit HTSSOP-20 LOUT 5,6,7 VIN PVIN CIN SW 11-16 RF VOUT COUT 4 CC3 AVIN RFB1 CF 3 LM21215 FB EN optional optional COMP RC2 19 18 CC1 RC1 RFB2 2 SS/ TRK CSS CC2 17 1 PGOOD ILIM RILIM PGND AGND 8,9,10 20 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com DESCRIPTION (CONTINUED) The LM21215 features internal over voltage protection (OVP) and resistor-programmable over-current protection (OCP) for increased system reliability. A precision enable pin and integrated UVLO allow turn-on of the device to be tightly controlled and sequenced. Startup inrush currents are limited by both an internally fixed and externally adjustable soft-start circuit. Fault detection and supply sequencing are possible with the integrated power good circuit. The LM21215 is designed to work well in multi-rail power supply architectures. The output voltage of the device can be configured to track an external voltage rail using the SS/TRK pin. If the output is pre-biased at startup, it will not sink current, allowing the output to smoothly rise past the pre-biased voltage. The regulator is offered in a 20-pin HTSSOP package with an exposed pad that can be soldered to the PCB, eliminating the need for bulky heatsinks. Connection Diagram Top View 20 AGND ILIM 1 SS/TRK 2 19 FB 18 COMP EN 3 AVIN 4 17 PGOOD PVIN 5 16 SW PVIN 6 EP 15 SW PVIN 7 14 SW PGND 8 13 SW PGND 9 12 SW PGND 10 11 SW Figure 1. Top View HTSSOP-20 Package 2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 PIN DESCRIPTIONS Pins Name 1 ILIM Resistor-programmable current limit pin. A resistor connected to this pin and ground will set the value of the rising current limit ICLR. Shorting this pin to AGND will program the device to the maximum possible current limit. 2 SS/TRK Soft-start control pin. An internal 2µA current source charges an external capacitor connected between this pin and AGND to set the output voltage ramp rate during startup. This pin can also be used to configure the tracking feature. 3 EN Active high enable input for the device. If not used, the EN pin can be left open, which will go high due to an internal current source. 4 AVIN Analog input voltage supply that generates the internal bias. It is recommended to connect PVIN to AVIN through a low pass RC filter to minimize the influence of input rail ripple and noise on the analog control circuitry. 5,6,7 PVIN Input voltage to the power switches inside the device. These pins should be connected together at the device. A low ESR input capacitance should be located as close as possible to these pins. 8,9,10 PGND Power ground pins for the internal power switches. 11-16 SW 17 PGOOD 18 COMP 19 FB 20 AGND EP Exposed Pad Description Switch node pins. These pins should be tied together locally and connected to the filter inductor. Open-drain power good indicator. Compensation pin is connected to the output of the voltage loop error amplifier. Feedback pin is connected to the inverting input of the voltage loop error amplifier. Quiet analog ground for the internal reference and bias circuitry. Exposed metal pad on the underside of the package with an electrical and thermal connection to PGND. It is recommended to connect this pad to the PC board ground plane in order to improve thermal dissipation. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings PVIN (1) (2) (3) −0.3V to +6V , AVIN to GND SW (4), EN, FB, COMP, PGOOD, SS/TRK to GND −0.3V to PVIN + 0.3V −65°C to 150°C Storage Temperature Lead Temperature (Soldering, 10 sec.) 260°C ESD Rating, Human Body Model (5) (1) (2) (3) (4) (5) ±2kV Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The PVIN pin can tolerate transient voltages up to 6.5 V for a period of up to 6ns. These transients can occur during the normal operation of the device. The SW pin can tolerate transient voltages up to 9.0 V for a period of up to 6ns, and -1.0V for a duration of 4ns. These transients can occur during the normal operation of the device. The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin. Operating Ratings (1) PVIN, AVIN to GND +2.95V to +5.5V −40°C to +125°C Junction Temperature θJA (2) (1) (2) 24°C/W Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. Thermal measurements were performed on a 2x2 inch, 4 layer, 2 oz. copper outer layer, 1 oz.copper inner layer board with twelve 8 mil. vias underneith the EP of the device and an additional sixteen 8 mil. vias under the unexposed package. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 3 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Electrical Characteristics Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of −40°C to +125°C. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions Min Feedback pin voltage VIN = 2.95V to 5.5V -1% Typ Max 0.6 1% Units SYSTEM VFB ΔVOUT/ΔIOUT Load Regulation ΔVOUT/ΔVIN 0.02 Line Regulation V %VOUT/A 0.1 %VOUT/V RDSON HS High Side Switch On Resistance ISW = 12A 7 9.0 mΩ RDSON LS Low Side Switch On Resistance ISW = 12A 4.3 6.0 mΩ ICLR HS Rising Switch Current Limit RILIM = 16.5 kΩ 16.5 20 23.5 A RILIM = 41.3 kΩ 8.5 10 11.5 ICLF LS Falling Switch Current Limit RILIM = 130 kΩ 3.8 RILIM = 16.5 kΩ 14.5 RILIM = 41.3 kΩ 7.5 RILIM = 130 kΩ VZX -8 12 mV 1.5 3 mA 50 70 µA 2.45 2.7 2.95 V 140 200 280 mV -10 6 20 mV 1.3 1.9 2.5 µA 350 500 675 µs Device reset to soft-start ramp 50 110 200 µs Switching Frequency 475 500 525 kHz IQ Operating Quiescent Current Shutdown Quiescent Current VEN = 0V VUVLO AVIN Under Voltage Lockout AVIN Rising VUVLOHYS AVIN Under Voltage Lockout Hysteresis VTRACKOS SS/TRACK PIN accuracy (VSS - VFB) tINTSS tRESETSS 3 Zero Cross Voltage ISD ISS A 0 < VTRACK < 0.55V Soft-Start Pin Source Current Internal Soft-Start Ramp to Vref CSS = 0 3 OSCILLATOR fOSC tHSBLANK HS OCP blanking time Rising edge of SW to ICLR comparison 55 ns tLSBLANK LS OCP blanking time Falling edge of SW to ICLF comparison 400 ns tZXBLANK Zero Cross blanking time Falling edge of SW to VZX comparison 120 ns Minimum HS on-time 140 ns PWM Ramp p-p Voltage 0.8 V 95 dBV/V 11 MHz tMINON ΔVRAMP ERROR AMPLIFIER VOL Error Amplifier Open Loop Voltage Gain GBW Error Amplifier Gain-Bandwidth Product IFB Feedback Pin Bias Current ICOMP = -65µA to 1mA VFB = 0.6V 1 nA ICOMPSRC COMP Output Source Current 1 mA ICOMPSINK COMP Output Sink Current 65 µA POWERGOOD VOVP VOVPHYS VUVP VUVPHYS 4 Over Voltage Protection Rising Threshold VFB Rising Over Voltage Protection Hysteresis VFB Falling Under Voltage Protection Rising Threshold VFB Rising Under Voltage Protection Hysteresis VFB Falling 105 112.5 120 2 82 90 %VFB %VFB 97 %VFB 2.5 %VFB tPGDGL PGOOD Deglitch Low (OVP/UVP Condition Duration to PGOOD Falling) 15 µs tPGDGH PGOOD Deglitch High (minimum low pulse) 12 µs Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 Electrical Characteristics (continued) Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of −40°C to +125°C. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions Min Typ Max 10 20 40 Units SYSTEM RPD IPGOODLEAK PGOOD Pull-down Resistance PGOOD Leakage Current VPGOOD = 5V VIHENR EN Pin Rising Threshold VEN Rising VENHYS EN Pin Hysteresis 1 Ω nA LOGIC IEN EN Pin Pullup Current VEN = 0V 1.20 1.35 1.45 V 50 110 180 mV 2 µA 165 °C 10 °C THERMAL SHUTDOWN TTHERMSD Thermal Shutdown TTHERMSDHYS Thermal Shutdown Hysteresis Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 5 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified: VIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency 100 Efficiency (VOUT = 3.3 V, Inductor P/N SER2010-02MLD) 100 VIN = 3.3V VIN = 5.0V 98 99 98 EFFICIENCY (%) 94 92 90 88 86 97 96 95 94 93 84 92 82 91 80 90 0 3 6 9 12 OUTPUT CURRENT (A) 15 VIN = 4.0V VIN = 5.5V 0 3 6 9 12 OUTPUT CURRENT (A) Figure 2. Figure 3. Line Regulation 0.10 0.03 0.08 û OUTPUT VOLTAGE (%) û OUTPUT VOLTAGE (%) Load Regulation 0.04 0.02 0.01 0.00 -0.01 -0.02 VIN = 3.3V VIN = 5.0V -0.03 2 4 6 8 10 OUTPUT CURRENT (A) 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 IOUT = 0A IOUT = 12A -0.08 -0.04 0 -0.10 3.0 12 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) Figure 4. Non-Switching IQTOTAL vs. VIN Non-Switching IAVIN and IPVIN vs. Temperature 1.20 1.17 IAVIN(mA) IPVIN+ IAVIN(mA) 1.4 1.3 1.2 1.1 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 0.180 IAVIN IPVIN 0.172 1.14 0.164 1.11 0.156 1.08 0.148 1.05 0.140 1.02 0.132 0.99 0.124 0.96 0.116 0.93 0.108 0.100 0.90 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) Figure 6. 6 5.5 Figure 5. 1.5 1.0 3.0 15 IPVIN(mA) EFFICIENCY (%) 96 Figure 7. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified: VIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Enable Threshold and Hysteresis vs. Temperature VFB(V) VIHENR(V) 0.601 0.600 0.599 0.598 144 1.35 136 1.34 128 1.33 120 1.32 112 1.31 104 1.30 96 1.29 88 1.28 80 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) Figure 8. Figure 9. UVLO Threshold and Hysteresis vs. Temperature 60 285 58 2.76 270 2.74 255 2.72 240 2.70 225 2.68 210 2.66 195 2.64 180 2.62 165 2.60 150 ENABLE LOW CURRENT ( A) VUVLO(V) Enable Low Current vs. Temperature 300 VUVLOHYS(mV) V UVLO V UVLOHYS 2.78 152 1.36 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) 2.80 160 V IHENR V ENHYS 1.37 VENHYS(V) VFB vs. Temperature 0.602 56 54 52 50 48 46 44 42 40 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) Figure 10. Figure 11. OVP/UVP Threshold vs. Temperature Minimum On-Time vs. Temperature 160 156 0.68 VUVP VOVP MINIMUM ON-TIME (nS) VOVP,VUVP(V) 0.66 0.64 0.62 0.60 0.58 0.57 0.54 152 148 144 140 136 132 128 124 0.52 0.50 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) Figure 12. 120 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) Figure 13. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 7 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: VIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. FET Resistance vs. Temperature 10 LOW SIDE HIGH SIDE 9 8 10 7 9 6 8 5 7 4 6 3 5 2 4 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) 3.5 4.0 4.5 VIN(V) 5.0 Peak Current Limit (ICLR) vs. VIN Peak Current Limit (ICLR) vs. Temperature RILIM = 10 kΩ 23.0 RILIM = 24.9k RILIM = 16.5k CURRENT LIMIT (A) 19 18 17 16 15 22.0 21.5 21.0 20.5 20.0 19.5 14 3.0 VIN = 3.3V VIN = 5.5V 22.5 20 19.0 3.5 4.0 4.5 VIN(V) 5.0 5.5 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) Figure 16. Figure 17. Peak Current Limit (ICLR) vs. Temperature RILIM = 61.9 kΩ Load Transient Response 8.0 5.5 Figure 15. 21 ICLR(A) 3.0 Figure 14. 22 VIN = 3.3V VIN = 5.5V VOUT (50 mV/Div) 7.8 CURRENT LIMIT (A) RILIM = 41.2k RILIM = 74.9k 11 ICLR(A) RDSON(m ) Peak Current Limit (ICLR) vs. VIN 12 7.6 7.4 7.2 IOUT (10A/Div) 7.0 6.8 6.6 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) 8 Submit Documentation Feedback 100 µs/DIV Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified: VIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Figure 18. Figure 19. Output Voltage Ripple (IOUT = 15A) Startup with Prebiased Output VOUT (500 mV/Div) VOUT (10 mV/Div) VPGOOD (5V/Div) VENABLE (5V/Div) 2 ms/DIV 2 µs/DIV Figure 20. Figure 21. Startup with SS/TRK Open Circuit Startup with applied Track Signal VOUT (500 mV/Div) VOUT (500 mV/Div) VPGOOD (5V/Div) VTRACK (500 mV/Div) VENABLE (5V/Div) VPGOOD (5V/Div) IOUT (10A/Div) IOUT (10A/Div) 200 µs/DIV 200 ms/DIV Figure 23. Figure 22. Output Over-Current Condition (RILIM = 20 kΩ) VPGOOD (5V/Div) VOUT (1V/Div) IL (10A/Div) 100 µs/DIV Figure 24. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 9 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Block Diagram CURRENT LIMIT ILIM Ilimit high VREF AVIN PVIN Over temp + - PVIN UVLO 2.7V + - SD OR Driver Precision enable AVIN 1.35V + - EN Control Logic PWM comparator Zero-cross AVIN OSC RAMP + - + - PWM SW INT SS PVIN + SS/TRK 0.6V EA Driver FB OVP COMP 0.68V 0.54V + - Ilimit low OR Powerbad + - PGND UVP AGND OR PGOOD Operation Description GENERAL The LM21215 switching regulator features all of the functions necessary to implement an efficient low voltage buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 15A of continuous output current. The regulator utilizes voltage mode control with trailing edge modulation to optimize stability and transient response over the entire output voltage range. The device can operate at high switching frequency allowing use of a small inductor while still achieving high efficiency. The precision internal voltage reference allows the output to be set as low as 0.6V. Fault protection features include: current limiting, thermal shutdown, over voltage protection, and shutdown capability. The device is available in the HTSSOP-20 package featuring an exposed pad to aid thermal dissipation. The LM21215 can be used in numerous applications to efficiently step-down from a 5V or 3.3V bus. PRECISION ENABLE The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.35V (typical). The EN pin has 110 mV of hysteresis and will disable the output when the enable voltage falls below 1.24V (typical). If the EN pin is not used, it can be left open, and will be pulled high by an internal 2 µA current source. Since the enable pin has a precise turn-on threshold it can be used along with an external resistor divider network from VIN to configure the device to turn-on at a precise input voltage. 10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 UVLO The LM21215 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the input voltage reaches 2.7V (typical). The UVLO threshold has 200 mV of hysteresis that keeps the device from responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed by using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 29 in the design guide. CURRENT LIMIT The LM21215 has programmable current limit protection to avoid dangerous current levels through the power FETs and inductor. A current limit condition is met when the current through the high side FET exceeds the rising current limit level (ICLR). The control circuitry will respond to this event by turning off the high side FET and turning on the low side FET. This forces a negative voltage on the inductor, thereby causing the inductor current to decrease. The high side FET will not conduct again until the lower current limit level (ICLF) is sensed on the low side FET. At this point, the device will resume normal switching. A current limit condition will cause the internal soft-start voltage to ramp downward. After the internal soft-start ramps below the Feedback (FB) pin voltage, (nominally 0.6 V), FB will begin to ramp downward, as well. This voltage foldback will limit the power consumption in the device, thereby protecting the device from continuously supplying power to the load under a condition that does not fall within the device SOA. After the current limit condition is cleared, the internal soft-start voltage will ramp up again. Figure 25 shows current limit behavior with VSS, VFB, VOUT and VSW. SHORT-CIRCUIT PROTECTION In the unfortunate event that the output is shorted with a low impedance to ground, the LM21215 will limit the current into the short by resetting the device. A short-circuit condition is sensed by a current-limit condition coinciding with a voltage on the FB pin that is lower than 100 mV. When this condition occurs, the device will begin its reset sequence, turning off both power FETs and discharging the soft-start capacitor after tRESETSS (nominally 110 µs). The device will then attempt to restart. If the short-circuit condition still exists, it will reset again, and repeat until the short-circuit is cleared. The reset prevents excess current flowing through the FETs in a highly inefficient manner, potentially causing thermal damage to the device or the bus supply. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 11 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Iclr IL Iclf VSS VFB 100 mV VOUT VSW CURRENT LIMIT SHORT-CIRCUIT REMOVED SHORT-CIRCUIT Figure 25. Current Limit Conditions THERMAL PROTECTION Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 165°C, the LM21215 tri-states the power FETs and resets soft start. After the junction cools to approximately 155°C, the device starts up using the normal start up routine. This feature is provided to prevent catastrophic failures from accidental device overheating. Note that thermal limit will not stop the die from operating above the specified maximum operating temperature,125°C. The die should be kept under 125°C to ensure correct operation. POWER GOOD FLAG The PGOOD pin provides the user with a way to monitor the status of the LM21215. In order to use the PGOOD pin, the application must provide a pull-up resistor to a desired DC voltage (i.e. Vin). PGOOD will respond to a fault condition by pulling the PGOOD pin low with the open-drain output. PGOOD will pull low on the following conditions: 1) VFB moves above or below the VOVP or VUVP, respectively 2) The enable pin (EN) is brought below the enable threshold 3) The device enters a pre-biased output condition (VFB>VSS). Figure 26 shows the conditions that will cause PGOOD to fall. 12 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 t RESETSS V ss 0.6V Vovp VOVPHYS VFB Vuvp VUVPHYS VEN V PGOOD V SW OVP UVP DISABLE tPGDGL PRE-BIASED STARTUP t PGDGH Figure 26. PGOOD Conditions LIGHT LOAD OPERATION The LM21215 offers increased efficiency when operating at light loads. Whenever the load current is reduced to a point where the peak to peak inductor ripple current is greater than two times the load current, the device will enter the diode emulation mode preventing significant negative inductor current. The point at which this occurs is the critical conduction boundary and can be calculated by the following equation: IBOUNDARY = (VIN ± VOUT) x D 2 x L x fSW (1) Several diagrams are shown in Figure 27 illustrating continuous conduction mode (CCM), discontinuous conduction mode (DCM), and the boundary condition. It can be seen that in diode emulation mode, whenever the inductor current reaches zero the SW node will become high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor and the parasitic capacitance at the node. If this ringing is of concern an additional RC snubber circuit can be added from the switch node to ground. At very light loads, usually below 100mA, several pulses may be skipped in between switching cycles, effectively reducing the switching frequency and further improving light-load efficiency. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 13 LM21215 Switchnode Voltage SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Continuous Conduction Mode (CCM) VIN Time (s) Inductor Current Continuous Conduction Mode (CCM) IAVERAGE Inductor Current Time (s) DCM - CCM Boundary IAVERAGE Switchnode Voltage Time (s) Discontinuous Conduction Mode (DCM) VIN Inductor Current Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Figure 27. Modes of Operation for LM21215 14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 DESIGN GUIDE OUTPUT VOLTAGE The first step in designing the LM21215 application is setting the output voltage. This is done by using a voltage divider between VOUT and AGND, with the middle node connected to VFB . When operating under steady-state conditions, the LM21215 will force VOUT such that VFB is driven to 0.6 V. VOUT LM21215 RFB1 0.6V FB RFB2 Figure 28. Setting VOUT A good starting point for the lower feedback resistor, RFB2, is 10 kΩ. RFB1 can then be calculated with the following equation: VOUT = RFB1 + RFB2 0.6V RFB2 (2) PRECISION ENABLE The enable (EN) pin of the LM21215 allows the output to be toggled on and off. This pin is a precision analog input. When the voltage exceeds 1.35V, the controller will try to regulate the output voltage as long as the input voltage has exceeded the UVLO voltage of 2.70V. There is an internal current source connected to EN so if enable is not used, the device will turn on automatically. If EN is not toggled directly the device can be preprogrammed to turn on at a certain input voltage higher than the UVLO voltage. This can be done with an external resistor divider from AVIN to EN and EN to AGND as shown below in Figure 29. Input Power Supply RA AVIN LM21215 EN VOUT RB Figure 29. Enable Startup Through Vin The resistor values of RA and RB can be relatively sized to allow EN to reach the enable threshold voltage depending on the input supply voltage. With the enable current source accounted for, the equation solving for RA is shown below: RB VPVIN - 1.35V RA = 1.35V - IENRB (3) In the above equation, RA is the resistor from VIN to enable, RB is the resistor from enable to ground, IEN is the internal enable pull-up current (2 µA) and 1.35V is the fixed precision enable threshold voltage. Typical values for RB range from 10 kΩ to 100 kΩ. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 15 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com SOFT START When EN has exceeded 1.35V, and both PVIN and AVIN have exceeded the UVLO threshold, the LM21215 will begin charging the output linearly to the voltage level dictated by the feedback resistor network. The LM21215 employs a user adjustable soft start circuit to lengthen the charging time of the output set by a capacitor from the soft start pin to ground. After enable exceeds 1.35V, an internal 2 µA current source begins to charge the soft start capacitor. This allows the user to limit inrush currents due to a high output capacitance and not cause an over current condition. Adding a soft-start capacitor can also reduce the stress on the input rail. Larger capacitor values will result in longer startup times. Use the equation below to approximate the size of the soft-start capacitor: tSS x ISS = CSS 0.6V where • • ISS is nominally 2 µA tSS is the desired startup time (4) If VIN is higher than the UVLO level and enable is toggled high the soft start sequence will begin. There is a small delay between enable transitioning high and the beginning of the soft start sequence. This delay allows the LM21215 to initialize its internal circuitry. Once the output has charged to 90% of the nominal output voltage the power good flag will transition high. This behavior is illustrated in Figure 30. Voltage 90% VOUT (VUVP) VOUT Enable Delay (tRESETSS) 0V VEN VPGOOD Soft Start Time (tss) Time Figure 30. Soft Start Timing As shown above, the size of the capacitor is influenced by the nominal feedback voltage level 0.6V, the soft-start charging current ISS (2 µA), and the desired soft start time. If no soft-start capacitor is used then the LM21215 defaults to a minimum startup time of 500 µs. The LM21215 will not startup faster than 500µs. When enable is cycled or the device enters UVLO, the charge developed on the soft-start capacitor is discharged to reset the startup process. This also happens when the device enters short circuit mode from an over-current event. INDUCTOR SELECTION The inductor (L) used in the application will influence the ripple current and the efficiency of the system. The first selection criteria is to define a ripple current, ΔIL. In a buck converter, it is typically selected to run between 20% to 30% of the maximum output current. Figure 31 shows the ripple current in a standard buck converter operating in continuous conduction mode. Larger ripple current will result in a smaller inductance value, which will lead to a lower series resistance in the inductor, and improved efficiency. However, larger ripple current will also cause the device to operate in discontinuous conduction mode at a higher average output current. 16 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 VSW VIN Time IL IL AVG = IOUT 'IL Time Figure 31. Switch and Inductor Current Waveforms Once the ripple current has been determined, the appropriate inductor size can be calculated using the following equation: L= (VIN ± VOUT) D üIL fSW (5) OUTPUT CAPACITOR SELECTION The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM21215 that provide various advantages. The best performance is typically obtained using ceramic, SP or OSCON type chemistries. Typical trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes, while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading conditions. When selecting the value for the output capacitor, the two performance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple can be approximated by using the following formula: 'VOUT 'IL x RESR + 1 8 x fSW x COUT where • • • • ΔVOUT (V) is the amount of peak to peak voltage ripple at the power supply output RESR (Ω) is the series resistance of the output capacitor fSW (Hz) is the switching frequency COUT (F) is the output capacitance used in the design (6) The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also affect the output voltage droop during a load transient. The peak droop on the output voltage during a load transient is dependent on many factors; however, an approximation of the transient droop ignoring loop bandwidth can be obtained using the following equation: Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 17 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 VDROOP = 'IOUTSTEP x RESR + www.ti.com L x 'IOUTSTEP2 COUT x (VIN - VOUT) where • • • • • • • COUT (F) is the minimum required output capacitance L (H) is the value of the inductor VDROOP (V) is the output voltage drop ignoring loop bandwidth considerations ΔIOUTSTEP (A) is the load step change RESR (Ω) is the output capacitor ESR VIN (V) is the input voltage VOUT (V) is the set regulator output voltage (7) Both the tolerance and voltage coefficient of the capacitor should be examined when designing for a specific output ripple or transient droop target. INPUT CAPACITOR SELECTION Quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. Additionally, they help minimize input voltage droop in an output current transient condition. In general, it is recommended to use a ceramic capacitor for the input as it provides both a low impedance and small footprint. Use of a high grade dielectric for the ceramic capacitor, such as X5R or X7R, will provide improved over-temperature performance and also minimize the DC voltage derating that occurs with Y5V capacitors. The input capacitors CIN1 and CIN2 should be placed as close as possible to the PVIN and PGND pins. Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating is given by the relationship: IIN-RMS = IOUT D(1 - D) (8) As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device. When operating at low input voltages (3.3V or lower), additional capacitance may be necessary to protect from triggering an under-voltage condition on an output current transient. This will depend on the impedance between the input voltage supply and the LM21215, as well as the magnitude and slew rate of the output transient. The AVIN pin requires a 1 µF ceramic capacitor to AGND and a 1Ω resistor to PVIN. This RC network will filter inherent noise on PVIN from the sensitive analog circuitry connected to AVIN. PROGRAMMABLE CURRENT LIMIT A resisitor from the ILIM pin to GND will set the internal current limit on the LM21215. The current limit should be programmed such that the peak inductor current (IL) does not trigger the current limit in normal operation. This requires setting the resistor from the ILIM pin to GND (RILIM) to the appropriate value to allow the maximum ripple current, ΔILMAX plus the DC output current through the high-side FET during normal operation. The maximum ripple current can be described as: For D > 0.5 'ILMAX = (VINMAX - VOUTMIN) VOUTMIN LMIN fSWMIN VINMAX For D < 0.5 'ILMAX = 18 (VINMIN - VOUTMAX) VOUTMAX LMIN fSWMIN VINMIN Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 where • VINMAX, VINMIN, VOUTMAX, VOUTMIN, LMIN and FSWMIN are the respective maximum and minimum conditions of the system as defined by the component tolerance and device variation (9) From this, the maximum allowable current through the high-side FET (IHSMAX) of device can be described as: 'ILMAX + IDCMAX IHSMAX = 2 where • • IOUTMAX is the maximum defined DC output current, up to 15 A (10) Once the IHSMAX value has been determined, a nominal value of the RILIMresistor can be calculated as follows: 582.4 - 14.2 RILIM (k:) = IHSMAX where • RILIMvalue is the nominal resistance necessary for the given IHSMAX value (11) A conservative design should also take into account the device variation over VIN and temperature, as seen in the Electrical Characteristics table for the ICLR parameter and the typical performance characteristics. These variations can cause the IHSMAX value to increase, depending on the range of the input voltage and junction temperature. CONTROL LOOP COMPENSATION The LM21215 incorporates a high bandwidth amplifier between the FB and COMP pins to allow the user to design a compensation network that matches the application. This section will walk through the various steps in obtaining the open loop transfer function. There are three main blocks of a voltage mode buck switcher that the power supply designer must consider when designing the control system; the power train, modulator, and the compensated error amplifier. A closed loop diagram is shown in Figure 32. Power Train PWM Modulator VIN RDCR LOUT DRIVER VOUT SW RESR RO COUT PWM + Error Amplifier and Compensation COMP + EA - CC1 RC1 0.6V FB RFB1 RC2 C C3 RFB2 CC2 Figure 32. Loop Diagram The power train consists of the output inductor (L) with DCR (DC resistance RDCR), output capacitor (C0) with ESR (effective series resistance RESR), and load resistance (Ro). The error amplifier (EA) constantly forces FB to 0.6V. The passive compensation components around the error amplifier help maintain system stability. The modulator creates the duty cycle by comparing the error amplifier signal with an internally generated ramp set at the switching frequency. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 19 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com There are three transfer functions that must be taken into consideration when obtaining the total open loop transfer function; COMP to SW (Modulator) , SW to VOUT (Power Train), and VOUT to COMP (Error Amplifier). The COMP to SW transfer function is simply the gain of the PWM modulator. V GPWM = üVinramp where • ΔVRAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8 V) (12) The SW to COMP transfer function includes the output inductor, output capacitor, and output load resistance. The inductor and capacitor create two complex poles at a frequency described by: fLC = RO + RDCR 1 2S LOUTCOUT(RO + RESR) (13) In addition to two complex poles, a left half plane zero is created by the output capacitor ESR located at a frequency described by: fesr = 1 2SCoResr (14) A Bode plot showing the power train response can be seen below. 60 0 -40 40 GAIN (dB) -120 0 -160 -20 -200 PHASE (°) -80 20 -240 -40 -280 -60 GAIN PHASE -80 100 1k 10k 100k 1M FREQUENCY (HZ) -320 -360 10M Figure 33. Power Train Bode Plot The complex poles created by the output inductor and capacitor cause a 180° phase shift at the resonant frequency as seen in Figure 33. The phase is boosted back up to -90° due to the output capacitor ESR zero. The 180° phase shift must be compensated out and phase boosted through the error amplifier to stabilize the closed loop response. The compensation network shown around the error amplifier in Figure 32 creates two poles, two zeros and a pole at the origin. Placing these poles and zeros at the correct frequencies will stabilize the closed loop response. The Compensated Error Amplifier transfer function is: s s +1 +1 2SfZ1 2SfZ2 GEA = Km s s s +1 +1 2SfP1 2SfP2 (15) The pole located at the origin gives high open loop gain at DC, translating into improved load regulation accuracy. This pole occurs at a very low frequency due to the limited gain of the error amplifier, however, it can be approximated at DC for the purposes of compensation. The other two poles and two zeros can be located accordingly to stabilize the voltage mode loop depending on the power stage complex poles and Q. Figure 34 is an illustration of what the Error Amplifier Compensation transfer function will look like. 20 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 GAIN (dB) 100 GAIN PHASE 90 80 45 60 0 40 -45 20 -90 0 -135 -20 -180 100 1k 10k 100k 1M FREQUENCY (Hz) PHASE (°) www.ti.com 10M Figure 34. Type 3 Compensation Network Bode Plot As seen in Figure 34, the two zeros (fLC/2, fLC) in the comensation network give a phase boost. This will cancel out the effects of the phase loss from the output filter. The compensation network also adds two poles to the system. One pole should be located at the zero caused by the output capacitor ESR (fESR) and the other pole should be at half the switching frequency (fSW/2) to roll off the high frequency response. The dependancy of the pole and zero locations on the compensation components is described below. fLC 1 fZ1 = 2 = 2SR C C1 C1 1 fZ2 = fLC = 2S(R + R )C C1 FB1 C3 fP1 = fESR = fP2 = fsw 1 2SRC2CC3 CC1 + CC2 = 2SR C C 2 C1 C1 C2 (16) An example of the step-by-step procedure to generate comensation component values using the typical application setup, (see Figure 39), is given. The parameters needed for the compensation values are given in the table below. Parameter Value VIN 5.0V VOUT 1.2V IOUT 15A fCROSSOVER 100 kHz L 0.56 µH RDCR 1.8 mΩ CO 150 µF RESR 1.0 mΩ ΔVRAMP 0.8V fSW 500 kHz where ΔVRAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8V), and fCROSSOVER is the frequency at which the open-loop gain is a magnitude of 1. It is recommended that the fCROSSOVER not exceed one-fifth of the switching frequency. The output capacitance, CO, depends on capacitor chemistry and bias voltage. For MultiLayer Ceramic Capacitors (MLCC), the total capacitance will degrade as the DC bias voltage is increased. Measuring the actual capacitance value for the output capacitors at the output voltage is recommended to Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 21 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com accurately calculate the compensation network. The example given here is the total output capacitance using the three MLCC output capacitors biased at 1.2V, as seen in the typical application schematic, Figure 39. Note that it is more conservative, from a stability standpoint, to err on the side of a smaller output capacitance value in the compensation calculations rather than a larger, as this will result in a lower bandwidth but increased phase margin. First, a the value of RFB1 should be chosen. A typical value is 10 kΩ. From this, the value of RC1 can be calculated to set the mid-band gain so that the desired crossover frequency is achieved: RC1 = fcrossover 'VRAMP fLC VIN RFB1 100 kHz 0.8 V 10 k: 17.4 kHz 5.0 V = 9.2 k: = (17) Next, the value of CC1 can be calculated by placing a zero at half of the LC double pole frequency (fLC): CC1 = 1 SfLCRC1 = 1.99 nF (18) Now the value of CC2 can be calculated to place a pole at half of the switching frequency (fSW): CC2 = CC1 SfSWRC1 CC1 -1 = 71 pF (19) RC2 can then be calculated to set the second zero at the LC double pole frequency: RFB1 fLC RC2 = fESR - fLC = 166: (20) Last, CC3 can be calculated to place a pole at the same frequency as the zero created by the output capacitor ESR: 1 CC3 = 2SfESRRC2 = 898 pF (21) An illustration of the total loop response can be seen in Figure 35. 200 GAIN PHASE 150 160 140 GAIN (dB) 100 100 80 60 50 40 20 0 PHASE MARGIN (°) 120 0 -20 -50 -40 10 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 35. Loop Response 22 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 It is important to verify the stability by either observing the load transient response or by using a network analyzer. A phase margin between 45° and 70° is usually desired for voltage mode systems. Excessive phase margin can cause slow system response to load transients and low phase margin may cause an oscillatory load transient response. If the load step response peak deviation is larger than desired, increasing fCROSSOVER and recalculating the compensation components may help but usually at the expense of phase margin. THERMAL CONSIDERATIONS The thermal characteristics of the LM21215 are specified using the parameter θJA, which relates the junction temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PD TJA + TA (22) and PD = PIN (1 - Efficiency) - IOUT2 RDCR where • • • • • TJ is the junction temperature in °C PIN is the input power in Watts (PIN = VIN x IIN) θJA is the junction to ambient thermal resistance for the LM21215 TA is the ambient temperature in °C IOUT is the output load current in A (23) It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the junction temperature exceeds 165°C the device will cycle in and out of thermal shutdown. If thermal shutdown occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device. Figure 36, shown below, provides a better approximation of the θJA for a given PCB copper area. The PCB used in this test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were plated to 2oz. copper weight. To provide an optimal thermal connection, a 3 x 5 array of 8 mil. vias under the thermal pad were used, and an additional twelve 8 mil. vias under the rest of the device were used to connect the 4 layers. THERMAL RESISTANCE ( JA) 30 28 26 24 22 20 18 16 14 12 10 2 3 4 5 6 7 8 2 BOARD AREA (in ) 9 10 Figure 36. Thermal Resistance vs PCB Area (4 Layer Board) Figure 37 shows a plot of the maximum ambient temperature vs. output current for the typical application circuit shown in Figure 39, assuming a θJA value of 24 °C/W. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 23 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com MAX. AMBIENT TEMERATURE (°C) 125 120 115 110 105 100 95 90 85 80 0 3 6 9 12 OUTPUT CURRENT (A) 15 Figure 37. Maximum Ambient Temperature vs. Output Current (0 LFM) PCB LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched at high slew rates. The first loop starts from the input capacitor, to the regulator PVIN pin, to the regulator SW pin, to the inductor then out to the output capacitor and load. The second loop starts from the output capacitor ground, to the regulator GND pins, to the inductor and then out to the load (see Figure 38). To minimize both loop areas, the input capacitor should be placed as close as possible to the VIN pin. Grounding for both the input and output capacitor should be close. Ideally, a ground plane should be placed on the top layer that connects the PGND pins, the exposed pad (EP) of the device, and the ground connections of the input and output capacitors in a small area near pin 10 and 11 of the device. The inductor should be placed as close as possible to the SW pin and output capacitor. 2. Minimize the copper area of the switch node. The six SW pins should be routed on a single top plane to the pad of the inductor. The inductor should be placed as close as possible to the switch pins of the device with a wide trace to minimize conductive losses. The inductor can be placed on the bottom side of the PCB relative to the LM21215, but care must be taken to not allow any coupling of the magnetic field of the inductor into the sensitive feedback or compensation traces. 3. Have a solid ground plane between PGND, the EP and the input and output cap. ground connections. The ground connections for the AGND, compensation, feedback, and soft-start components should be physically isolated (located near pin 1 and 20) from the power ground plane but a separate ground connection is not necessary. If not properly handled, poor grounding can result in degraded load regulation or erratic switching behavior. 4. Carefully route the connection from the VOUT signal to the compensation network. This node is high impedance and can be susceptible to noise coupling. The trace should be routed away from the SW pin and inductor to avoid contaminating the feedback signal with switch noise. 5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and can improve efficiency. Voltage accuracy at the load is important so make sure feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the best output accuracy. 24 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 6. Provide adequate device heatsinking. For most 15A designs a four layer board is recommended. Use as many vias as is possible to connect the EP to the power plane heatsink. The vias located undernieth the EP will wick solder into them if they are not filled. Complete solder coverage of the EP to the board is required to achieve the θJA values described in the previous section. Either an adequate amount of solder must be applied to the EP pad to fill the vias, or the vias must be filled during manufacturing. See the THERMAL CONSIDERATIONS section to ensure enough copper heatsinking area is used to keep the junction temperature below 125°C. LM21215 L VOUT SW PVIN VIN CIN COUT PGND LOOP1 LOOP2 Figure 38. Schematic of LM21215 Highlighting Layout Sensitive Nodes Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 25 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com HTSSOP-20 5,6,7 VIN 3 RF 4 CIN1 CIN2 CIN3 PVIN LO SW VOUT CC3 EN RFB1 RC2 AVIN CF LM21215 FB CSS 11-16 2 SS / TRK COMP CO1 CO2 CO3 19 18 CC1 RC1 RFB2 CC2 VIN 1 ILIM RILIM 17 PGOOD PGND AGND 8,9,10 RPGOOD 20 Figure 39. Typical Application Schematic 1 Table 1. Bill of Materials (VIN = 3.3 - 5.5V, VOUT = 1.2V, IOUT = 15A) ID DESCRIPTION VENDOR PART NUMBER QUANTITY CF CAP, CERM, 1uF, 10V, +/-10%, X7R, 0603 MuRata GRM188R71A105KA61D 1 CIN1, CIN2, CIN3, CO1, CO2, CO3 CAP, CERM, 100uF, 6.3V, +/-20%, X5R, 1206 MuRata GRM31CR60J107ME39L 6 CC1 CAP, CERM, 1800pF, 50V, +/-5%, C0G/NP0, 0603 TDK C1608C0G1H182J 1 CC2 CAP, CERM, 68pF, 50V, +/-5%, C0G/NP0, 0603 TDK C1608C0G1H680J 1 CC3 CAP, CERM, 820pF, 50V, +/-5%, C0G/NP0, 0603 TDK C1608C0G1H821J 1 26 CSS CAP, CERM, 0.033uF, 16V, +/-10%, X7R, 0603 MuRata GRM188R71C333KA01D 1 LO Inductor, Shielded Drum Core, Powdered Iron, 560nH, 27.5A, 0.0018 ohm, SMD Vishay-Dale IHLP4040DZERR56M01 1 RF RES, 1.0 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW06031R00JNEA 1 RC1 RES, 9.31k ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW06039K31FKEA 1 RC2 RES, 165 ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW0603165RFKEA 1 RFB1, RFB2, RPGOOD RES, 10k ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060310K0FKEA 3 RILIM RES, 7.15k ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW06037K15FKEA 1 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 LM21215 www.ti.com SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 HTSSOP-20 LO 5,6,7 VIN PVIN CIN1 RF REN1 3 4 CF SW VOUT CC3 EN RFB1 RC2 AVIN REN2 LM21215 FB CSS 11-16 2 SS/ TRK COMP CO1 CO2 19 18 CC1 RC1 RFB2 CC2 VIN 1 ILIM PGOOD 17 RPGOOD PGND AGND RILIM 8,9,10 20 Figure 40. Typical Application Schematic 2 Table 2. Bill of Materials (VIN = 4.0 - 5.5V, VOUT = 0.9V, IOUT = 8A) ID DESCRIPTION VENDOR PART NUMBER QUANTITY CF CAP, CERM, 1uF, 10V, +/-10%, X7R, 0603 MuRata GRM188R71A105KA61D 1 CIN1, CO1, CO2 CAP, CERM, 100uF, 6.3V, +/-20%, X5R, 1206 MuRata GRM31CR60J107ME39L 3 CC1 CAP, CERM, 1800pF, 50V, +/-5%, C0G/NP0, 0603 MuRata GRM1885C1H182JA01D 1 CC2 CAP, CERM, 82pF, 50V, +/-5%, C0G/NP0, 0603 TDK C1608C0G1H820J 1 CC3 CAP, CERM, 820pF, 50V, +/-5%, C0G/NP0, 0603 TDK C1608C0G1H821J 1 CSS CAP, CERM, 0.033uF, 16V, +/-10%, X7R, 0603 MuRata GRM188R71C333KA01D 1 LO Inductor, Shielded Drum Core, 680nH, 22A, 0.0014 ohm, SMD Coilcraft XAL1060-681ME 1 RF RES, 1.0 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW06031R00JNEA 1 RC1 RES, 8.25k ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW06038K25FKEA 1 RC2 RES, 124 ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW0603124RFKEA 1 REN1, RFB1, RPGOOD RES, 10k ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060310K0FKEA 3 REN2 RES, 19.6k ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060319K6FKEA 1 RFB2 RES, 20.0k ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060320K0FKEA 1 RILIM RES, 39.2k ohm, 1%, 0.1W, 0603 Vishay-Dale CRCW060339K2FKEA 1 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 27 LM21215 SNVS625E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E • 28 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 27 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM21215 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM21215MH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM21215 MH LM21215MHE/NOPB ACTIVE HTSSOP PWP 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM21215 MH LM21215MHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM21215 MH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM21215MHE/NOPB HTSSOP PWP 20 250 178.0 16.4 LM21215MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 6.95 7.1 1.6 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM21215MHE/NOPB HTSSOP PWP LM21215MHX/NOPB HTSSOP PWP 20 250 203.0 190.0 41.0 20 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA PWP0020AA MYB20XX (REV E) 4214875/A NOTES: A. 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