ADVANCE INFORMATION WCMC8016V9X 8Mb (512K x 16) Pseudo Static RAM Features • Wide voltage range: 2.70V–3.30V • Access Time: 70ns • Ultra-low active power — Typical active current: 2.0mA @ f = 1 MHz • • • • • — Typical active current: 11mA @ f = fmax Ultra low standby power Easy memory expansion with CE, CE2, and OE features Automatic power-down when deselected CMOS for optimum speed/power Offered in a 48 Ball BGA Package Functional Description[1] The WCMC8016V9X is a high-performance CMOS pseudo static RAM organized as 512K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life® (MoBL® ) in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption by more than 99% when deselected using CE LOW, CE2 HIGH or both BHE and BLE are HIGH. The input/output pins (I/O 0 through I/O 1 5) are placed in a high-impedance state when: deselected (CE HIGH, CE 2 LOW OE is deasserted HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling even when the chip is selected (Chip Enable CE LOW, CE2 HIGH and both BHE and BLE are LOW). Reading from the device is accomplished by asserting the Chip Enables (CE LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O 7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O1 5. See the Truth Table for a complete description of read and write modes Logic Block Diagram 512K x 16 RAM Array 1T SENSE AMPS A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0 –I/O7 I/O8 –I/O15 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 COLUMN DECODER BHE WE CE2 CE OE BLE Power -Down Circuit Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress .com. WeidaSemiconductor, Inc. 38-14026 Revised August 2003 ADVANCE INFORMATION WCMC8016V9X Pin Configuration[2, 3, 4] FBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 CE 2 A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A 17 A7 I/O3 Vcc D VCC I/O12 GND A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F NC/ A12 A13 WE I/O7 G A8 A9 A10 A11 NC/ I/O15 A 18 H Note: 2. NC “no connect” - not connected internally to the die. 3. DNU pins are to be left floating or tied to Vss. 4. Ball G2 and H6 are the expansion pins for the 16Mb and 32Mb density resectively. 38-14026 Page - 2 - of 12 ADVANCE INFORMATION WCMC8016V9X DC Voltage Applied to Outputs in High Z State [5, 6, 7] ........................................–0.2V to 3.3V DC Input Voltage [5, 6, 7] .....................................–0.2V to 3.3V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Output Current into Outputs (LOW).............................20 mA Storage Temperature ................................ –65°C to + 150°C Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied .............................................. –55°C to + 85°C Latch-Up Current .....................................................>200 mA Supply Voltage to Ground Potential ................. –0.4V to 4.6V Operating Range[9] Device WCMC8016V9X Range Ambient Temperature VCC Industrial –25°C to +85°C 2.70V to 3.30V Product Portfolio Power Dissipation Product Speed (ns) VCC Range (V) Operating ICC (mA) f = 1MHz WCMC8016V9X-FI70 Min. Typ.[8] Max. 2.70 3.0 3.30 70 f = fmax Standby I SB2 (µA) Typ. [8] Max. Typ. [8] Max. Typ.[8] Max. 2 3.5 11 17 55 80 Notes: 5. VIH(MAX) = VCC + 0.5V for pulse durations less than 20ns. 6. VIL(MIN) = -0.5V for pulse durations less than 20ns. 7. Overshoot and undershoot specifications are characterized and are not 100% tested. 8. Typical values are included for reference only and are not guranteed or tested. Typical values are measured at VC C = VCC (typ) and TA = 25C 9. VCC must be at minimal operational levels before inputs are turned ON. 38-14026 Page - 3 - of 12 ADVANCE INFORMATION WCMC8016V9X Electrical Characteristics Over the Operating Range WCMC8016V9X-70 Parameter Description Test Conditions Typ. [8] Min. VCC Supply Voltage VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.70V VOL Output LOW Voltage IOL = 2.0mA VCC = 2.70V VIH Input HIGH Voltage VCC= 2.7V to 3.3V VIL Input LOW Voltage VCC= 2.7V to 3.3V(F = 0) IIX Input Leakage Current IOZ ICC Max. Unit 3.3 V 2.7 2.4 V 0.4 V 0.8*Vcc VCC +0.3V V -0.3 0.4 V GND < VI < VCC –1 +1 µA Output Leakage Current GND < VO < VCC , Output Disabled –1 +1 µA VCC Operating Supply Current f = fMAX = 1/tRC 11 17 mA 2.0 3.5 mA ISB1 Automatic CE Power-Down Current — CMOS Inputs CE > VCC −0.2V or CE2< 0.2V Vcc = 3.3V VIN>VCC –0.2V, VIN <0.2V) f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC=3.30V 400 µA ISB2 Automatic CE Power-Down Current — CMOS Inputs CE > VCC – 0.2V or CE 2 < Vcc = 3.3V 0.2V, Vcc = 3.0V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.30V Vcc = 2.8V 55 80 µA 50 70 µA 45 60 µA VCC = V CCmax IOUT = 0 mA CMOS levels f = 1 MHz Capacitance[10] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF T A = 25°C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance[10] Description Thermal Resistance (Junction to Ambient) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board Thermal Resistance (Junction to Case) Symbol BGA Unit ΘJA 55 °C/W ΘJC 16 °C/W Note: 10. Tested initially and after any design or process changes that may affect these parameters. 38-14026 Page - 4 - of 12 ADVANCE INFORMATION WCMC8016V9X AC Test Loads and Waveforms R1 VCC OUTPUT VCC 50 pF INCLUDING JIG AND SCOPE 38-14026 R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalentto: THÉVENINEQUIVALENT RTH OUTPUT V Parameters 3.0V VCC Unit R1 1179 Ω R2 RTH 1941 733 Ω Ω VTH 1.87 V Page - 5 - of 12 ADVANCE INFORMATION WCMC8016V9X Switching Characteristics Over the Operating Range [11] 70 ns Parameter Description Min. Max. Unit READ CYCLE t RC Read Cycle Time 70 t AA Address to Data Valid t OHA Data Hold from Address Change t ACE CE LOW and CE2 HIGH to Data Valid 70 ns t DOE OE LOW to Data Valid 35 ns 70 10 [12, 14] t LZOE ns OE LOW to LOW Z ns 5 [12, 14] t HZOE OE HIGH to High Z t LZCE CE LOW and CE2 HIGH to Low Z[12, 14] ns 25 t HZCE CE HIGH and CE2 LOW to High Z t DBE BLE / BHE LOW to Data Valid 5 [12, 14] [12, 14] ns ns ns 25 ns 70 ns t LZBE BLE / BHE LOW to Low Z t HZBE BLE / BHE HIGH to HIGH Z[12, 14] 25 ns Address Skew 10 ns tS K 5 ns [13] WRITE CYCLE t WC Write Cycle Time 70 ns t SCE CE LOW and CE2 HIGH to Write End 60 ns t AW Address Set-Up to Write End 60 ns t HA Address Hold from Write End 0 ns t SA Address Set-Up to Write Start 0 ns t PWE WE Pulse Width 45 ns t BW BLE / BHE LOW to Write End 60 ns t SD Data Set-Up to Write End 45 ns t HD Data Hold from Write End 0 t HZWE WE LOW to High-Z[12, 14] t LZWE [12, 14] WE HIGH to Low-Z ns 25 5 ns ns Notes: 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1ns/V, timing reference leve ls of V CC(typ)/2, input pulse levels of 0 to VCC (typ.) , and output loading of the specified I OL /I O H as shown in the “AC Test Loads and Waveforms” section.. 12. t HZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 13. The internal Write time of the memory is defined by the overlap of WE, CE = V IL, BHE and/or BLE = V IL, and CE2 = VIH . All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be refere nced to the edge of the signal that terminates the write. 14. High-Z and Low-Z parameters are characterized and are not 100% tested. 38-14026 Page - 6 - of 12 ADVANCE INFORMATION WCMC8016V9X Switching Waveforms Read Cycle 1 (Address Transition Controlled)[15] t RC ADDRESS tOHA t SK DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle 2 (O E Controlled) [15] ADDRESS CE tRC tSK tPD tHZCE CE2 tACE BHE / BLE tLZBE tDBE tHZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC Note: 15. WE is HIGH for read cycle. 38-14026 tPU I CC 50% 50% Page - 7 - of 12 ADVANCE INFORMATION WCMC8016V9X Switching Waveforms (continued) Write Cycle 1 (WE Controlled) [13, 14,16, 17, 18] tWC ADDRESS tSCE CE CE2 tAW tHA tSA tPWE WE tBW BHE /BLE OE tSD DATAI/O tHD VALID DATA DON’T CARE [13, 14,16, 17, 18] Write Cycle 2 (CE or CE2 Controlled) tWC ADDRESS tSCE CE CE2 tS A tAW tHA tPWE WE tBW BHE /BLE OE tSD DATAI/O tHD VALID DATA DON’T CARE tHZOE Notes: 16. Data I/O is high impedance if OE = VIH . 17. If Chip Enable goes INACTIVE and CE2 goes LOW simultaneously with WE = V IH, the output remains in a high-impedance state. 18. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. 38-14026 Page - 8 - of 12 ADVANCE INFORMATION WCMC8016V9X Switching Waveforms (continued) [17, 18] Write Cycle 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE CE2 tBW BHE /BLE tAW tHA tSA tPWE WE tSD DATAI/O tHD VALID DATA DON’T CARE tLZWE tHZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW)[17, 18] tWC ADDRESS CE CE2 tSCE tAW tHA tBW BHE/BLE tS A tP W E WE tSD DATA I/O 38-14026 DON’T CARE tHD VALID DATA Page - 9 - of 12 ADVANCE INFORMATION WCMC8016V9X Truth Table[19] CE CE2 WE OE BHE BLE H X X X X X X L X X X X X X X L H H L L H H L H L Inputs/Outputs Mode Power High Z Deselect/Power-Down Standby (I SB) X High Z Deselect/Power-Down Standby (I SB) H H High Z Deselect/Power-Down Standby (I SB) L L Data Out (I/O0 – I/O15) Read Active (ICC) L H L Data Out (I/O0 – I/O7); High Z (I/O8 – I/O15) Read Active (ICC) H L L H High Z (I/O0 – I/O7); Data Out (I/O8 – I/O15) Read Active (ICC) H H H L H High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L L High Z Output Disabled Active (ICC) L H L X L L Data In (I/O0 – I/O15) Write Active (ICC) L H L X H L Data In (I/O0 – I/O7); High Z (I/O8 – I/O15) Write Active (ICC) L H L X L H High Z (I/O0 – I/O7); Data In (I/O8 – I/O15) Write Active (ICC) Note: 19. H = V I H, L = V IL , X = Don’t Care Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 70 WCMC8016V9X-FI70 BA48K 48-ball Fine Pitch BGA (6 mm × 8mm × 1.2 mm) Industrial 38-14026 Page - 10 - of 12 ADVANCE INFORMATION WCMC8016V9X Package 48-Ball (6 mm x 8mm x 1.2 mm) FBGA BA48K 51-85193-*A MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders 38-14026 Page - 11 - of 12 © Weida Semiconductor, Inc., 2002. The information contained herein is subject to change without notice. Weida Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Weida Semiconductor product. Nor does it convey or imply any license under patent or other rights. Weida Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Weida Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Weida Semiconductor against all charges. ADVANCE INFORMATION WCMC8016V9X Document Title: WCMC8016V9X MoBL3® 8Mb (512K x 16) Pseudo Static RAM Document Number: 38-14026 REV. ECN NO. Issue Date Orig. of Change ** 130543 10/16/03 MPR 38-14026 Description of Change New Datasheet Page - 12 - of 12