MAY 1996 ADVANCE INFORMATION DS4054-2.2 WL100 WLAN INTERFACE CIRCUIT FEATURES ■ Low Power CMOS Technology ■ Flexible Data Transceiver ■ Clock Recovery with Continuous Calibration for Flexible Packet Length ■ Flexible Preamble Format ■ Selectable Data Rates: 156·25kb/s, 250kb/s, 312·5kb/s, 500kb/s, 625kb/s and 1Mb/s ■ CRC-32 Generator/Checker ■ Fast Antenna Diversity with Manual Override ■ Battery Level Monitoring ■ 8-Bit Parallel Controller Interface B_DATA0 B_DATA1 B_DATA2 B_DATA3 B_DATA4 B_DATA5 B_DATA6 VSS VDD B_DATA7 B_ADDR0 B_ADDR1 B_ADDR2 B_ADDR3 B_ADDR4 CS The WL100, together with the DE6003 frequency hopping radio transceiver, implements a wide variety of WLAN applications where NRZ encoding is used. RD WR RESET CKSEL1 CKSEL0 E_CLK VDD VSS B_CLK C_CLK TEST ATSTIN ATSTOUT XCKT RXD SYNLOK PIN 1 IDENT WL100 PIN 1 PIN 64 NC NC IRQ VSS VBAT SHCAP RSSI NC NC VREF STDBY VDD ANTSEL VSS NC NC RELATED DOCUMENTS PAOFF PWRLO RX/TX TXD LOADB SD6 SD5 VDD VSS CLK NC SD4 SD3 SD2 SD1 SD0 DE6003 data sheet, DS3506 GPS application notes AN142,143,144,145, 154 and 203 for further design information. FP64 ORDERING INFORMATION WL100/CG/FP1R - Commercial, Quad Plastic Flatpack Prior to completion of full device characterisation, preproduction parts will be designated WL100/PR/FP1R. DE6003 FREQUENCY HOPPING TRANSCEIVER WL100 WLAN INTERFACE CIRCUIT Fig. 1 Pin connections (top view). See Table 8 for pin descriptions. WLAN MAC CONTROLLER Fig. 2 WLAN system block diagram HOST MICROPROCESSOR WL100 GENERAL FUNCTIONALITY Fig. 4 shows the WL100 Block Diagram and its interaction with the DE6003 and a generic WLAN Media Access Controller (MAC) layer Controller, referred to in the following text as the Controller. The format of a generic data burst/packet that the WL100 receives on the RXD line is shown in Fig. 3. On the radio side, the WL100 conforms to the DE6003 specifications. On the Controller side the WL100 conforms to the general 8-bit Controller external bus specifications. All WL100 registers are accessed by the Controller through the 8-bit B_DATA bus. A typical Controller I/O read/write timing is shown in Fig. 15. There are five types of registers internal to the WL100 which the Controller can access via the B_DATA bus: Control Registers (write only), Status Registers (read only), Configuration registers (write only), FIFO (read/write) and Data Length Registers (write only). The Controller uses the control registers to initiate a particular WL100 function. The bit definitions for the WL100 control registers are shown in Fig. 5. SYNC WORD SYNC WORD The status registers are used to inform the Controller about the WL100 and DE6003 status. Fig. 6 shows the bit definitions for the WL100 status registers. The Controller makes the decision about a channel status according to the table in Fig. 6. Fig. 7 shows the 1638 receive/transmit FIFO and the data length register. The FIFO buffers the data going to/coming from the Controller and provides an uninterrupted data flow between the WL100 and DE6003 at different data rates and system clock speeds. The data length register is used for the CRC calculations during data receive. The configuration registers are shown in Figs. 8 and 9. They give flexibility to the WL100 so that it can be used in a number of different system applications. Configuration registers can be written to only when the Commence Diversity (CD), Commence Transmission (CT), Commence Reception (CR) and Commence Hopping (CH) bits in a WL100 control register are inactive (high). SYNC WORD SYNCHRONISATION SEQUENCE 10 FRAME DELIMITER 100 CRC - 32 HEADER PREAMBLE USER DATA FCS Fig 3 Generic data burst/packet format Start address End address 00 03 04 08 0C 0D 10 1B 1C 1E 02 07 0B 0F 1A 1D 1F Description Control registers Unused Status registers Unused FIFO Unused Configuration registers Unused Data length registers Unused Table 1 Table 1 shows how the WL100 registers are mapped into its address space. The Controller activates the WL100 each time it wants to scan the channel, receive data from the channel or transmit data over it. Prior to the start of a transmit or a receive function, the WL100 will drive the control signals to put the radio in a required mode of operation, according to the DE6003 specification. The Controller is responsible for updating the frequency control register (Fig.5, ADDR 01), maintaining minimum time between consecutive transmissions, maximum continuous transmit time, radio standby to transmit time, frequency hopping time for transmit and for receive and timely loading of the data length register (Fig. 7, ADDR 1C and1D) for the CRC function. In the transmit direction, the WL100 receives the user data in 8-bit words from the Controller bus and converts it into a serial data stream. After a preamble sequence has been transmitted, the WL100 calculates CRC, does bit stuffing and transmits a data stream to the radio, appending the CRC at the end. Both transmit and receive data is buffered by the FIFO. In the receive direction, the WL100 receives a serial NRZ data stream from the radio, strips the preamble, removes the 2 stuffed bits, generates the CRC, converts the serial data into 8bit words and sends it to the Controller. Once all data have been received, the WL100 checks CRC and writes four CRC bytes into the FIFO in case the Controller needs to read them. If the WL100 cannot recover the synchronisation sequence within a predefined time, it returns a channel status to the Controller. BLOCK DIAGRAM DESCRIPTION Receive/Transmit State Machine The Receive/Transmit state machine controls the WL100to-DE6003 interface and is responsible for the receive/transmit control timing, transmit power amplifier control timing, transmitter power level control and channel load pulse timing. To hop to a new frequency, the CH bit (Fig. 5, ADDR 01, bit 7) has to be set to 0. As a result, a negative LOADB pulse is generated and will load the frequency data SD (0:6) (Fig. 5, ADDR 01, bits 0 to 6) into the DE6003. The Controller does not need to reset the CH bit as the WL100 carries this out as part of the channel select sequence. To start data transfer, the Controller must set the CT bit to 0 (Fig.5, ADDR 00, bit 4). When all transmit data has been read by the WL100, the CT bit must be reset to 1. Preamble Generator A preamble is generated for every transmit data burst sent to the DE6003 on TXD. The preamble is fully programmable ( see Fig. 8, ADDR 12 and ADDR 13, bits 0:2 for a sync word bit pattern, ADDR18 for the number of transmitted sync words, and ADDR 13, bits 3:7 and ADDR 14 to 17 for the frame delimiter bit pattern). Bit Stuffing The Bit Stuffing logic examines the data stream to the radio and inserts an altered polarity bit relative to the last bit in a selected bit group. A number of bits in a group can be programmed (see Fig. 9, ADDR 19, bits 6 and 7). The DE6003 requires at least one transition after every 16 bit times at 625kb/s data rate to assure adequate bit error rate performance. Thus, to break long sequences of ones or zeros at 312kb/s, bit stuffing after DE6003 ANT 2 RSSI STDBY PWRLO LOADB SD (6:0) PAOFF RX / TX SYNLOK ANTSEL CKSEL E_CLK CLK TXD RXD ADDR 00 (6) ADDR 00 (7) CLOCK SELECTOR/ GENERATOR RECEIVE / TRANSMIT STATE MACHINE C10MHz ADDR 19 (7:6) BIT STUFFING ADDR 01 (6:0) ADDR 06 (0) ADDR 06 (1) ADDR 07 (7) 2 CLK RCV M U X M U X 2 5 M U X VBAT ADC VREF SUCCESSIVE APPROXIMATION REGISTER DIVERSITY CONTROLLER ADDR 04 (7, 6, 4:0) ADDR 00 (2:0) CK800N, CK400N ADDR 06 (5.4) 5 ADDR 07(6:3) ADDR 12-17 CRC GEN/CHK FIFO CONTROL AND FLAG LOGIC BIT DESTUFFING PREAMBLE GENERATOR ADDR 06 (7:6) ADDR 07 (2:0) CONFIGURATION REGISTERS DATA RECOVERY XCKT CLOCK RECOVERY AND CCA WL100 7 C_CLK ADC CONTROL ANT 1 2 SHCAP TEST BATTERY MONITOR INTERRUPT LOGIC RD/WR CONTROL AND REGISTER SELECT 8 8 8 5 STATUS ADDR 04-07 8 MUX ATSTIN ATSTOUT ADDR 05 (6, 4:0) PARALLEL/SERIAL CONVERTER MUX (15) FIFO 1638 (0) MUX SERIAL/PARALLEL CONVERTER 8 IRQ RESET B_ADDR (4:0) WR RD CS B_CLK B_DATA (7:0) WLAN MEDIA ACCESS CONTROLLER (MAC) WL100 Fig. 4 WL100 chip block diagram 3 WL100 8 bits will be required and for 156kb/s, bit stuffing after 4 bits will be needed. The WL100 performs bit stuffing for user data only. Preamble fields must be selected by a user in a way that a maximum number of consecutive ones or zeros is not violated. Bit stuffing also helps to distinguish between long strings of ones or zeros in a valid data stream and a clear channel (no data and no noise) by the Clear Channel Assessment (CCA) logic. Full and Empty flags are also provided (Fig. 6, ADDR 06, bits 2 and 3). All bits are set on the negative edge of the C_CLK clock. Parallel-to-Serial Converter The Parallel-to-Serial Converter transforms parallel byte-wide data from the FIFO or from the Preamble Generator to a serial bit stream. The data from the FIFO is sent to the CRC Generator and Bit Stuffing logic. The preamble is sent directly to the TXD output of the chip. Bit Destuffing The Bit Destuffing logic monitors a data sequence from the Data Recovery logic and strips the bits inserted by the bit stuffing logic of the transmitter. CRC Generator/Checker The WL100 performs this optional function if instructed to do so by the Controller (see Fig. 5, ADDR 02, bit 1). CRC is generated according to IEEE-802 standard 32-bit AUTODIN-II polynomial. During transmit the WL100 does not need to know the user data byte count and will automatically append CRC when the CT bit (Fig. 5, ADDR 00, bit 4) is high and the FIFO becomes empty. During receive the Controller has to provide the WL100 with the data length information (Fig. 7, ADDR 1C and ADDR 1D) some time before the end of a frame to let the WL100 know when to check CRC. Serial-to-Parallel Converter This transforms a serial data stream from the bit destuffing logic into parallel byte-wide format and sends it to the FIFO. FIFO The FIFO a 1638, fall-through type. During receive operation it buffers the data coming from the Serial-to-Parallel Converter and makes it available for the Controller to read over the B_DATA bus. During transmit operation it buffers the data coming from the B_DATA bus and makes it available to the Parallel-to-Serial Converter. FIFO Control and Flag Logic Clock Recovery and Clear Channel Assessment (CCA) The FIFO Control and Flag logic controls data flow through the FIFO. Almost Full (AF) and Almost Empty (AE) flags (Fig. 6, ADDR 07, bits 3 and 4) are programmable by FL 0 and FL1(Fig. 9, ADDR 1A, bits 5 and 6) and can be monitored by the Controller as well as Read and Write error indication bits (Fig. 6, ADDR 07, bits 5 and 6). A Read error is caused by attempting to read from the FIFO when it is empty; a Write error is caused by attempting to write to the FIFO when it is full. The Clock Recovery and CCA logic recovers the data clock XCKT from the RXD data stream, provides recovered clock to the Data Recovery logic, and determines if the channel is busy or free to transmit. The WL100 starts recovering clock each time the CR bit (Fig. 5, ADDR 00, bit 3) is set low by the Controller. It must stay low for the whole time of CCA or data receive function. ADDR 01 ADDR 00 6 5 4 3 2 1 SD6 SD5 SD4 SD3 SD2 SD1 0 7 6 5 SD0 PWRL STDB RST 4 3 CT CR 2 1 ANT2 MAN 0 CD (d) = default state 7 CH 0 = Commence Hopping 1 = Inactive (d) Channel Select (d = 0000000) 0 = Commence Auto Diversity 1 = Auto Diversity Inactive (d) 0 = Low power level (d) 1 = High power level 0 = Manual Diversity 1 = Auto Diversity (d) (See Table 6) 0 = Sleep Mode (d) 1 = Operational Mode 0 = Manual ANT 1 (d) 1 = Manual ANT 2 (See Table 6) 0 = Reset All Registers (Except CNTRL and CONFIG) 1 = Inactive (d) 0 = Commence Transmission (at least 1µs long) 1 = Stop Transmission (d) 0 = Commence Receive Function 1 = Stop Receive Function (d) ADDR 02 7 6 5 MSK7 0 = SYNLOK Enabled 1 = SYNLOK Disabled (d) 4 3 2 1 0 DGT ECRC DBG 0 = Normal Operation Mode (d) 1 = Device Tests (Digital) Mode 0 = CRC Disabled (TX) / DL Not Valid (RX) 1 = CRC Enabled (TX) / DL Is Valid (RX) (d) Fig. 5 Control registers (write only) 4 0 = Normal Mode (d) XCKT when in Sync 1 = Debug Mode XCKT at all times WL100 Read/Write Control and Register Select After the time limit for the synchronisation has expired, the syncdone (SYDN) bit is set (Fig. 6, ADDR 07, bit 2) and interrupt to the controller is generated. At this time the Controller can make a decision about the channel status by examining noise (NS) and long sequence (LONG) bits (Fig. 6, ADDR 07, bits 1 and 0). Clock Recovery and CCA logic requires 16:1 ratio for an oversampling clock C_CLK. Table 7 shows the oversampling clock rate required for particular selected data transfer rates. The Read/Write Control and Register Select logic controls the bidirectional B_DATA bus and selects the WL100 registers during the Controller-initiated read and write operations. Interrupt Logic Interrupt logic generates interrupt requests to the Controller when a certain WL100 status has to be reported. At that time, IRQ becomes low and stays low until reset. Table 2 lists all cases when the WL100 generates interrupts together with corresponding interrupt reset conditions. Radio Synthesiser Unlocked interrupt can be disabled by setting the MSK7 bit high (Fig. 5, ADDR 02, bit 7). Data Recovery Logic The Data Recovery logic detects the sequence of sync words and the frame delimiter in the data stream supplied by the Clock Recovery logic according to the Sync Word and Frame Word configuration (see Fig. 8, ADDR 12 and ADDR 14 -17) and separates it from the User Data. If NS or LONG bits (ADDR 07, bits 1 and 0) have been set, the WL100 stops searching for sync sequence. The Controller might choose to poll these bits to get early indication of a free channel prior to expiration of Syncdone Timer. Once the sync sequence has been detected, the SYNC bit (see Fig. 6, ADDR 06, bit 6) goes high and remains high until the end of the data reception. The FRM bit (see Fig. 6, ADDR 06, bit 7) goes high when a frame delimiter has been detected and stays on until the end of data reception. Diversity Controller The Diversity Controller automatically selects the optimum antenna during receive operations. To start auto diversity, the Controller has to set the auto diversity bit (Fig. 5, ADDR 00, bit 0) low, which has to stay low for at least 1µs, when it can be switched back to high at any time before another diversity function is to be initiated. The circuit performs diversity by comparing the Receive Signal Strength Indication (RSSI) energy levels from both antennas and selecting the one which yields the higher level. The Diversity Switch can also be controlled manually (Fig. 5, ADDR 00, bits 1 and 2). The RSSI level can be checked at any time by auto operation of the diversity (see Fig. 6, ADDR 04). ADDR 05 ADDR 04 6 5 3 2 1 BT4 BT3 BT2 BT1 0 7 6 5 BT0 AUT2 DVAL BVAL 4 4 3 2 1 0 DV4 DV3 DV2 DV1 DV0 RSSI Level (See Table 9) 0 = DV Not Valid (d) 1 = DV Valid Battery Level (See Table 10) 0 = BT Not Valid (d) 1 = BT Valid (d) = default state 7 0 = Auto ANT 1 (d) 1 = Auto ANT 2 ADDR 07 ADDR 06 7 6 5 LCK WERR RERR 4 AE 3 2 AF SYDN 1 NS 0 7 6 5 4 FIFO Write Error FIFO Read Error Channel status (ADDR 07, bits 2:0) Status NS LONG 1 0 0 Channel is busy 1 1 X 1 X 1 Channel is clear to transmit 2 1 0 0 = Power Amp. Off 1 = Power Amp. On 0 = Transmit in Progress 1 = No Transmit 0 = Buffer Not Full 1 = Buffer Full 0 = Buffer Not Empty 1 = Buffer Empty 0 = No CRC Error 1 = CRC Error 0 = CRC Not Ready 1 = CRC Checked 0 = No Synchronisation 1 = SYNC Achieved 0 = No Frame 1 = Frame Recognised 0 = No Long Sequence 1 = Long Sequence of ‘1’s or ‘0’s 0 = No Noise 1 = Noise 0 = Syncdone Timer Not Expired 1 = Syncdone Timer Expired 0 = Buffer Not Almost Full 1 = Buffer Almost Full 0 = Buffer Not Almost Empty 1 = Buffer Almost Empty 0 = Radio PLLs Locked 1 = Radio PLLs Unlocked SYDN 3 CRC LONG FRM SYNC CRCE EMP FULL RXTX PAOF RDY Fig. 6 Status registers (read only) 5 WL100 Battery Monitor the WL100 (C10MHz clock from the CLK RCV or E_CLK from an external clock oscillator). It supplies the system clock B_CLK for the Controller, C_CLK clock for the Clock Recovery and CCA logic, and CK400N and CK800N clock for the Diversity Controller and the Battery Monitor. Fig. 14 shows the details of the Clock Selector/Generator logic. For DR(2:0) bit settings see Fig. 9, ADDR 19, bits 2:0. Note that, for correct operation, the Receive/ Transmit state machine, the Diversity Controller and the Battery Monitor require 10MHz clock. So even if an external oscillator with a clock rate other than 10MHz is used, the low level 10MHz CLK from the DE6003 is still required. When the STDB bit (ADDR 00, bit 6) is reset to ‘0’, all WL100 clocks are disabled except for the control registers and configuration registers clocks; B_CLK clock output also remains active. The Battery Monitor (input VBAT) allows relative estimation of the remaining operating time for the user in battery-powered applications. Both the Diversity Controller and the Battery Monitor use as an input a digital representation of analog RSSI and battery voltage levels from the 5-bit succesive approximation ADC. The Battery Monitor status register value is updated whenever an auto diversity function is performed (Fig. 6, ADDR 05). CLK RCV CLK RCV is a 10MHz low level clock amplifier. An analog circuit, it transforms the nominal 61 mA square wave current, CLK, from the DE6003 into a digital CMOS level clock. Clock Selector/Generator The Clock Selector/Generator selects the clock source for ADDR 0C 7 6 5 4 3 2 1 0 FIFO (15) FIFO (15:0) FIFO (0) ADDR 1D ADDR 1C 7 6 5 4 3 2 DL15 DL14 DL13 DL12 DL11 DL10 1 0 7 6 5 4 3 2 1 0 DL9 DL8 DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0 Data Length, DL(15:0) (up to 65·535 bytes) Fig. 7 Data register (FIFO) and data length registers (read/write) Interrupt FIFO read error (ADDR 07, bit 5) FIFO write error (ADDR 07, bit 6) FIFO almost full (ADDR 07, bit 03) FIFO almost empty (ADDR 07, bit 04) Syncdone Timer expired (ADDR 07, bit 2) Radio synthesiser unlocked (ADDR 07, bit 7) CRC ready (ADDR 06, bit 5) NOTES 1. Set on the negative edge of B_CLK 2. Set on the negative edge of C_CLK 3. Set on the negative edge of 10MHz 6 Reset condition RST control bit (ADDR 00, bit 5) RST control bit (ADDR 00, bit 5) When the condition is cleared When the condition is cleared When CR goes high (ADDR 00, bit 3) When the condition is cleared When CRC is read by the Controller or when CR goes high (ADDR 00, bit 3) Table 2 WL100 interrupts Note 1 1 1 1 2 3 1 WL100 CONFIGURATION REGISTERS Tables 3, 4, and 5, together with Figs. 8 and 9, describe the configuration registers of the WL100. Table 3 describes the configuration registers that control Clock Recovery and CCA; Table 4 describes the registers controlling the Preamble Generator and Data Recovery mechanism and Table 5 describes other programmable resources. Bits Register JT (1:0) ADDR 1A NT (1:0) ADDR 1A BS (1:0) ADDR 19 Definition Jitter tolerance for the incoming data (maximum deviation from an ideal pulse. when pulse is still considered valid). Three options. Noise tolerance (number of occurrences of invalid data until the noise flag is raised). Four options. Bit stuffing algorithm. Four options. Fig. 9 9 9 Table 3 Clock Recovery and CCA configuration registers Bits Register TSW (7:0) BSW (2:0) SW (7:0) NSW (2:0) ADDR 18 ADDR 13 ADDR 12 ADDR 19 BE (0) ADDR 1A BFW (4:0) FW(31:0) ADDR 13 ADDR 14, 15, 16, 17 Definition Fig. Number of Sync Words to be transmitted. Number of bits in a Sync Word. Sync Word bit pattern. Number of Sync Words to be recovered before the Receiver is considered to be in sync with the Transmitter. Indicates if single bit errors are allowed before Frame Delimiter after synchronisation has been achieved. Number of bits in the Frame Delimiter. Frame Delimiter bit pattern. 9 8 8 9 9 9 8 Table 4 Configuration registers controlling the Preamble Generator and the Data Recovery mechanism Bits ST (15:0) DR(2:0) FL(1:0) Register Definition Time limit for achieving synchronisation (0-216 C_CLK clock cycles). Specifies required oversampling clock rate. Specifies thresholds for Almost Full and Almost Empty FIFO flags. ADDR 10,11 ADDR 19 ADDR 1A Fig. 8 9 9 Table 5 Other programmable resources Function Manual Auto MAN (ADDR 00, bit 1) ANTSEL (pin 52) 0 1 ANT 2 (ADDR 00, bit 2) AUT 2 (ADDR 04, bit 7) Table 6 Antenna selection table 7 ADDR 13 ADDR 12 ADDR 11 ADDR 10 5 4 3 2 1 0 7 SW6 6 SW5 5 SW4 4 SW3 3 0 = Not Used 1 = 2 Bits in a Sync Word 2 = 3 Bits in a Sync Word 3 = 4 Bits in a Sync Word 4 = 5 Bits in a Sync Word 5 = 6 Bits in a Sync Word 6 = 7 Bits in a Sync Word 7 = 8 Bits in a Sync Word 0 = Not Used 1 = 2 Bits in a Frame Word 2 = 3 Bits in a Frame Word 3 = 4 Bits in a Frame Word : 30 = 31 Bits in a Frame Word 31 = 32 Bits in a Frame Word ADDR 16 NUMBER OF BITS IN A SYNC WORD. BSW(2:0) ADDR 17 SW2 2 SYNC WORD. SW(7:0) NUMBER OF BITS IN A FRAME WORD. BFW(4:0) BFW4 BFW3 BFW2 BFW1 BFW0 BSW2 BSW1 BSW0 SW7 6 SW1 1 SW0 0 6 5 4 ST15 ST14 ST13 ST12 7 2 ST11 ST10 3 ST9 1 ST8 0 ST7 7 ST6 6 ST5 5 ST4 4 ST3 3 ST2 2 ST1 1 ST0 0 ADDR 15 SYNCHRONISATION TIME LIMIT. ST(15:0) ADDR 14 8 7 Fig. 8 Configuration registers ADDR 10 through ADDR 17 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 FRAME WORD. FW (31:0) FW31 FW30 FW29 FW28 FW27 FW26 FW25 FW24 FW23 FW22 FW21 FW20 FW19 FW18 FW17 FW16 FW15 FW14 FW13 FW12 FW11 FW10 FW9 6 FW8 0 FW7 7 FW6 6 FW5 5 FW4 4 FW3 3 FW2 2 FW1 1 FW0 0 7 WL100 WL100 ADDR 1A ADDR 19 ADDR 18 4 3 2 1 0 7 FL1 FL0 BE0 NT1 NT0 JT1 JT0 BS1 6 5 4 3 2 1 BS0 NSW2 NSW1 NSW0 DR2 DR1 0 7 NUMBER OF SYNC WORDS REQUIRED FOR SYNCHRONISATION, NSW (2:0) NOISE TOLERANCE, NT (1:0) 0 = 1 Occurrence 1 = 4 Occurrences 2 = 8 Occurrences 3 = 16 Occurrences AF/AE FLAGS THRESHOLD, FL (1:0) 0 = Set when 1 Location Full/Empty 1 = Set when 2 Locations Full/Empty 2 = Set when 3 Locations Full/Empty 3 = Set when 4 Locations Full/Empty 4 JITTER TOLERANCE, JT (1:0) 3 2 1 0 NUMBER OF TRANSMITTED SYNC WORDS, TSW (7:0) (up to 255) 0 = No Bit Stuffing 1 = Bit Stuffing After 4 2 = Bit Stuffing After 8 3 = Bit Stuffing After 16 0 = Not Allowed 1 = Allowed 5 DR0 TSW7 TSW6 TSW5 TSW4 TSW3 TSW2 TSW1 TSW0 BIT STUFFING, BS (1:0) SINGLE BIT ERRORS, BE (0) 6 5 6 7 C_CLK RATE, DR (2:0) 0 = E_CLK (MAX DATA RATE) 1 = E_CLK/2 2 = E_CLK/4 3 = E_CLK/8 4 = 10MHz 5 = 5MHz 6 = 2·5MHz 7 = INVALID – DO NOT INVOKE 0 = 1 Sync Word 1 = 2 Sync Words 2 = 3 Sync Words 3 = 4 Sync Words 4 = 5 Sync Words 5 = 6 Sync Words 6 = 7 Sync Words 7 = 8 Sync Words 0 = 12·5% 1 = 25% 2 = 37·5% Fig. 9 Configuration registers ADDR 18, ADDR 19 and ADDR 1A FLOW DIAGRAMS Figs. 10 through 13 are flow diagrams for a channel hop, antenna diversity and battery monitoring, channel sense, data receive and data transmit functions. RESET YES DV(4:0) . RSSI 2? NO CD = 0? NO YES RESET SWITCH ANTENNA DVAL = 1 ANT 2 = 0 DV (4:0) = RSSI 2 DVAL = 1 ANT 2 = 1 DVAL = 0 BVAL = 0 CH = 0? NO SAMPLE 1ST ANTENNA SAMPLE VREF YES SWITCH ANTENNA LOADB = 0 CH = 1 1µs EXPIRED? NO YES 1ST ANTENNA RSSI CONVERSION VREF CONVERSION BT(4:0) = VREF CONV SAMPLE VBAT DV(4:0) = RSSI (1) LOADB = 1 SAMPLE 2ND ANTENNA VBAT CONVERSION DONE 2ND ANTENNA RSSI CONVERSION Fig. 10 Channel selection BT(4:0) = VABS = BT (4:0) 2 VBAT CONV BVAL = 1 Fig. 11 Antenna diversity and battery monitoring 9 WL100 RESET CR = 0? YES SD TIMER EXPIRED? NO RESET YES NO NO CT = 0? CLOCK RECOVERY CCA AND DATA RECOVERY YES NO NS OR LONG ? RX/TX = 0 NO SYNC = 1? YES NO SD TIMER EXPIRED? YES 1µs EXPIRED? SET NS = 1 OR LONG = 1 NO NO YES FRAME = 1? YES PAOFF = 1 YES BIT DESTUFFING FIFO WRITE CRC GEN SYDONE = 1 IRQ = 0 4µs EXPIRED? NO YES CR = 1? NO YES NO ECRC = 1? SEND A PREAMBLE YES EOF? NO READ FROM FIFO GENERATE CRC BIT STUFFING TRANSMIT DATA YES NO CT = 1? CRC READY? NO PAOFF = 0 YES YES COMPLETE DATA TRANSFER CRC ERR = 1 IRQ = 0 NO 4µs EXPIRED? YES CR = 1? ECRC = 1? YES NO CRC REG = 0? NO RX/TX =1 YES YES APPEND CRC32 DONE RESET FLAGS AND POINTERS DONE Fig. 12 Channel sense and data receive 10 Fig. 13 Data transmit NO WL100 CLOCK SELECTOR/GENERATOR Fig. 14 shows the logic of the clock selector/generator. C_CLK rate conntrol bits DR (0:2) are bits 0 through 2 of configuration register ADDR 18 (0:2). Table 7 gives clock rates for data rates from 156·25 kb/s to 1000kb/s. NOTES * External oscillator is not required if CLK is used. If both CLK and E_CLK are used, any system clock rate up to 32MHz can be obtained. ** CLK is required in addition to E_CLK to ensure correct DE6003 timing. *** Represents a minimum E_CLK rate. E_CLK = C_CLK3N (not to exceed 32MHz) can be used if a higher system clock rate is required. Clock must be confirmed with internal clock. System clock rate B_CLK (MHz) Required*** Data rate oversampling (kb/s) clock rate C_CLK (MHz) 1000 625* 500 312·5* 250 156·25* 16 10 8 5 4 2·5 32/16/10/8/4** 10* 32/16/10/8/4/2** 10* 32/16/10/8/4/2/1** 10* Table 7 CK800N CK400N 48 DIVIDER 44 6 42 5 TO DIVERSITY CONTROLLER AND BATTERY MONITOR 4 48 3 DIVIDER 44 2 42 1 7-T0-1 MUX C_CLK 0 TEST (INTERNALLY TIED TO GND) MUX 1 DR2 DR1 DR0 0 10 E_CLK CLKEN CLK 11 CLK RCV 4-T0-1 B_CLK 01 MUX C10MHz 00 CKSEL (0) CKSEL (1) Fig. 14 Clock selector/generator WL100 CLOCK SPEED. The WL100 is designed to operate with one or two clock sources CLK and E_CLK. CLK is primarily used tor oversampling of the data at 625, 312.5 or156.25 kb/s. In addition, the CLK signal is required for operation of the DE6003 control signals. If an external clock signal (E_CLK) other than 10MHz is used then the CLK clock input must still have a 10MHz clock applied from the DE6003 in order for the DE6003 interface timing to be correct. Timing problems can also arise if the MAC controller uses a different clock source other than the one used to generate B_CLK. If this is the case and asynchronous clocks are used, the signals from the MAC controller should be re-timed with B_CLK (see Fig. 17) E_CLK allows the WL100 to be interfaced to microcontrollers with different data bus clock speeds. CLK, supplied from the DE6003, is still required for proper DE6003 control signal timing. The maximum clock speed for E_CLK is 32 MHz. The B_CLK rate is programmable and is based on the E_CLK rate (see Fig 14). 11 WL100 Pin Pin Type 1 2 3 4 5 6 7 10 8,24,41,51,61 9,23,40,53 11 12 13 14 15 16 17 18 19 20 21 22 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 44 45 46 47 48 42 43,49,50,56,57,63,64 52 54 55 58 59 60 62 B_DATA0 B_DATA1 B_DATA2 B_DATA3 B_DATA4 B_DATA5 B_DATA6 B_DATA7 VSS VDD B_ADDR0 B_ADDR1 B_ADDR2 B_ADDR3 B_ADDR4 CS RD WR RESET CKSEL1 CKSEL0 E_CLK B_CLK C_CLK TEST ATSTIN ATSTOUT XCKT RXD SYNLOK PAOFF PWRLO RX/TX TXD LOADB SD6 SD5 SD4 SD3 SD2 SD1 SD0 CLK NC ANTSEL STDBY VREF RSSI SHCAP VBAT IRQ I/O I/O I/O I/O I/O I/O I/O I/O GND 15V I I I I I I I I I I I I O O I I O O I I O O O O O O O O O O O O A O O A A A A OD Description Data Bus, bit 0 Data Bus, bit 1 Data Bus, bit 2 Data Bus, bit 3 Data Bus, bit 4 Data Bus, bit 5 Data Bus, bit 6 Data Bus, bit 7 Ground Positive supply Address Bus, bit 0 Address Bus, bit 1 Address Bus, bit 2 Address Bus, bit 3 Address Bus, bit 4 Chip select (active low) Read cycle (active low) Write cycle (active low) Power on reset (active low) Clock source select, bit 1 Clock source select, bit 0 External clock, 100 ppm stability System clock output Oversampling clock (test output) Device test, normally tied to GND Used for a device test, internally tied to GND Used for a device test Recovered or transmit clock (test output) Receive data input Lock monitor (locked when low) Turns off transmit power amp. (active low) Power level control (low when zero) Controls the radio mode (receive when high) Transmit data output Channel select load pulse (active low) Channel select code, bit 6 Channel select code, bit 5 Channel select code, bit 4 Channel select code, bit 3 Channel select code, bit 2 Channel select code, bit 1 Channel select code, bit 0 10MHz low level clock from DE6003 No connection Diversity switch control (Selects ANT1 when low) Standby mode (active low) Reference voltage 1·23V Receive signal strength indicator (0V to 5V range, 0·4V to 2·4V linear) Sample and hold capacitor input (requires external 50pF capacitor to ground) Battery voltage, 2·8V to 5·0V range (requires external 1kV series resistor) Interrupt to the Controller (active low). Requires a 10kV pullup resistor to drive the signal high. Table 8 WL100 pin descriptions NOTES I = Input to WL100 O = Output from WL100 OD = Output from WL100 with external pull-up resistor A = Analog input 12 WL100 ELECTRICAL CHARACTERISTICS The Electrical Characteristics are guaranteed over the following range of operating conditions, unless otherwise stated: TAMB = 0°C to 170°C, VDD = 5V±10% Static Characteristics Value Characteristic Units Min. Typ. CLK Input impedance Bias Input current 0·25 2·5 1·0 All Other Inputs Input voltage low Input voltage high 2·0 300 1·25 All Other Inputs Input current All Outputs Output voltage low Output voltage high 0·2 0·8VDD 0·9VDD RXD, E_CLK Input hysteresis, rising Input hysteresis, falling V V VIN = VDD 61 µA VIN = VDD or VSS 0·4 V V IOL = 6mA IOH = 26mA V V VIL to VIH VIH to VIL µA VOUT = VDD or VSS 61 67 37 V V mA mA 3·1 1·9 IRQ Leakage current All Outputs Short circuit current 1·6 0·8 CKSEL (1:0), E_CLK, TEST, ATSTIN Input current Conditions Max. 270 150 mA VDD = VOUT = 15·5V mA VDD = 15·5V, VOUT = 0V µA/MHz Excluding peripheral buffers Operating Current 135 75 1 All Inputs Input capacitance 3 pF Excluding package leadframe capacitance of bidirectional pins All Outputs Output capacitance 4 pF Excluding package leadframe capacitance of bidirectional pins All Bidirectional Pins Capacitance 5 pF Excluding package leadframe 40 5 mA mA Transmit/Receive at 625kb/s Standby (STDB = 0) 5·0 3·7 V V Power Supply Current VBAT Voltage range (full) Voltage range (linear) 2·8 2·8 13 WL100 Dynamic Characteristics (see Figs. 15 and 16) Value Characteristic Symbol Units Min. Data rate Conditions Typ. Max. 156·25 1000 kb/s Jitter tolerance 37·5 % IRQ low to FIFO full/empty 160 B_CLK cycles ADC linearity, accuracy 0·5 LSB 2 µs 0·4 2·4 V 1 32 MHz ADC conversion time RSSI input range B_CLK frequency I/O address to RD low (t1) RD low to valid data (t2) 25 16 C_CLK (MHz) to B_CLK (MHz) = 4:1, FL = 3 VREF = 1·23V VREF = 1·23V ns See Fig. 15 ns See Fig. 15 B_DATA set-up to WR low (t3) 0 ns See Fig. 15 I/O address to WR (t4) 25 ns See Fig. 15 RD duration (t5) 2 B_CLK cycles See Fig. 15 WR duration (t6) 2 B_CLK cycles See Fig. 15 DE6003 channel hop time (t7) LOADB pulse width (t8) 80 1 µs See Fig. 16 and Note 1 µs See Fig. 16 Diversity decision time (t9) µs See Fig. 16 RX/TX low to PAOFF high (t10) 1 µs See Fig. 16 PAOFF high to transmit data (t11) 4 µs See Fig. 16 PAOFF low to RX/TX high (t12) 4 µs See Fig. 16 WR to B_DATA hold time (t13) 20 ns See Fig. 15 RD to B_DATA hold time (t14) 14 ns See Fig. 15 9·6 NOTE 1. Channel hop time, t7, is specified here as 80µs (typ.) to be consistent with DE6003 requirements. I/O READ CYCLE I/O WRITE CYCLE I/O ADDRESS I/O ADDRESS B_CLK CS, ADDR B_DATA READ DATA t2 WRITE DATA t14 RD t3 t1 t13 t5 WR t1 = t4 = 25ns t2 = 16ns (MAX) t3 = 0ns (MIN) t5 = t6 = 2 B_CLK CYCLES (MIN) t4 Fig. 15 Typical controller bus timing 14 t6 WL100 CH * SD (6:0) * LOADB t7 t8 t9 CD * CR * NOISE RXD RECEIVE DATA SYDN ** NS ** CT ** RX/TX t10 t12 PAOFF t11 TXD DATA HOP TO CHANNEL A DIVERSITY SENSE CHAN A NOISE TRANSMIT CHANNEL A HOP TO CHANNEL B DIVERSITY RECEIVE CHANNEL B * CONTROL BITS ** STATUS BITS Fig. 16 Timings for WL100 primary operation modes (not to scale) READ FIFO DATA B_CLK RD_FIFO = CS • RD • (B ADD = 0C) RD_FIFO_LATCHED FIFO POINTER DECREMENTED (NOTE 1) WRITE FIFO DATA Note 1. In asynchronous systems, when the system clock differs from the ones specified in Table 7, the width of these pulses may become negligible and the FIFO will fail to increment/decrement. To avoid these race hazards all controller to WL100 signals could be re-synchronised to B_CLK, but this would take a large amount of hardware. In most applications re-synchronising the read/write strobes should be sufficient, the relationship between the delayed and resynchronised RD and WR strobes to CS, ADDR and DATA should be checked. A resynchronising circuit is shown below. B_CLK RD (WR) D Q D Q RD (WR) WR_FIFO = CS • WR • (B ADD = 0C) WR_FIFO_LATCHED FIFO POINTER INCREMENTED (NOTE 1) B_CLK RD and WR re-synchronising circuit Fig. 17 Read and Write synchronising 15 WL100 RSSI (V) DV (4:0) RSSI (V) DV (4:0) RSSI (V) DV (4:0) RSSI (V) DV (4:0) 0·00 0·03 0·11 0·19 0·27 0·36 0·42 0·50 00000 00001 00010 00011 00100 00101 00110 00111 0·58 0·65 0·73 0·81 0·89 0·96 1·04 1·12 01000 01001 01010 01011 01100 01101 01110 01111 1·20 1·27 1·35 1·43 1·51 1·58 1·66 1·74 10000 10001 10010 10011 10100 10101 10110 10111 1·82 1·89 1·97 2·05 2·13 2·20 2·28 2·36 11000 11001 11010 11011 11100 11101 11110 11111 Table 9 RSSI values NOTE : Variation in RSSI values between DE6003 transceivers can be up to 5dB. VBAT (V) BT (4:0) BT (4:0) <2·83 2·83 2·92 3·00 3·07 3·15 3·22 3·30 3·37 3·45 3·52 3·60 3·67 >3·75 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 - Non-linear ±200mV Non-linear Table 10 Battery level monitoring values 16 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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