CUSTOMER PROCUREMENTSPECIFICATION 216COl/CO2 CPUCENTRALPROCESSINGUNIT FEATURES Part Zi 6COl Z16CO2 Memory Address 8 Mbytes 64 Kbytes Memory Extension 48 Mbytes 384 Kbytes Speed (MHz) 10 10 H Extendable Register Files 1 Nine Basic Instruction Types n 40/48-Pin PDIP and 44-Pin PLCC Packages’ n Eight User-Selectable Addressing Modes n +4.5 I V,, I +5.5-Volt Operating Range n Seven Data Types n Low-Power CMOS H Supports Three Interrupt Types and Four Traps n 0°C to +70°C Temperature Range n RISC-Like Load/Store Architecture GENERAL DESCRIPTION The Z16COl/CO2 CPU are members of the 16-bit processor and controller family. Designed using a RISC-like Load/Store architecture, the CPU can operate in either system or normal modes, permitting privileged operations and improving operating system organization and implementation. The processor’s resources include seven data types that range from bits to 32-bit long words, and byte and word strings, plus eight user-selectable addressing modes. The nine basic instruction types can be combined with various data types and addressing modes to form a powerful set of 414 instructions. To boost the main CPU’s performance capability, the processor core includes hardwired control and is a 16-bit real-time processor functioning at register access speeds. Register flexibility is created by grouping or overlapping multiple registers, and by allowing extended register file capabilities as the system expands. Easy extended register file control is accomplished through a single instruction stream communication. The extended processing architecture features provide a modular approach to expanding both the hardware and software capabilities of the Z16COl/CO2. TheCPUsupportsthreetypesof interrupts (non-maskable, vectored, and non-vectored) and four traps (system call, extended process architecture instruction, privileged instructions, and segmentation trap). The vectored and non-vectored interrupts are maskable. cPs95scc0103 (3/95) Notes: All Signals with a preceding front slash, “/“, are active Low, e.g.: B/AN(WORDis active Low); /B/W^(BYTE is active Low, only). Powerconnections follow conventionaldescriptions below: Connection Circuit Device Power Ground “cc GND V DO “ss 1 216CWCO2 +cPs95sccolo3 ~ziLfli5 GENERAL DESCRIPTION (Continued) Z-Bus internal Data Bus 0 Z16COO CPU Functional Block Diagram AD13 c) AD14 c) AD13 c) AD12 c) AD11 c) REAMWRITE hwlM4u/sYsTEM BYTEWORD 3laius ST1 ADi ,AM).AD? ,c) A06 .A& - ~573 ~ST2 AD10 c) zid~i YBw” AM .- 3m A03 .- A02 .AD1 ,- IWAlT /STOP AW - iNMI lnlemlpN M INVI : : sN4 sN2 : : sN2 SNl Z16COVCO2 Signal Descriptions 2 Z-Bus Interface Z16COlKO2 cPs95scc0103 PIN DESCRIPTION AD6 SN6 SN5 AD7 AD6 AD4 SN4 AD5 AD3 iD2 AD1 sN2 GND CLOCK IAS NIC ww Nils WIW BUSACK IWAIT /BUSREP SNO 216CO2 40-Pin PDIP SNI 216COl 46-Pin PDIP Z16CO2 44-Pin PLCC 3 Z16COlKO2 + cPs95scc0103 ABSOLUTE MAXIMUM RATINGS Voltages on V,, with respect to V,, . ... . .. .. . . .. .-0.3V to +7.OV Voltages on all inputs with respect to Vss........““............................................. -0.3V to V,,+O.3V Storage Temperature.. .... ...... .... .. ..... .... .. ... .-65”C to + 150% Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operating of the device at any condition above these indicated in the operational sectionsof these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. STANDARD TEST CONDITIONS The DC characteristics below apply for the following test conditions, unless otherwise noted. All voltages are referenced to GND (OV). Positive current flows into the referenced pin. All AC parameters assume a total load capacitance (including parasitic capacitances) or 100 pf max, except for parameter 6 (50 pf max). Timing reference between two output signals assume a load difference of 50 pf max. Available operating temperature ranges are: The Ordering Information section lists package temperature ranges and product numbers. s = 0°C to +7O”C, + 4.5v s V,,I (Z16COi,Zl6CO2) + 5.5v E = -4OOC to +lOO”C, + 4.5V IV& (Z16CO1, Zi 6CO2) + 5.5V DC CHARACTERISTICS SYm VCH VCL Parameter ClockinputHighVoltage ClockinputLowVoltage InputHighVoltage VI, V,, RESET InputHighVoltageon /RESETPin V,, NMI InputHighVoltageon NMI Pin InputLowVoltage Vi, VOH OutputHighVoltage VOL OutputLowVoltage I InputLeakage I\ SEGT InputLeakageon /SEGTPin IOL OutputLeakage V,, PowerSupplyCurrent ICC 4 MIN MAX v&I.4 -0.3 2.0 2.4 2.4 -0.3 2.4 v,,to.3 0.45 v,,to.3 v,$o.3 v,,tD.3 0.8 -100 0.4 L-10 100 *lo 35 Units Condition v v v v v V V Drivenby ExternalClockGenerator Drivenby ExternalClockGenerator I”J\ f#I p4 rnA b:4;‘:$ I,,=-250uA +2.4V 0.4V< VIN< t2.4V 10MHz Z16GOllCO2 cPs95sccolo3 piu3E ’ FOOTNOTES TO AC CHARACTERISTICS ZlGCOlR 10 MHz Equation No. Symbol 11 13 16 17 19 TdA(DR) TdDS(A) TdDW(DS) TdA(MR) TwMRh 20 21 22 25 27 TdMR(A) TdDW(DSW) TdMR(DR) TdA(AS) TdAS(DR) TwCI-20ns TwCh-25ns 2TcC-60ns TwCh-20ns 2TcG60ns 28 29 30 32 33 TdDS(AS) TwAS TdAS(A) TdAS(DSR) TdDSR(DR) TwCI-20ns TwCh-5n.s TwCI-7Ons TwCEns TcCtTwCh-6Ons ’ 2TcCtTwCh-6On.s TwClt5ns TcCtTwCh-3Ons TwCh-20ns TcC-20ns _ * 35 36 38 40 41 TdDS(DW) TdA(DSR) TwDSR TwDSW TdDSI(DR) TwCI-15ns TcC-35ns TcCtTwCh-3Ons TcC-25n.s 2TcC-80ns 43 44 46 48 68 69 TwDS TdAS(DSA) TdDSA(DR) TdS(AS) TWA TdDS(s) 2TcC-40ns 4TcCtTwCI-30ns 2TcCtTwCh-75ns TwCh-20ns TcCSOns TwCI-1Ons ACTimingTestConditions: VoL=0.8V VOH= 2.ov 'I,,= 0.8V V,,= 2.4V v,,, =0.45v yHc= v,, - 0.4v , Zl6COlKO2 cPs95sccolo3 AC CHARACTERISTICS No. Symbol 1 2 3 4 5 6 7 8 9 TcC ClockCycleTime TwCh ClockWidth(High) TwCl ClockWidth(Low) ClockFallTime TfC TrC ClockRiseTime TdC(SNv) Clock+SegmentNumberValid(50pfload) TdC(SNn) Clocktsegment NumberNotValid TdC(Bz) , Clockt Bus Float TdC(A) ClocktAddressValid 10 11 12 13 14 15 16 1.7 18 19 TdC(Az) TdA(DR) TsDR(C) TdDS(A) TdC(DW)’ ThDR(DS) TdDW(DS) TdA(MR) TdC(MR) TwMRh 20 21 22 23 24 25 26 27 28 29 TdMR(A) /MREQ[ AddressNotActive TdDW(DSW)WriteDataValidto /DS Fall(Write)Delay TdMR(DR) /MREQ[ReadDataRequiredValid ClockFall/MREQRiseDelay TdC(MR) TdC(ASf) Clock+ /AS Fall Delay AddressValidto /AS RiseDelay TdA(AS) TdC(ASr) Clock[ /AS RiseDelay TdAS(DR) /AS + ReadDataRequiredValid TdDS(AS) /DS + /AS Fall Delay TwAS /AS Width(Low) 30 31 32 33 34 35 36 37 38 39 /AS t AddressNotActiveDelay TdAS(A) TdAz(DSR) AddressFloatto /DS (Read)FallDelay TdAS(DSR) /AS t /DS (Read)FallDelay TdDSR(DR) /DS (Read)Fallto ReadDataRequiredValid TdC(DSr) ClockFallto /OS RiseDelay TdDS(DW) /DS + WriteDataNotValid TdA(DSR) AddressValidto /DS (Read)FallDelay TdC(DSR) ClockRise/DS (Read)FallDelay TwDSR /DS (Read)Width(Low) TdC(DSWj ClockFallto /DS (Write)FallDelay 40 41 42 43 44 45 46 47 TwDSW TdDSI(DR) TdC(DSf) TwDS TdAS(DSA) TdC(DSA) TdDSA(DR) TdC(S) 6 Parameter Clock+ AddressFloat AddressValidto ReadDataRequiredValid ReadDatato ClockFallSetupTime /DStAddressActive Clock+ WriteDataValid ReadDatato /DS RiseHoldTime WriteDataValidto /DS RiseDelay AddressValidto /MREQFallDelay ClockFallto /MREQFallDelay /MREQWidth(High) /DS (Write)Width(Low) /DS (l/O) [ ReadDataRequiredValid Clock [ /DS (l/O) FallDelay /DS (l/O) Width(Low) /AS t /DS (Acknowledge) FallDelay Clock+ /DS (Acknowledge) FallDelay /DS (Acknowledge) [ ReadDataRequiredDelay ClockRiseto StatusValidDelay 216CO1/2 10 MHz Min Max 100 40 40 ** ** ** 10 10 50 0 50 50 50 180 20 45* 60 0 110* 20 50 80 20 15* 140* 50 35 20 25 140 20* 35* 30 0 35* 80 30 25* 65* 45 110* 45 75* 120* 45 160 410* 45 165* 50 I Zl6COllCO2 cPs95sccolo3 ~ZllJJE AC CHARACTERISTICS (Continued) 216CO112 10 MHz Min Max No. Symbol Parameter 48 49 50 51 52 53 54 TdS(AS) TSR(C) ThR(C) TwNMl TsNMI(C) TsVI(C) ThVI(C) StatusValidto /AS RiseDelay /RESET to ClockRiseSetupTime /RESET to ClockRiseHoldTime /NMI Width(Low) /NMIto ClockRiseSetupTime /VI, /NVIto ClockRiseSetupTime /VI, /NVIto ClockRiseHoldTime 55 56 57 58 59 60 61 TsSGT(C) ThSGT(C) TsMI(C) ThMI(C) TdC(M0) TsSTP(C) ThSTP(C) /SEGTto ClockRiseSetupTime /SEGTto ClockRiseHoldTime /Mt to ClockRiseSetupTime /MI to ClockRiseHoldTime . ClockRiseto /MO Delay /STOPto ClockFallSetupTime /STOPto ClockFallHoldTime 35 10 35 0 62 63 64 65 66 67 68 69 TsW(C) ThW(C) TsBRQ(C) ThBRQ(C) TdC(BAKr) TdC(BAKf) TWA TdDS(S) /WAITto ClockFallSetupTime /WAITto ClockFallHoldTime /BUSREQ to ClockRiseSetupTime /BUSREQ to ClockRiseHoldTime, ClockRiseto /BUSACKRiseDelay ClockRiseto /BUSACKFallDelay AddressValidWidth /DS Riseto STATUSNotValid 20 5 35 5 , 20* 35 0 35 35 35 10 50 35 0 35 35 ,. 50* 30 * Clock-cycletime-dependent characteristics. SeeFootnotesto AC Characteristics. ** Clockmaybe stopped. t Unitsin nanoseconds (ns). ” ,“ 7 -- @ziuE Zl6COllCO2 cPs95sccolo3 COMPOSITE AC TIMING DIAGRAM This composite liming dia. gram does not show actual timing sequences. Refer to this diagram only for the detailed timing relationships of indiwdual edges. Use the precedtng illustrations as an exolanation of the various iitiing sequences. Trming measurements are made al the followrng voltages. U.^. I ^... Clock oulput input FlOal DATAIN n I Y-READ INTERRUPT ACKNOWLEWE Composite AC liming 6 4.ov 2.ov 2.ov V D.8V 0.8V 0.8V rD.5V 216COllCO2 cPs95scc0103 TIMING DIAGRAMS i -5 \ i I 1 I I I .E .-E I% 8 u 216COllCO2' cPs95scc0103 TIMING DIAGRAMS (Continued) ’ WAIT CTCLES ADDEC (-‘“) C .I 8s IUWT I uw IDIWT . . x II ‘co(lT ADDRESS DATA OUT II J w OUTWT Y-t-t10 I I Input/Output Timing T L Z16COVCO2 cPs95sccolo3 TIMING DIAGRAMS (Continued) maL i . @b-we i u. $c Ix II Y < 191 Interrupt and Segment Trap Request/Acknowledge liming - 11 Z16COlKO2 cPs95scc0103 TIMING DIAGRAMS (Continued) 4 CLOCU AH CVCLLS ADDED iiD Iii / AD MAD YDW ABMESS )-- (Z) S MAO ns WNHE I Memory Read and Write Timing Zi 6COWO2 cPs95scc0103 TIMING DIAGRAMS (Continued) AVWLL- -E ;.. ;.. JJ // AD Bus Request/Acknowledge Timing 13 Zl6COl/C42 * ; cPs95sccolo3 ’ TIMING DIAGRAMS (Continued) ’ r Stop Timing 0 1995 byzilog, Inc. All rights reserved. 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