NTE3881 Integrated Circuit NMOS, Parallel I/O Interface (PIO), 4MHz Description: The NTE3881 Parallel I/O Circuit (PIO) is a programmable, two port device which provides a TTL compatible interface between peripheral devices and the NTE3880. The Central Processing Unit (CPU) can configure the NTE3881 to interface with a wide range of peripheral devices with no other external logic required. Typical peripheral devices that are fully compatible with the NTE3881 include most keyboard, paper tape readers and punches, printers, PROM programmers, etc. The NTE3881 utilizes N channel silicon gate depletion load technology and is packaged in a 40–Lead DIP type package. Features: D Two Independent 8–Bit Bidirectional Peripheral Interface Ports with “Handshake” Data Transfer Control D Interrupt Driven “Handshake” for Fast Response D Any One of Four Distinct Modes of Operation may be Selected for a Port, including: Byte Output Byte Input Byte Bidirectional Bus (Available on Port A Only) Bit Control Mode D All with Interrupt Controlled Handshake D Daisy Chain Priority Interrupt Logic Included to Provide for Automatic Interrupt Vectoring without External Logic D Eight Outputs are Capable of Driving Darlington Transistors D All Inputs and Outputs Fully TTL Compatible D Single 5 Volt Supply and Single Phase Clock Required Absolute Maximum Ratings: Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Voltage On Any Pin With Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6W Note 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics: (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Clock Input Low Voltage VILC –0.3 – 0.80 V Clock Input High Voltage VIHC VCC–0.6 – VCC+3 V Input Low Voltage VIL –0.3 – 0.8 V Input High Voltage VIH 2.0 – VCC V Output Low Voltage VOL IOL = 2.0mA – – 0.4 V Output High Voltage VOH IOH = –250µA 2.4 – – V Power Supply Current ICC – – 70 mA Input Leakage Current IL1 VIN = 0 to VCC – – ±10 µA Tri–State Output Leakage Current in Float ILOH VOUT = 2.4 to VCC – – 10 µA Tri–State Output Leakage Current in Float ILOL VOUT = 0.4V – – –10 µA Data Bus Leakage Current in Input Mode ILD 0 ≤ VIN ≤ VCC – – ±10 µA –1.5 – – mA Min Typ Max Unit Darlington Drive Current IOHD VOH = 1.5V Port B Only Capacitance: (TA = +25°C, f = 1MHz unless otherwise specified) Parameter Symbol Test Conditions Clock Capacitance Cφ Unmeasured Pins – – 10 pF Input Capacitance CIN Input Capacitance – – 5 pF – – 10 pF Min Typ Max Unit 250 – – ns Output Capacitance COUT AC Characteristics: (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified) Parameter Symbol Test Conditions Clock Cycle Time TcC Note 1 Clock Width (High) TcCH 105 – 2000 ns Clock Width (Low) TcCL 105 – 2000 ns Clock Fall Time TfC – – 30 ns Clock Rise Time TrC – – 30 ns 50 – – ns CE, B/A, C/E, to RD, IORQ ↓ Setup Time TsCS(RI) Any Hold Time for Specified Setup Time Th 0 – – ns TsRI(C) 115 – – ns – – 380 ns – – 110 ns CL = 50pF 50 – – ns Note 4 250 – – ns RD, IORQ to Clock ↑ Setup Time RD, IORQ ↓ to Data Out Delay TdRI(DO) RD, IORQ ↑ to Data Out Float Delay TdRI(DOr) Data In to Clock ↑ Setup Time TsDI(C) Note 2 Note 3 IORQ ↓ to Data Out Delay (INTA Cycle) TdIO(DOI) M1 ↓ to Clock ↑ Setup Time TsM1(Cr) 90 – – ns M1 ↑ to Clock ↓ Setup Time (M1 Cycle) TsM1(Cf) 0 – – ns Note 1 TcC = TwCh + TwCI + TrC + TfC. Note 2. TsCS(RI) may be reduced. However, the time subtracted from TsCS(RI) will be added to TdR(DO). Note 3. Increase TdRI(DO) by 10ns for each 50pF increase in loading up to 200pF max. Note 4. Increase TdIO(DOT) by 10ns for each 60pF increase in loading up to 200pF max. AC Characteristics (Cont’d): (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified) Parameter Symbol M1 ↓ to IEO ↓ Delay (Interrupt Immediately Preceding M1) TdM1(IEO) IEI to IORQ ↓ Setup Time (INTA Cycle) TsIE(IO) Test Conditions Note 5, Note 6 Note 6 Min Typ Max Unit – – 190 ns 140 – – ns IEI ↓ to IEO ↓ Delay TdIEI(IEO) CL = 50pF, Note 5 – – 130 ns IEI ↑ to IEO ↑ Delay (after ED Decode) TdIE(IIOr) Note 5 – – 160 ns 220 – – ns IORQ ↑ to Clock ↓ Setup Time (To Activate READY on Next Clock Cycle) TsIO(C) Clock ↓ to Ready ↑ Delay TdC(RDYr) CL = 50pF, Note 5 200 – – ns Clock ↓ to Ready ↓ Delay TdC(RDYf) Note 5 150 – – ns TwSTB Note 4 150 – – ns 200 – – ns – – 180 ns 230 – – ns – – 210 ns – – 180 ns STROBE Pulse Width STROBE ↑ to Clock ↓ Setup Time (To Activate READY on Next Clock Cycle) TsSTB(C) IORQ ↑ to PORT Data Stable Delay (Mode 0) TdIO(PD) Note 5 PORT DATA to STROBE ↑ Setup Time (Mode 1) TsPD(STB) STROBE ↓ to PORT DATA Stable (Mode 2) TdSTB(PD) STROBE ↑ to PORT DATA Float Delay (Mode 2) TdSTB(PDz) CL = 50pF Note 5 PORT DATA Match to INT ↓ Delay (Mode 3) TdPD(INT) – – 490 ns STROBE ↑ to INT ↓ Delay TdSTB(INT) – – 440 ns Note 4 For Mode 2: tW(ST) > tS(PD) Note 5 Increase these values by 2nsec for each 10pF increase in loading up to 100pF max. Note 6. 2.5 TcC > (N–2) TdIEI (IEOG) + TdM1(IEO) + TsIE(IO) + TTL Buffer Delay, if any. Pin Connection Diagram D2 D7 D6 Chip Enable Control Data Select Port B/A Select A7 A6 A5 A4 GND A3 A2 A1 A0 A STB B STB A RDY D0 D1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 D3 D4 D5 M1 IORQ RD B7 B6 B5 B4 B3 B2 B1 B0 (+) 5V System Clock Input IEI INT IEO B RDY 40 21 1 20 2.055 (52.2) .550 (13.9) Max .155 (3.9) .100 (2.54) .019 (0.5) .137 (3.5) .650 (16.5)