ZILOG Z16C32IUSC

P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
PRELIMINARY PRODUCT SPECIFICATION
Z16C32
IUSC™ INTEGRATED UNIVERSAL
SERIAL CONTROLLER
FEATURES
■
Two Full-Capacity 20 MHz DMA Channels, Each with
32-Bit Addressing and 16-Bit Data Transfers.
■
DMA Modes Include Single Buffer, Pipelined, ArrayChained and Linked-Array Chained.
■
Ring Buffer Feature Supports Circular Queue of Buffers
in Memory.
■
Linked Frame Status Transfer Feature Writes Status
Information for Received Frames and Reads Control
Information for Transmit Frames to the DMA Channel’s
Array or Linked List to Significantly Simplify Processing
Frame Status and Control Information.
■
Programmable Throttling of DMA Bus Occupancy in
Burst Mode with Bus Occupancy Time Limitation.
■
0 to 20 Mbit/sec, Full-Duplex Channel, with Two Baud
Rate Generators and a Digital Phase-Locked Loop for
Clock Recovery.
■
32-Byte Data FIFOs for Receiver and Transmitter
■
Up to 12.5 MByte/sec (16-Bit) Data Bus Bandwidth
■
Multiprotocol Operation Under Program Control with
Independent Mode Selection for Receiver and
Transmitter.
■
Async Mode with One-to-Eight Bits/Character, 1/16 to
Two Stop Bits/Character in 1/16 Bit Increments; 16x,
32x, or 64x Oversampling; Break Detect and
Generation; Odd, Even, Mark, Space or No Parity and
Framing Error Detection. Supports 9-Bit and MIL-STD1553B Protocols.
■
HDLC/SDLC Mode with 8-Bit Address Compare;
Extended Address Field Option; 16- or 32-Bit CRC;
Programmable Idle Line Condition; Optional Preamble
Transmission and Loop Mode. Selectable Number of
Flags Between Back-to-Back Frames.
■
Byte Oriented Synchronous Mode with One-to-Eight
Bits/Character; Programmable Sync and Idle Line
Conditions; Optional Receive Sync Stripping; Optional
Preamble Transmission; 16- or 32-Bit CRC; Transmitto-Receive Slaving (for X.21).
■
External Character Sync Mode for Receive
■
Transparent Bisync Mode with EBCDIC or ASCII
Character Code; Automatic CRC Handling;
Programmable Idle Line Condition; Optional Preamble
Transmission; Automatic Recognition of DLE, SYN,
SOH, ITX, ETX, ETB, EOT, ENQ and ITB.
■
Flexible Bus Interface for Direct Connection to Most
Microprocessors; User Programmable for 8 or 16 Bits
Wide. Directly Supports 680X0 Family or 8X86 Family
Bus Interfaces.
■
Receive and Transmit Time Slot Assigners for ISDN,
T1 and E1 (CEPT) Applications.
■
8-Bit General-Purpose Port with Transition Detection
■
Low Power CMOS
■
68-Pin PLCC Package
■
Electronic Programmer's Manual Support Tool and
Software Drivers are Available.
GENERAL DESCRIPTION
The Z16C32 IUSC™ (Integrated Universal Serial Controller)
is a multiprotocol datacommunications device with onchip dual-channel DMA. The integration of a high-speed
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serial communications channel with high-performance
DMA facilitates higher data throughput than can be
achieved with discrete serial/DMA chip combinations.
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P R E L I M I N A R Y
Z16C32 IUSC™
GENERAL DESCRIPTION (Continued)
There are additional reasons for using the Z16C32 IUSC
than just reduced chip count and board space economy.
The DMA and serial channel intercommunication offers
application benefits as well. For example, events such as
the reception of the end of a HDLC frame is internally
communicated from the serial controller to the DMA so that
each frame can be written into a separate memory buffer.
The buffer chaining capabilities, ring buffer support, automated frame status/control blocks, and buffer termination
at the end of the frame combine to significantly reduce
CPU overhead (Figure 1).
The IUSC is software configurable to satisfy a wide variety
of serial communication applications. The 20 Mbit/second
data rate and multiple protocol support make it ideal for
applications in today’s dynamic environment of changing
specifications and increasing speed. The many programmable features allow the user to tune the device response
to meet system requirements and adapt to future requirements. The IUSC contains a variety of sophisticated internal functions including two baud rate generators, a digital
phase-locked loop, character counters, and 32-byte FIFOs
for both the receiver and the transmitter.
The on-chip DMA channels allow high speed data transfers for both the receiver and the transmitter. The IUSC
supports automatic status and control transfer through
DMA and allows initialization of the serial controller under
DMA control. Each DMA channel can do a 16-bit transfer
in as little as three 50 ns clock cycles and can generate
addresses compatible with 32-, 24- or 16-bit memory
ranges. The DMA channels operate in any of four modes:
single buffer, pipelined, array-chained, or linked-list. The
array-chained and linked-list modes provide scatter-read
and gather-write capabilities with minimal software intervention. To prevent the DMA from holding bus mastership
too long, mastership time may be limited by counting the
absolute number of clock cycles, the number of bus
transactions, or both.
The CPU bus interface is designed for use with any
conventional multiplexed or non-multiplexed bus from
manufacturers of CISC and RISC processors including
Intel, Motorola, and Zilog. The bus interface is configurable
for 16-bit data, 8-bit data with separate address or 8-bit
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data without separate address to support multiplexed or
non-multiplexed busses.
The IUSC handles asynchronous formats, synchronous
bit-oriented formats such as HDLC and synchronous byteoriented formats (e.g., BISYNC and DDCMP). This device
supports virtually any serial data transfer application.
The IUSC can generate and check CRC in any synchronous mode. Complete access to the CRC value allows
system software to resend or manipulate the CRC as
needed in various applications. The IUSC also provides
facilities for modem control signals. In applications where
these controls are not needed, the modem controls can be
used for general-purpose I/O.
Interrupts are supported by a daisy-chain hierarchy within
the serial channel and between the serial channel and the
DMA. Separate interrupt vectors for each type of interrupt
within the serial controller and the DMA facilitate fast
discrimination of the interrupt source. The IUSC supports
Pulsed, Double Pulsed, and Status Interrupt Acknowledge
cycles.
Support tools are available to aid the designer in efficiently
programming the IUSC. The Technical Manual describes
in detail all the features and gives programming sequence
hints. The Electronic Programmer's Manual, DC #8287-02,
is an MS-DOS, disk-based programming initialization tool
that can generate custom sequences. Also, Zilog offers
assorted application notes and development boards to
assist the designer in hardware and software development. Contact your nearest Zilog representative for additional information.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
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P R E L I M I N A R Y
ZILOG
Host
Processor
Bus
Interface
Z16C32 IUSC™
16-Bit Internal Data Bus
Transmit
DMA
Interrupt
Control
Receive
DMA
Transmit
FIFO
Receive
FIFO
Serial Clock
Logic
Transmitter
Time Slot
Assigner
DPLL
Counters
BRG0, BRG1
Receiver
Time Slot
Assigner
I/O
Port
Figure 1. Z16C32 IUSC Block Diagram
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Z16C32 IUSC™
GENERAL DESCRIPTION (Continued)
TxD
RxD
/TxC
/RxC
/CTS
AD0
AD1
AD2
AD3
AD4
Address/
Data Bus
Bus
Timing
Control
Interrupt
AD13
AD14
AD15
/AS
/DS
/RD
/WR
/CS
S//D
D//C
R//W
/INTACK
/WAIT//RDY
GND
GND
GND
Ground
/DCD
/RxREQ
/ABORT
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
/BUSREQ
/TxREQ
B//W
/UAS
/INT
Z16C32
IEI
IEO
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
/BIN
/BOUT
CLK
/RESET
VCC
GND
GND
VCC
VCC
VCC
VCC
GND
GND
VCC
VCC
Serial
Data
Channel
Clocks
Channel
I/O
Channel
DMA
Interface
Channel
Interrupt
Interface
I/O Port
System Clock
Device Reset
Power
Figure 2. Z16C32 Pin Functions
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Z16C32 IUSC™
B//W
/WAIT//RDY
Reserved
S//D
D//C
/CS
/RESET
VCC
VCC
VCC
/AS
/DS
/RD
/WR
R//W
/INTACK
/UAS
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/ABORT
/INT
IEI
IEO
GND
VCC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
VCC
/RxREQ
1 68
61
10
60
IUSC
26
44
43
/TxREQ
/RxC
RxD
/DCD
/TxC
TxD
/CTS
GND
GND
GND
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
27
/BIN
/BUSREQ
CLK
/BOUT
GND
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
GND
VCC
PORT 7
Figure 3. Z16C32 68-Pin PLCC Pin Assignments
PIN DESCRIPTION
Figure 2 shows the logical pin groupings of the IUSC’s
pins, and Figure 3 shows the physical pin assignments.
Only one strobe pin (/DS, /RD, /WR or Pulsed INTACK)
should ever be active at one time. Any unused input pin (if
an input when the IUSC is bus master or slave) must be
pulled up to its inactive state.
/RESET Reset (input, active Low). A Low on this line
places the IUSC in a known, inactive state, and conditions
it so that the data, from the next write operation that asserts
the /CS pin, goes into the Bus Configuration Register
(BCR) regardless of register addressing. /RESET should
be driven Low as soon as possible during power-up, and
as needed when restarting the overall system or the
communications subsystem.
CLK System Clock (input). This signal is the timing reference for the DMA and bus interface logic. (The serial
controller section is clocked by the selected sources of
receive and transmit clocking.)
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AD15-0 Address/Data Bus (inputs/tri-state outputs). After
Reset, these lines carry data between the controlling
microprocessor and the IUSC, and may also carry multiplexed addresses of registers within the IUSC. Such operation, between the host processor and the IUSC, is often
called slave mode. Once the software has set up the
device and placed it into operation, these lines also carry
multiplexed addresses and data between the IUSC and
system memory; such operation is called master mode.
AD15-0 can be used in a variety of ways based on whether
the IUSC senses activity on /AS after Reset, and on the
data written to the Bus Configuration Register (BCR).
/CS Chip Select (input, active Low). A Low on this line
indicates that the controlling microprocessor’s current bus
cycle refers to a register in the IUSC. The IUSC ignores /CS
when a Low on /INTACK indicates that the current bus
operation is an interrupt acknowledge cycle. On a multiplexed bus the IUSC latches the state of this pin at rising
edges on /AS; on a non-multiplexed bus, it latches /CS at
leading/falling edges on /DS, /RD, or /WR.
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P R E L I M I N A R Y
Z16C32 IUSC™
PIN DESCRIPTION (Continued)
S//D Serial/DMA (input/tri-state output, input High indicates serial). Cycles with /CS Low, and /INTACK and this
pin both High, access registers in the serial controller
section. Cycles with /INTACK High, and /CS and this pin
both Low, access registers in the DMA controller section.
The state of this line when the Bus Configuration Register
is written determines wait vs acknowledge operation, as
described in the text. On a multiplexed bus, the IUSC
latches the state of this pin at rising edges on /AS; on a nonmultiplexed bus, it latches the state at leading/falling
edges on /DS, /RD, or /WR.
Software can program the IUSC so that when it is acting as
a bus master, it drives this line High to indicate a DMA cycle
for serial data and Low to indicate an “array” or “list”
access. (Array/list accesses read the address and length
of the next memory buffer.)
D//C Data/Control (input/tri-state output, input High indicates Data). A slave read cycle with /CS Low , and all three
of /INTACK, S//D, and this pin High, fetches data from the
serial controller’s receive FIFO through the Receive Data
Register (RDR). A slave write cycle with the same conditions writes data into the transmit FIFO through its Transmit
Data Register (TDR). Slave cycles with /INTACK and S//D
High, and /CS and this pin Low , read or write registers in
the serial controller. On a multiplexed bus, the IUSC
determines which register to access from the low-order AD
lines at the rising edge of /AS; on a non-multiplexed bus it
typically selects the register based on the Least Significant
Bits of the serial controller’s Channel Command/Address
Register. On a multiplexed bus, the IUSC latches the state
of this pin at rising edges on /AS; on a non-multiplexed bus
it latches the state at leading/ falling edges on /DS, /RD, or
/WR.
For slave cycles on a multiplexed bus, with /INTACK High
and both /CS and S//D Low, the state of this line at the rising
edge of /AS selects between the registers of the transmit
DMA channel (Low ) and those of the receive DMA channel
(High). On a non-multiplexed bus, with /INTACK High and
/CS and S//D both Low, the IUSC can take the DMA
channel selection from this line or from the DMA Command/Address Register.
Software can program the IUSC so that when it is acting as
a bus master, it drives this line High to indicate a DMA cycle
for the receiver and Low to indicate a cycle for the transmitter.
/AS Address Strobe (input/tri-state output, active Low).
After a reset, the IUSC’s bus interface logic monitors this
signal to see if the host bus multiplexes addresses and
data on AD15-0. If the logic sees activity on /AS before (or
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during) software writes to the Bus Configuration Register,
then in subsequent slave cycles directed to the IUSC,
it captures register selection from the AD lines, S//D, and
C//D on rising edges of /AS.
When the IUSC takes control of the bus and operates as a
master, it always uses the bus in a multiplexed fashion,
driving /AS Low when it places the least significant 16 bits
of an address on the AD15-0 lines. External devices can be
used to de-multiplex the address and data, if this is
necessary to match the characteristics of the host processor or host bus.
For a non-multiplexed bus, this pin should be pulled up to
+5V using a resistor of about 10 kOhms. If a processor
uses a non-multiplexed bus, yet has an output called
Address Strobe (e.g., 680x0 devices), this pin should not
be tied to the output.
/UAS Upper Address Strobe (tri-state output, active Low).
When the IUSC takes control of the bus and operates as a
master, it drives /UAS Low when it places the more significant 16 bits of an address on AD15-0. External memory
and other slave devices (or de-multiplexing latches) should
capture the MS address at each rising edge on this line.
R//W Read/Write control (input/tri-state output, Low signifies “write”). R//W and /DS indicate read and write cycles
on the bus, for host processors/buses having this kind of
signalling. When the IUSC has taken control of the bus and
is operating in master mode, this pin is an output that
remains valid throughout the Low time of /DS. In slave
cycles, the IUSC samples R//W at each leading/falling
edge on /DS.
/DS Data Strobe (input/tri-state output, active Low). R//W
and /DS indicate read and write cycles on the bus, for host
processors/buses having this kind of signalling. It is an
output when the IUSC has taken control of the bus and is
operating in master mode, otherwise, it is an input that is
qualified by /CS Low or /INTACK Low. In master mode, the
R//W line remains valid throughout the Low time of this line.
In slave mode, the IUSC samples R//W at each leading/
falling edge on this line. For slave write cycles and master
read cycles, the IUSC captures data at the rising (trailing)
edge on this line. For slave read cycles the IUSC provides
valid data on the AD lines within the specified access time
after this line goes Low , and keeps the data valid until after
the master releases this line to High. For master write
cycles, the IUSC places valid data on the AD lines before
it drives this signal to Low, and keeps the data valid until
after it drives this line back to High.
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/RD Read Strobe (input/tri-state output, active Low). This
line indicates a read cycle on the bus, for host processors/
buses having this kind of signalling. It is an output when the
IUSC has taken control of the bus and is operating in
master mode, otherwise, it is an input that is qualified by
/CS Low or /INTACK Low. For master read cycles, the IUSC
captures data at the rising (trailing) edge of this line. For
slave read cycles the IUSC provides valid data on the AD
lines within the specified access time after this line goes
Low, and keeps the data valid until after the master
releases this line to High.
/WR Write Strobe (input/tri-state output, active Low). This
line indicates write cycles on the bus, for host processors/
buses having this kind of signalling. It is an output when the
IUSC has taken control of the bus and is operating in
master mode, otherwise it is an input that is qualified by
/CS Low. For slave write cycles, the IUSC captures write
data at the rising (trailing) edge of this line. For master write
cycles, the IUSC places valid data on the AD lines before
it drives this signal to Low , and keeps the data valid until
after it drives this line back to High.
B//W Byte / Word Select (tri-state output, High indicates
8-bit transfer). When the IUSC takes control of the bus and
operates as a master, a High on this line indicates that a
byte is to be transferred, and a Low indicates that 16 bits
are to be transferred. The IUSC ignores this signal during
slave cycles: it takes the byte/word distinction from an AD
line at the rising edge of /AS, or from a bit in the serial or
DMA Command/Address Register.
/WAIT//RDY Wait, Ready, or Acknowledge handshaking
(input/tri-state output, active Low). This line is an input
when the IUSC has taken control of the bus and is operating in master mode. For slave cycles, the IUSC activates
this line as an output. In both directions, the line can carry
wait or acknowledge signalling depending on the state of
the S//D input during the initial BCR write. If S//D is High
when the BCR is written, this line operates as a Ready/Wait
line for Zilog and most Intel processors. In this mode, the
IUSC will not complete a master cycle while this line is Low,
and it asserts this line Low until it’s ready to complete an
interrupt acknowledge cycle; it never asserts this line when
the host accesses one of the IUSC registers.
If S//D is Low when the BCR is written, this line operates
thereafter as an Acknowledge line for Motorola and some
Intel processors. In this mode, the IUSC will not complete
a master cycle until this line is Low. It asserts this line Low
for register read and write cycles, and when it is ready to
complete an interrupt acknowledge cycle.
PS97USC0200
Z16C32 IUSC™
For slave cycles, this is a full time (totem pole) output. The
board designer can combine this signal with similar signals from other slaves, by means of an external logic gate
or a tri-state or open-collector driver.
/INT Interrupt Request (output, active Low). The IUSC
drives this line Low when (1) its IEI pin is High, (2) one or
more of its interrupt condition(s) is (are) enabled and
pending, and (3) the Under Service flag is not set for its
highest priority enabled/pending condition, nor for any
higher-priority internal condition. Software can program
whether the bus interface drives this pin in a totem-pole or
an open-drain fashion.
/INTACK Interrupt Acknowledge (input, active Low). A
Low on this line indicates that the host processor is
performing an interrupt acknowledge cycle. In some systems, a Low on this line may further indicate that external
logic has selected this IUSC as the device to be acknowledged, or as a potential device to be acknowledged. A
field in the Bus Configuration Register selects whether this
line carries a level-sensitive “status” signal that the IUSC
should sample at the leading edge of /AS or /DS, or a
single-pulse or double-pulse protocol. The IUSC responds
to an interrupt acknowledge cycle in a variety of ways
depending on this programming and the state of the /INT
and IEI lines, as described in the text.
IEI Interrupt Enable In (input, active High). This signal and
the IEO pin can be part of an interrupt-acknowledge daisy
chain with other devices that may request interrupts. If IEI
is High outside of an interrupt acknowledge cycle, one or
more IUSC interrupt condition(s) is (are) enabled and
pending, and the Under Service flag isn’t set for the highest
priority condition nor for any higher-priority one, then the
IUSC requests an interrupt by driving its /INT pin Low. If the
IEI pin is High during an interrupt acknowledge cycle, one
or more IUSC interrupt condition(s) is (are) enabled and
pending, and the Under Service flag isn’t set for the highest
priority condition nor for any higher-priority, then the IUSC
keeps IEO Low and responds to the cycle.
IEO Interrupt Enable Out (output, active High). This signal
and/or IEI can be part of an interrupt acknowledge daisy
chain with other devices that may request interrupts. The
IUSC drives its IEO pin Low whenever its IEI pin is Low,
and/or if the Under Service flag is set for any condition. This
IUSC drives this signal slightly differently during an interrupt acknowledge cycle, in that it also forces IEO Low if it
is (has been) requesting an interrupt.
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Z16C32 IUSC™
PIN DESCRIPTION (Continued)
/BUSREQ Bus Request (output, active Low). The DMA
controller section drives this line Low to request control of
the host bus. /BUSREQ can be an open-drain or totempole output depending on a bit in the Bus Configuration
Register. In open-drain mode the IUSC samples the pin as
an input and only drives it Low after sampling it high.
/TxC Transmit Clock (input or output). This signal can be
used as a clock input for any of the functional blocks in the
serial controller. Or, software can program the IUSC so that
this pin is an output carrying any of several transmitter or
internal clock signals, a general purpose input or output, or
an interrupt input.
/BIN Bus Acknowledge In (input, active Low). When the
IUSC receives a falling edge on this input, it samples
whether it has been driving (or has just begun to drive)
/BUSREQ. If so, it keeps /BOUT High and takes control of
the host bus. If not, it passes the bus grant by driving
/BOUT Low. This signal can be used with /BOUT to form a
bus-grant daisy chain for arbitration of bus control. Alternatively, it can be connected to a direct, positive grant from
an external arbiter, and the /BOUT pin can be left unconnected.
/RxREQ Receive DMA Request (input or output). In device
testing or in applications not using the serial controller and
DMA controller sections together in the usual way, this pin
can carry an active Low DMA Request from the receive
FIFO. On the IUSC this request is internally routed to the
on-chip Receive DMA channel; it is more typical to use the
RxREQ pin as a general-purpose output or as an interrupt
input.
/BOUT Bus Acknowledge Out (output, active Low). As
noted above, this signal can be used with /BIN to form a
bus-grant daisy chain for arbitration of bus control.
/ABORT Abort Master Cycle (input, active Low ). A Low on
this line during a master cycle makes the currently active
DMA channel terminate its activity and enter a disabled
state. Note that /ABORT is only effective during a DMA
cycle, so that the IUSC knows which channel should be
aborted. Also note that external logic must set /WAIT//RDY
to the right state for the cycle to complete, before /ABORT
becomes effective.
/TxREQ Transmit DMA Request (input or output). In device
testing or in applications not using the serial controller and
DMA controller sections together in the usual way, this pin
can carry an active Low DMA Request from the transmit
FIFO. On the IUSC this request is internally routed to the
on-chip Transmit DMA channel, and it’s more typical to use
the RxREQ pin as a general-purpose output or as an
interrupt input.
/DCD Data Carrier Detect (input or output, active Low).
Software can program the IUSC so that this signal enables/
disables the receiver. In addition, software can program
the device to request interrupts in response to transitions
on this line. The pin can also be used as a simple input or
output.
RxD Received Data (input, positive logic). The serial input.
TxD Transmit Data (output, positive logic). The serial
output.
/RxC Receive Clock (input or output). This signal can be
used as a clock input for any of the functional blocks in the
serial controller. Or, software can program the IUSC so that
this pin is an output carrying any of several receiver or
internal clock signals, a general-purpose input or output,
or an interrupt input.
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/CTS Clear to Send (input or output, active Low). Software
can program the IUSC so that this signal enables/disables
the transmitter. In addition, software can program the
device to request interrupts in response to transitions on
this line. The pin can also be used as a simple input or
output.
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P R E L I M I N A R Y
Z16C32 IUSC™
PORT7/TxCOMPLT General-Purpose I/O or Transmit Complete (input or output). Software can program the IUSC so
that this pin is a general-purpose input or output, or so that
it carries a Transmit Complete signal from the Transmitter,
that can control an external driver. The IUSC captures
transitions on this pin in internal latches.
PORT 3/RxTSA General-Purpose I/O or Receive Time Slot
Assigner Gate (input or output). Software can program the
IUSC so that this pin is a general-purpose input or output,
or so that it carries the Gate output of the Receive Time Slot
Assigner. The IUSC captures transitions on this pin in
internal latches.
PORT6/FSYNC General-Purpose I/O or Frame Sync (input or output). Software can program the IUSC so that this
pin is a general-purpose input or output, or a Frame Sync
input for the IUSC’s Time Slot Assigner circuits. The IUSC
captures transitions on this pin in internal latches.
PORT 2 General-Purpose I/O (input or output). Software
can program the IUSC so that this pin is a general-purpose
input or output. The IUSC captures transitions on this pin
in internal latches.
PORT5/RxSYNC General-Purpose I/O or Receive Sync
(input or output). Software can program the IUSC so that
this pin is a general-purpose input or output, or so that it
carries a Receive Sync output from the Receiver. The IUSC
captures transitions on this pin in internal latches.
PORT4/TxTSA General-Purpose I/O or Transmit Time Slot
Assigner Gate (input or output). Software can program the
IUSC so that this pin is a general-purpose input or output,
or so that it carries the Gate output of the Transmit Time Slot
Assigner, that can enable an external TxD driver in timeslotted ISDN or Fractional T1 applications. The IUSC
captures transitions on this pin in internal latches, as
described in the text.
PORT 1-0/CLK 1-0 General-Purpose I/Os or Reference
Clocks (inputs or outputs). Software can program the IUSC
so that either of these pins is a general-purpose input or
output, or a reference clock that can be divided down to
derive clocking for the Receiver and/or Transmitter. When
one of these pins is a general-purpose I/O, the IUSC
captures transitions on it in internal latches.
VCC, VSS Power and Ground. The inclusion of seven pins for
each power rail ensures good signal integrity, prevents
transients on outputs, and improves noise margins on
inputs. The IUSC’s internal power distribution network
requires that all these pins be connected appropriately.
ARCHITECTURE
The IUSC integrates a fast and efficient dual-channel DMA
with a highly versatile serial communications controller.
The functional capabilities of the IUSC are described from
two different points of view; as a datacommunications
device, it transmits and receives data in a wide variety of
datacommunications protocols; as a microprocessor peripheral with two DMA channels that offer such features as
PS97USC0200
four DMA transfer types, a flexible bus interface, and
vectored interrupts. The architecture is described in three
sections, DMA and Bus Interface Capabilities, Communication between the DMA and Serial Channel, and Serial
Communication Capabilities. The structure of the IUSC is
shown in Figure 1.
9
ZILOG
P R E L I M I N A R Y
Z16C32 IUSC™
DMA AND BUS INTERFACE CAPABILITIES
The IUSC’s two versatile DMA channels combined with a
flexible bus interface gives it the ability to meet a wide
variety of application requirements. The time required to
move data into and out of the transmitter and receiver is
minimized by the IUSC’s speed (20 MHz clock, three clock
cycles per word, typical); two buffer-chaining modes with
linked-frame status transfer; early buffer termination to
keep received frames in separate memory buffers; and
vectored interrupts. Some of the these features are briefly
described below, however, the user should refer to the
IUSC Technical Manual for additional information.
DMA Modes
The IUSC contains two DMA channels, one for the transmitter and one for the receiver. Each channel supports a
32-bit address and a 16-bit byte count. The channels
operate in one of four modes. In normal mode, the processor must reload the address and length at the end of each
buffer. In Pipelined mode, the processor can load the
address and length of the next buffer at any time during the
DMA transfer to the first buffer. In Array-Chained mode the
processor creates a table of address/length pairs in memory
for automatic transfer by the channel. In Linked List mode
the processor creates a linked list of address and length
pairs in memory to be automatically transferred by the
channel.
Single Buffer Mode is the most basic of the four data
transfer types. The starting address of each memory buffer
and the maximum number of characters to be transferred
to or from memory are programmed into the IUSC registers. When the DMA is enabled, it transfers all data between system memory and the transmit and receive FIFOs.
Pipelined Mode is similar to Single Buffer Mode with the
addition of an extra set of registers into which the processor can load to reload the DMA with the address and count
of the next memory buffer. Therefore, when a buffer is
complete, the IUSC is pre-programmed with the address
and count of the next buffer so the DMA need not stop
between each buffer as long as software stays one step
ahead of memory buffer usage.
In Array Mode, one of the two chaining modes, software
sets up a table of memory buffer information. The length of
the array is only limited by the amount of system memory
available for buffers. The IUSC is programmed with the
location of the array of buffer addresses and sizes. This
mode has the advantage that a burst of short frames is less
10
likely to overrun the systems ability to keep up. The use of
receive status block and transmit control block along with
the early buffer termination feature simplifies the segmentation and reassembly of serial messages in memory
buffers. When a DMA channel fetches a buffer count of
zero, it stops and can create an End-Of-Array interrupt.
Linked List Mode is the most versatile of DMA modes. It has
the Array Mode’s ability to switch buffers rapidly without
the requirement for the buffer information to be in a continuous table. Each link entry contains: The starting address to
write or read the data; the size of the buffer; optional status
or control information; and a pointer to the next link.
Memory buffers can easily be added and removed from
the list by changing the links in list entries.
DMA Features
In Linked List Mode, the IUSC has a programmable feature
to facilitate the use of buffers in a ring. When this feature is
enabled, the DMA writes a zero back to the buffer length
field of each array or list entry after it is read. Therefore, if
a linked list wraps around on itself, a DMA channel will not
reuse a buffer until software has processed the buffer, and
indicated that its eligible for reuse by writing a nonzero
value in the count field (fetching a count value of zero
deactivates the DMA channel). This feature can also be
used in array mode to track buffer use.
In both Bus Slave and Master Modes, the IUSC can read
and write data words in either byte order. It supports the
Little Endian convention used by many Intel microprocessors and the Big Endian convention used by many Motorola
microprocessors. When the IUSC is bus master, it can be
programmed to generate only the upper 16-bit address
when required and, consequently, save a clock cycle on
each transfer (three clocks per transfer instead of four).
When using the IUSC on a 16-bit bus and the starting
address of the message is on an odd address, the IUSC
automatically reorients itself onto even word boundaries
by first fetching a byte. This is especially valuable when
retransmitting a frame with a different size header than was
received. Two pins are available as status signals of the
type of transfer in progress.
There are a variety of command and status registers to
control and monitor the DMA channels. A DMA channel
can be aborted with either the /ABORT pin or by software
command. A pause command is also available to temporarily suspend transfers.
PS97USC0200
ZILOG
P R E L I M I N A R Y
Z16C32 IUSC™
Bus Interface & Utilization
Interrupts
The bus interface module stands between the external bus
pins and an on-chip 16-bit data bus that interconnects the
other functional modules. It includes several flexible bus
interfacing options that are controlled by the contents of
the Bus Configuration Register (BCR). The BCR is automatically the destination of the first write to the IUSC by the
host processor after a reset.
The interrupt subsystem of the IUSC derives from Zilog’s
experience in providing the most advanced interrupt capabilities in the microprocessor field. These capabilities
are at their best when used with a Zilog microprocessor,
but it is easy to interface the IUSC to work well with other
microprocessors as well. Four pins are dedicated to create
an interrupt daisy-chain hierarchy within the Serial Channel and between the Serial Channel and the DMA.
The IUSC is compatible with both multiplexed and nonmultiplexed bus interfaces and can transfer either 8 or 16
bits. It supports data transfers with /RD and /WR or R//W
and /DS strobe pins and either format of byte ordering. The
IUSC generates the Wait or Ready acknowledge handshaking used by Intel or Motorola microprocessors. Also,
three styles of interrupt acknowledge signals are supported for automated return of an interrupt vector to any
common microprocessor.
There are several options that control how the IUSC uses
the bus. The /BIN and /BOUT pins are available to form a
bus-grant daisy chain. The IUSC has several options on
how it arbitrates requests for bus mastership between
channels and how long it stays off the bus between
requests. The priority of the two DMA channels is programmable and can alternate between requests to allow both
channels equal access to the bus. Once one of the
channels has mastership of the bus, control can be passed
to the other channel if it is requesting or the IUSC can be
forced off the bus. A programmable preempt feature
selects whether the higher priority channel can take over
control of the bus if it starts requesting control while the
lower priority channel is using the bus.
The IUSC maximizes the use of its 32-byte FIFOs by
holding /BUSREQ active until the transmit FIFO is full, the
receive FIFO is empty, or both. The programmable dwell
timers can be used to limit how long the IUSC holds bus
mastership by counting either bus transfers, clock cycles
or both. Therefore, the combination of programmable FIFO
request levels, channel arbitration options, and programmable dwell timer features provide application software
the flexibility to optimize the IUSCs bus occupancy to meet
system throughput and bus response requirements.
When an IUSC responds to an interrupt acknowledge from
the CPU, it places an interrupt vector on the data bus. To
speed interrupt response time, the IUSC modifies three
bits in the vector to indicate which type of interrupt is being
requested. Separate vectors are provided for the serial
channel and DMA to easily discriminate the interrupt
source.
The DMA has four interrupt sources each for the receive
and transmit channels. Each interrupt source is independently enabled and there is a master enable for all DMA
interrupts. The four interrupt sources are End Of Array/ End
of Link, End Of Buffer, Hardware Abort, and Software
Abort.
Each of the six types of interrupts in the serial portion IUSC
(Receive Status, Receive Data, Transmit Status, Transmit
Data, I/O Status and Device Status) has three bits associated with it: Interrupt Pending (IP), Interrupt-Under-Service (IUS) and Interrupt Enable (IE). If the IE bit for a given
source is set, then that bit can source request interrupts.
Note that individual sources within the six types also have
their own interrupt arm bits. Finally, there is a Master
Interrupt Enable (MIE) bit which globally enables or disables all interrupts from the serial channel.
The Interrupt (/INT), Interrupt Acknowledge (/INTACK),
Interrupt Enable In (IEI) and Interrupt Enable Out (IEO)
pins are provided to create an automated mechanism to
place the vector on the bus among the highest priority
pending interrupts from multiple devices. The device with
the highest pending interrupt (/INT Low, IEI High) places a
vector on the bus in response to an interrupt acknowledge
cycle.
In the IUSC, the IP bit signals that an interrupt is pending.
If an IUS bit is set, this interrupt is being serviced and all
interrupt sources of lower priority are prevented from
requesting interrupts. An IUS bit is set during an interrupt
acknowledge cycle if there are no higher priority devices
requesting interrupts.
PS97USC0200
11
ZILOG
P R E L I M I N A R Y
Z16C32 IUSC™
DMA AND BUS INTERFACE CAPABILITIES (Continued)
There are six sources of Receive Status interrupt. Each one
is individually armed: Receiver exited hunt, received idle
line, received break/abort, received code violation/end-oftransmission/end-of-message, parity error/abort and overrun error. The Receive Data interrupt is generated whenever the receive FIFO fills with data beyond the level
programmed in the Receive Interrupt Control Register
(RICR). There are six sources of Transmit Status interrupt.
Each one is individually armed: Preamble sent, idle line
sent, abort sent, end-of-frame/end-of-message sent, CRC
sent and underrun error. The Transmit Data interrupt is
generated whenever the transmit FIFO empties below the
level programmed in the Transmit Interrupt Control Register (TICR).
The I/O Status interrupt serves to report transitions on any
of six pins. Interrupts are generated on either or both
edges with individual edge selection and arming for each
pin. The pins that can be programmed to generate I/O
Status interrupts are /RxC, /TxC, /RxREQ, /TxREQ, /DCD
and /CTS. These interrupts are independent of the programmed function of the pins.
The Device Status interrupt has four individually enabled
sources: Receive character counter underflow, DPLL sync
acquired, BRG1 zero count and BRGO zero count. Refer
to the IUSC Technical Manual for more details.
COMMUNICATION BETWEEN THE DMA AND SERIAL CHANNELS
The IUSC’s intra-chip communication between the DMA
and serial communications controller gives it the power to
achieve higher efficiency than is possible with a separate
DMA controller. The Linked Frame Status Transfer feature
writes the status and byte count of each received frame to
memory as part of an array or linked list. This provides a
simple and easy to use mechanism for storing the results
of a received message without arbitrary restrictions on how
quickly the host software must examine the results. Similarly, control information for transmit frames can be automatically read by the DMA from the array or link and
transferred into registers in the serial logic.
In all modes, the DMA can accept a signal from the serial
channel for early buffer termination. When the end of a
message is received, the data is transferred to the buffer
and the status is written to memory. The status is written
after the data in single buffer and pipelined modes or to the
array/link in array and linked-list modes if Linked-Frame
Status Transfer is enabled. This early buffer termination is
12
treated identically to the terminal count condition in the
DMA. Therefore, the receipt of the end of a message is a
seamless transition from one memory buffer to the next.
An example of using these intercommunication features
using linked list mode is shown in Figure 4. This example
shows the format of a ring of memory buffers with the linked
frame status transfer and ring buffer features enabled. Any
protocol that sets the “RxBound” bit (RCSR4 = 1), like
HDLC or 802.3, is appropriate to this example. The linked
list is shown in Figure 4 with three links for simplicity and
may be as large as memory allows. The sixth word in each
list entry is reserved and should not be used (it keeps the
list entries on 32-bit boundaries). If the end of the buffer is
reached and it is not the end of the frame, the IUSC writes
zeros as the status and count. Also, if the transmit channel
needs to start a new memory buffer other than at the
beginning of a frame, the DMA ignores the transmit control
block.
PS97USC0200
P R E L I M I N A R Y
ZILOG
Buffer 1 Address
Buffer 1 Length
Buffer 1 RSBR or 0
Buffer 1 RSHR or 0
0
Z16C32 IUSC™
Buffer 3 Address
Ring Buffer Mode
Writes this word
to 0 after it is read.
Buffer 3 Length
Buffer 3 RSBR or 0
Integrated Frame Status
Transfer writes the Receive
Status Block (or 0) here.
Link Address
of Entry2
Buffer 3 RSHR or 0
0
Link Address
of Entry1
Buffer 2 Address
Buffer 2 Length
Buffer 2 RSBR or 0
Buffer 2 RSHR or 0
0
Link Address
of Entry3
Figure 4. Linked List Mode with Linked Frame Status Transfer and Ring Buffer Features
Another method by which the DMA and serial channel
work together is using the Transmit Character Counter to
break a large block of data into a number of fixed length
frames. For example, it is desired to transmit a large file
which is located in several memory buffers as fixed length
smaller frames. With the IUSC, the serial channel is programmed to send the end-of-frame sequence each time
the set number of bytes is transmitted. Therefore, DMA
transfers are not interrupted, nor is system response
required to break the large file into frames.
PS97USC0200
The IUSC provides higher throughput than discrete serial
and DMA chip solutions because discrete chips do not
directly communicate with each other and, therefore, the
status of one device must be read by the CPU and
communicated to the other. This typically requires interrupts and the suspension of activity until status/control
information is updated. This uses precious time and bus
bandwidth, which can limit total throughput.
13
ZILOG
P R E L I M I N A R Y
Z16C32 IUSC™
DATA COMMUNICATIONS CAPABILITIES
The IUSC provides a full-duplex channel programmable
for use in any common data communication protocol. The
receiver and transmitter are completely independent and
each is supported by a 32-byte deep FIFO and a 16-bit
frame length counter. All modes allow optional even, odd,
mark or space parity. Synchronous modes allow the choice
of either of two 16-bit or a 32-bit CRC polynomials. Character length of up to 8 bits can be programmed for the
receiver and transmitter independently. Error and status
conditions are carried with the data in the receive FIFO to
greatly reduce the CPU overhead required to send or
receive a message, while key control parameters accompany transmit characters through the Tx FIFO. Interrupts
can be individually armed to signal such conditions as
overrun, parity error, framing error, end-of-frame, idle line
received, sync acquired, transmit underrun, CRC sent,
closing sync/flag sent, abort sent, idle line sent and preamble sent. In addition, several useful internal signals like
receive character boundary, received sync, transmit character boundary and transmission complete can be sent to
pins for use by external circuitry.
Protocols
Asynchronous Mode. The receiver and transmitter handle
data at a rate of 1/16, 1/32, or 1/64 the clock rate. The
receiver rejects start bits less than one-half a bit time and
includes recovery logic following a framing error. The
transmitter is capable of sending one, two, or anywhere in
the range of 9/16th to two stop bits per character in 1/16 bit
increments.
Nine-Bit Mode. This mode is identical to async except that
the receiver checks for the status of an additional address/
data bit between the parity bit and the stop bit. The value
of this bit is FIFO’ed along with the data. In the transmitter,
this bit is automatically inserted with the value that is
FIFO’ed from the transmit data.
Isochronous Mode. Both transmitter and receiver operate on start-stop (async) data using a 1x clock. The
transmitter sends one or two stop bits.
Asynchronous With Code Violations. This is similar to
Isochronous mode except that the start bit is replaced by
a three bit-time code violation pattern as in MIL-STD1553B. The transmitter sends zero, one or two stop bits.
HDLC Mode. In this mode, the receiver recognizes flags,
performs optional address matching, accommodates extended address fields, and performs zero deletion and
CRC checking. The receiver is capable of receiving sharedzero flags, recognizes abort sequences and can receive
arbitrary length frames. The transmitter automatically sends
14
opening and closing flags, performs zero insertion and
can be programmed to send an abort, an extended abort,
a flag or CRC and a flag on transmit underrun. The
transmitter automatically sends a closing flag with optional
CRC at the end of a programmed message length. Sharedzero flags are selected in the transmitter and a separate
character length is programmed for the last character in
the frame.
Frames terminated with an ABORT can be marked with a
status bit on the preceding character in addition to the
status interrupt that can be enabled. Abort is only detected
in-frame and, therefore, eliminates false detection due to
an idle line. The IUSC provides four choices (flag, all 1s, all
0s, or alternating 1s and 0s) of line preamble to condition
the line before beginning data transmission. This feature is
valuable to get the receiver DPLL in sync and as a flow
control mechanism to slow down frame transmission without slowing down the clock or disabling the transmitter.
HDLC Loop Mode. This mode is available only in the
transmitter and allows the IUSC to be used in an HDLC
Loop configuration. In this mode, the receiver is programmed to operate in HDLC mode to allow the transmitter
to echo received messages. Upon receipt of a particular
bit pattern (actually a sequence of seven consecutive
ones) the transmitter stops repeating data and inserts its
own frame(s).
802.3 Mode. This mode implements the data format of
IEEE 802.3 with a 16-bit address compare. In this mode,
/DCD and /CTS are used to implement the carrier sense
and collision detect interactions with the receiver and
transmitter. Back-off timing must be provided externally.
Monosync Mode. In this mode, a single character is used
for synchronization. The sync character can be either eight
bits long or the same length as the data characters. The
receiver can automatically strip sync characters from the
received data stream. The transmitter is programmed to
automatically send CRC on either an underrun or at the end
of a programmed message length.
Slaved Monosync Mode. This mode is available only in
the transmitter and allows the transmitter (operating just as
though it were in monosync mode) to send data with its
byte boundaries synchronized to those of the received
data.
Bisync Mode. This mode is identical to monosync mode
except that character synchronization requires two successive characters. The two characters need not be identical.
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Transparent Bisync Mode. In this mode, the synchronization pattern is DLE-SYN, programmable selected from
either ASCII or EBCDIC encoding. The receiver recognizes control character sequences and automatically
handles CRC calculations without CPU intervention. The
transmitter is programmed to send either SYN, DLE-SYN,
CRC-SYN, or CRC-DLE-SYN upon underrun and automatically sends the closing DLE-SYN with optional CRC at the
end of a programmed message length.
NRZI-Space. In NRZI-Space, a 1 is represented by the
absence of a transition at the beginning of a bit cell, i.e., the
level present in the preceding bit cell is maintained. A 0 is
represented by a transition at the beginning of the bit cell.
External Sync Mode. The receiver is synchronized to the
receive data by an externally-supplied signal on a pin for
custom protocol applications.
Biphase-Space. In Biphase-Space, a 1 is represented by
a transition at the beginning of the bit cell only. A 0 is
represented by a transition at the beginning of the bit cell
and another transition at the center of the bit cell.
Biphase-Mark. In Biphase-Mark, a 1 is represented by a
transition at the beginning of the bit cell and another
transition at the center of the bit cell. A 0 is represented by
a transition at the beginning of the bit cell only.
Data Encoding
The IUSC is programmed to encode and decode the serial
data in any of eight different ways (Figure 5). The transmitter encoding method is selected independently of the
receiver decoding method.
NRZ. In NRZ, a 1 is represented by a High level for the
duration of the bit cell and a 0 is represented by a Low level
for the duration of the bit cell.
NRZB. NRZB is inverted from NRZ.
NRZI-Mark. In NRZI-Mark, a 1 is represented by a transition at the beginning of a bit cell, i.e., the level present in the
preceding bit cell is reversed. A 0 is represented by the
absence of a transition at the beginning of the bit cell.
Data
1
1
0
Biphase-Level. In Biphase-Level, a 1 is represented by a
High during the first half of the bit cell and a Low during the
second half of the bit cell. A 0 is represented by a Low
during the first half of the bit cell and a High during the
second half of the bit cell.
Differential Biphase-Level. In Differential Biphase-Level,
a 1 is represented by a transition at the center of the bit cell,
with the opposite polarity from the transition at the center
of the preceding bit cell. A 0 is represented by a transition
at the center of the bit cell with the same polarity as the
transition at the center of the preceding bit cell. In both
cases, there are transitions at the beginning of the bit cell
to set up the level required to make the correct center
transition.
0
1
0
NRZ
NRZB
NRZI-M
NRZI-S
BI-PHASE-M
BIPHASE-S
BIPHASE-L
DIFFERENTIAL
BIPHASE-L
Figure 5. Data Encoding
PS97USC0200
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ZILOG
P R E L I M I N A R Y
Z16C32 IUSC™
DATA COMMUNICATIONS CAPABILITIES (Continued)
Character Counters
The IUSC contains separate 16-bit character counters for
the receiver and transmitter. The receive character counter
is set to a programmable starting value or automatically at
the beginning of each received frame and can be reloaded
under software control during a frame. The counter decrements with each receive character. At the end of the
receive message the current value in the counter is automatically loaded into a four-deep FIFO. With the Receive
Status Block (RSB) feature enabled, the counter value and
the status (RCSR) can be automatically transferred to
memory following the data. In array and linked list modes,
the RSB can be transferred to the array or list entry for easy
software access. This allows DMA transfer of data to
proceed without CPU intervention at the end of a received
frame, as the values in the FIFO allow the CPU to determine
the status and length of each frame.
to the Baud Rate Generator can be the /TxC pin, the /RxC
pin, a PORT pin, or the output of either counter. The baud
rate generator output frequency is related to the baud rate
generator input clock frequency by the following formula:
Similarly, the transmit character counter is loaded automatically at the beginning of each transmit frame and can
be reloaded under software control during a frame. The
counter is decremented with each write to the transmit
FIFO. When the counter reaches zero, and that byte is sent,
the transmitter automatically terminates the message in
the appropriate fashion (usually by sending the CRC and
the closing flag or sync character) without requiring CPU
intervention. In linked list and array modes, the transmit
character count and frame control word can be fetched
from the linked list or array.
The IUSC contains a DPLL (Digital Phase-Locked Loop) to
recover clock information from a data stream with NRZI or
Biphase encoding. The DPLL is driven by a clock that is
nominally 8, 16 or 32 times the receive data rate. The DPLL
uses this clock, along with the data stream, to construct a
clock for the data. This clock can be routed to the receiver,
transmitter, or both, or to a pin for use externally. In all
modes, the DPLL counts the input clock to create nominal
bit times. While counting, the DPLL watches the incoming
data stream for transitions. When a transition is detected,
the DPLL may make a count adjustment (during the next
counting cycle) to produce an output clock which tracks
the incoming bit cells. The DPLL provides properly phased
transmit and receive clocks to the clock multiplexer.
Baud Rate Generators
The IUSC contains two Baud Rate Generators. Each generator consists of a 16-bit time constant register and a 16bit down counter. In operation, the counter decrements
with each cycle of its selected input clock, and the time
constant can be automatically reloaded when the count
reaches zero. The output of the Baud Rate Generator
toggles when the counter reaches a count of one-half of the
time constant and again when the counter reaches zero. A
new time constant can be written at any time but the new
value does not take effect until the next load of the counter.
The outputs of both baud rate generators are sent to the
clock multiplexer for use internally or externally. The input
16
Output frequency = Input frequency/time constant + 1.
Note: This allows an output frequency in the range of 1 to
1/65536 of the input frequency, inclusive.
The output of either Baud Rate Generator can be used as
the transmit or receive clock, the reference clock input to
the DPLL circuit, and/or can be output on the /RxC or /TxC
pin.
Digital Phase-Locked Loop
Counters
The IUSC contains two 5-bit counters, which are programmed to divide an input clock by 4, 8, 16 or 32. The
outputs of these two counters are sent to the clock multiplexer. The counters can be used as prescalers for the
Baud Rate Generators. They also provide a stable transmit
clock from a common source when the DPLL is providing
the receive clock. The PORT0 and PORT1 pins can be
used as inputs to the counters.
PS97USC0200
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P R E L I M I N A R Y
Z16C32 IUSC™
Clock Multiplexers
I/O Port
The clock multiplexer logic selects the receive and transmit clocks and optional outputs on the /RxC and/or /TxC
pin(s). In the Z16C32, the PORT0 and PORT1 pins can be
used directly as receive and transmit clocks, as well as
being used as inputs to the counters.
The Port pins are general-purpose I/O pins. They are used
as additional modem control lines or other I/O functions.
Each port bit is individually programmable as generalpurpose input, as an output, or for a dedicated input or
output function. This programming is done in the Port
Control Register. Whether used as inputs or outputs, the
port pins can be read at any time.
Time Slot Assigner
The IUSC is equipped with two Time Slot Assigners to
support ISDN and Fractional T1 communications. There is
one assigner for the receiver. Each time slot assigner
selects one or more time slots within a frame, however, the
selected time slots must be contiguous. The first selected
time slot is programmable from slot 0 (the first slot) to slot
127 of the frame. The number of concatenated slots is
programmable from 1 to 15 (total slots). The time of the first
slot can be offset an integral number of clocks. This offset
is a delay and is programmable from 0 (no offset) to 7
clocks in increments of one clock (one bit cell). This offset
can be used to compensate for delays in frame sync
detection logic.
The dedicated functions of the port pins include Time Slot
Assigner gate outputs, transmit complete output, clock
inputs, receive sync output, or frame sync input.
Test Modes
The Latched/Unlatch bit is held at 0 if no transitions occur
on the port pin; this bit is set to a 1 when a rising edge or
falling edge transition is detected, or immediately after the
latch is opened if one or more transitions occurred while
the latch was closed. Writing a 0 to the Latched/Unlatch bit
has no effect on the latch. Writing a 1 to this bit resets the
status bit and opens the latch. To use the port as an input
without edge detection, a 1 would be written to the Latched/
Unlatch bit to open the latch and then the Port Status
Register would be read to obtain the current pin input
status.
The IUSC can be programmed for local loopback or auto
echo operation. In local loopback, the output of the transmitter is internally routed to the input of the receiver. This
allows testing of the IUSC data paths without any external
logic. Auto echo connects the RxD pin directly to the TxD
pin. This is useful for testing serial links external to the
IUSC.
PS97USC0200
The port pins capture edge transitions. Programming for
the capture is done using the Port Latched/Unlatch command bits in the Port Status Register. Each port bit is
individually controlled. The Latched/Unlatch bit is used as
a status signal to indicate that a transition has occurred on
the port pin and as a command to open the latches that
capture this transition. Both rising edge and falling edge
are detected. When a transition is detected, the latch
closes, holding the post transition state of the input.
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ZILOG
P R E L I M I N A R Y
Z16C32 IUSC™
PROGRAMMING
An Electronic Programmer’s Manual (MS DOS based) and
a Technical Manual are available to provide details about
programming the IUSC. Also included are explanations
and features of all registers in the IUSC.
The registers in the IUSC are programmed by the system
to configure the channel. Before this can occur, the system
must set up the bus interface by writing to the Bus Configuration Register (BCR). The BCR has no specific address
and is only accessible after a hardware reset of the device.
The first write to the IUSC, after a hardware reset, programs
the BCR. From that time on other channel registers can be
accessed. No specific address need be presented to the
IUSC for the BCR write; the IUSC knows that the first write
after a hardware reset is destined for the BCR.
In the multiplexed bus case, all registers are directly
addressable through the address latched by /AS at the
beginning of each bus cycle. The D//C pin is still used to
directly access the receive and send data registers (RDR
and TDR) with a multiplexed bus; if D//C is High, the
address latched by /AS is ignored and an access of RDR
or TDR is performed.
In the non-multiplexed bus case, the channel registers are
accessed indirectly using the address pointer in the Channel Command/Address Register (CCAR). The address of
the desired register is first written to the CCAR and then the
selected register is accessed; the pointer in the CCAR is
automatically cleared after this access.
18
Two more points about the IUSC should be noted here.
Channel Reset bit in the CCAR places the channel in the
reset state. To exit this reset state either a word of all zeros
is written to the CCAR (16-bit bus) or a byte of all zeros is
written to the lower byte of the CCAR (8-bit bus). Secondly,
after reset, the transmit and receive clocks are disabled.
The first thing that should be done in any initialization
sequence is a write to the Clock Mode Control Register
(CMCR) to select a clock source for the receiver and
transmitter.
The Serial/DMA (S//D) pin is used to differentiate between
the serial channel and the DMA registers. The DMA registers fall into three logic groupings; common registers that
apply to both transmit and receive, transmit registers, and
receive registers. The registers for DMA transmit functions
and receive functions are symmetric and therefore, a
single diagram is shown for each in the following pages.
When addressing the DMA registers, the Data/Control (D/
/C) pin selects between the transmit and receive registers.
For example, there is a DMA byte count register for
transmit and receive (TBCR and RBCR) at address 10101
with S//D pin Low. The TBCR is selected with the D//C pin
Low, and the RBCR is selected with the D//C pin High. The
format of these two registers is shown in Figure 20.
The register addressing is shown in Table 2 and the table
assumes that the BCR register bit 0 is set to 1. The A5-A1
column in the Table reflects the state of AD5-AD1, AD13AD9, CCAR5-CCAR1 or DCAR5-DCAR1 as applicable.
The bit assignments of the registers are shown in Figures
7 through 80. See the IUSC Technical Manual for details.
The register addressing is shown in Table 2 and the bit
assignments for the registers are shown in Figure 6.
PS97USC0200
P R E L I M I N A R Y
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Z16C32 IUSC™
Reset
Any Transaction
Up To and Including
BCR Write
No /AS
At Least One /AS
NonMultiplexed
Bus
BCR
Write
Transaction
BCR[2]=0
BCR[15]=1
8-Bit With
Separate
Address
BCR[2]=0
BCR[15]=0
8-Bit Without
Separate
Address
Multiplexed
Bus
BCR[2]=1
16-Bit
BCR[2]=0
BCR[15]=1
8-Bit With
Separate
Address
BCR[2]=0
BCR[15]=0
8-Bit Without
Separate
Address
BCR[2]=1
16-Bit
Note:
The presence of one transaction with an /AS active between reset, up to
and including the BCR write, chooses a multiplexed type of bus.
Figure 6. BCR Reset Sequence and Bit Assignments
PS97USC0200
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P R E L I M I N A R Y
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Z16C32 IUSC™
PROGRAMMING (Continued)
Table 1. Register Address List
S//D
D//C
Address
A5-A1
Name
Description
1
1
1
1
0
0
0
0
00000
00001
00010
00011
CCAR
CMR
CCSR
CCR
Channel Command/Address Register
Channel Mode Register
Channel Command/Status Register
Channel Control Register
1
1
1
1
0
0
0
0
00100
00101
00110
00111
PSR
PCR
TMDR
TMCR
Port Status Register
Port Control Register
Test Mode Data Register
Test Mode Control Register
1
1
1
1
0
0
0
0
01000
01001
01010
01011
CMCR
HCR
IVR
IOCR
Clock Mode Control Register
Hardware Configuration Register
Interrupt Vector Register
I/O Control Register
1
1
1
1
0
0
0
0
01100
01101
01110
01111
ICR
DCCR
MISR
SICR
Interrupt Control Register
Daisy-Chain Control Register
Misc. Interrupt Status Register
Status Interrupt Control Register
1
1
1
1
1
0
0
0
XXXXX
1X000
10001
10010
RDR
RDR
RMR
RCSR
Receive Data Register (Read Only)
Receive Data Register (Read Only)
Receive Mode Register
Receive Command/Status Register
1
1
1
1
0
0
0
0
10011
10100
10101
10110
RICR
RSR
RCLR
RCCR
Receive Interrupt Control Register
Receive Sync Register
Receive Count Limit Register
Receive Character Count Register
1
1
1
1
1
0
1
0
0
0
10111
XXXXX
1X000
11001
11010
TC0R
TDR
TDR
TMR
TCSR
Time Constant 0 Register
Transmit Data Register (Write Only)
Transmit Data Register (Write Only)
Transmit Mode Register
Transmit Command/Status Register
1
1
1
1
1
0
0
0
0
0
11011
11100
11101
11110
11111
TICR
TSR
TCLR
TCCR
TC1R
Transmit Interrupt Control Register
Transmit Sync Register
Transmit Count Limit Register
Transmit Character Count Register
Time Constant 1 Register
20
PS97USC0200
P R E L I M I N A R Y
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Z16C32 IUSC™
Table 1. Register Address List (Continued)
S//D
D//C
Address
A5-A1
Name
X
0
0
0
0
0
X
0
X
X
XXXXX
00000
00001
00011
00100
BCR
DCAR
TDCMR
DCR
DACR
0
0
0
0
0
X
X
X
X
X
01001
01010
01100
01101
01110
BDCR
DIVR
DICR
CDIR
SDIR
Burst Dwell Control Register
DMA Interrupt Vector Register
DMA Interrupt Control Register
Clear DMA Interrupt Register
Set DMA Interrupt Register
0
0
0
0
0
0
0
0
0
0
01111
10101
10110
10111
11101
TDIAR
TBCR
TARL
TARU
NTBCR
Transmit DMA Interrupt Arm
Transmit Byte Count Register
Transmit Address Register (Lower)
Transmit Address Register (Upper)
Next Transmit Byte Count Register
0
0
0
0
0
0
0
1
1
1
11110
11111
00001
01111
10101
NTARL
NTARU
RDMR
RDIAR
RBCR
Next Transmit Address Register (Lower)
Next Transmit Address Register (Upper)
Receive DMA Mode Register
Receive DMA Interrupt Arm
Receive DMA Byte Count Register
0
0
0
0
0
1
1
1
1
1
10110
10111
11101
11110
11111
RARL
RARU
NRBCR
NRARL
NRARU
Receive Address Register (Lower)
Receive Address Register (Upper)
Next Receive Byte Count Register
Next Receive Address Register (Lower)
Next Receive Address Register (Upper)
PS97USC0200
Description
Bus Configuration Register
DMA Command/Address Register
Transmit DMA Channel Mode Register
DMA Control Register
DMA Array Count Register
21
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Z16C32 IUSC™
REGISTER DESCRIPTION
This section describes the function of the various bits in the
registers of the device. Throughout this section the following conventions are discussed:
Control bits are written and read by the CPU and are not
modified by the device. Command bits are written by the
CPU to initiate an action in the device and are read as
zeros. Status bits are controlled by the device and are read
to check device status. Any writes to status bits are ignored
by the device. Command/Status bits are controlled by both
the device and the CPU. They may be written and read by
the CPU and may also be modified by the device.
Reserved bits are not used in this implementation of the
device and may or may not be physically present in the
device. Any reserved bits that are physically present are
readable and writable, but reserved bits that are not
present are always read as zeros. To ensure compatibility
with future versions of the device, reserved bits should
always be written with zeros. Reserved commands should
not be used for the same reason.
First, the DMA registers unique to the IUSC are described
in the following pages (Figures 7-16) and then the serial
channel registers are described (Figures 17-80).
Address: 00000 (Shared) *
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Upper//Lower Byte Select (WO)
Address 0 (WO)
Address 1 (WO)
Address 2 (WO)
Address 3 (WO)
Address 4 (WO)
Byte//Word Access (WO)
Pointer Channel Select (WO)
Master Bus Request Enable
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Tx Channel
Rx Channel
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Null Command
Reset This Channel
Start This Channel
Start/Continue This Channel
Pause This Channel
Abort This Channel
Reserved
Start/Init This Channel
Reset Highest IUS
Reset All Channels
Start All Channels
Start/Continue All Channels
Pause All Channels
Abort All Channels
Reserved
Start/Init All Channels
Channel Select (WO)**
Channel Command
Notes:
* (Shared) means, shared between DMA Channels
** (WO) means Write Only
Figure 7. DMA Command/Address Register
22
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Z16C32 IUSC™
D7 D6 D5 D4 D3 D2 D1 D0
Software Abort (RO)
Hardware Abort (RO)
Buffer Termination (RO)
Array Termination (RO)
Busy (RO)
Initializing (RO)
Get Link (RO)
Continue (RO)
0
X
1
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
1
X
0
1
1
1
0
0
1
1
0 0
X X
X X
X X
X X
X X
X X
X X
0
X
X
X
X
X
X
X
0
X
X
X
X
1
X
X
Reset
Start
Start/Continue (Buffered Mode)
Start/Continue (Other Than Buffered Mode)
Pause
Abort
Start/Init (Array or Linked Array Modes)
Start/Init (Normal or Buffered Modes)
Command
Notes:
X = Previous Value
(RO) = Read Only
Figure 8. Affect of Commands on Status Bits
PS97USC0200
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Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 00001
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Software Abort (RO)
Hardware Abort (RO)
End of Buffer (RO)
End of Array/Link (RO)
Initialization (RO)
Busy (RO)
Get Link (RO)
Continue (RO)
8-Bit Operand
Enable Early Termination
0
0
1
1
0
1
0
1
Increment
Decrement
Fixed Address
Reserved
Address Mode
Ring Buffer Enable
Linked Frame Status Transfer
0
0
1
1
0
1
0
1
Auto Modes Disabled
Buffered
Array Chained
Linked-Array Chained
DMA Mode
Figure 9. Tx/Rx DMA Mode Register (TDMR) (RDMR)
24
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P R E L I M I N A R Y
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Z16C32 IUSC™
D7 D6 D5 D4
Initialization
Busy
Get Link
Continue
0
0
X
X
1
0
0
X
1
X
0
1
X
X
X
0
0
1
X
X
Channel Disabled
Channel Enabled
Not Possible
Not Possible
Not Possible
0
0
1
1
X
X
0
0
0
0
X
1
0
1
0
1
X
X
0
0
0
0
1
X
Channel Disabled, Base Registers Invalid
Channel Enabled, Base Registers Invalid
Channel Disabled, Base Registers Valid
Channel Enabled, Base Registers Valid
Not Possible
Not Possible
Buffered Mode
0
0
0
0
X
1
0
0
0
0
1
X
0
1
0
1
X
X
0
0
1
1
X
X
Channel Disabled, Data Transfer Phase
Channel Enabled, Data Transfer Phase
Channel Disabled, Array Transfer Phase
Channel Enabled, Array Transfer Phase
Not Possible
Not Possible
Array-Chained Mode
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
X
0
1
0
1
X
0
1
X
0
0
1
1
0
1
1
X
Channel Disabled, Data Transfer Phase
Channel Enabled, Data Transfer Phase
Channel Disabled, Array Transfer Phase
Channel Enabled, Array Transfer Phase
Not Possible
Channel Disabled, Link Transfer Phase
Channel Enabled, Link Transfer Phase
Not Possible
Linked Array-Chained Mode
Normal Mode
Figure 10. Status Bit Combinations
PS97USC0200
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Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 00011 (Shared)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
0
1
0
1
32-bit Linear
Reserved
Segmented 16/16
Segmented 8/24
Addressing
Mode
/UAS Every Transaction
One Wait Every Transaction
Enable Transaction Status
Bus Inactive Time
Reserved
Reserved
Reserved
Reserved
0
0
1
1
0
1
0
1
End of Demand or Burst
End of Demand Only
End of Burst Only
Reserved
DMA Request
Arbitration
Link Array Big End/Little End
Preempt Enable
0
0
1
1
0
1
0
1
Tx Channel
Rx Channel
Alternating
Reserved
Channel
Priority
Figure 11. DMA Control Register (DCR)
26
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Big End Array
(16-Bit bus)
Z16C32 IUSC™
AD15
AD0
Address n
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Address n+2
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
Little End Array
(16-Bit bus)
AD15
AD0
Address n
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
Address n+2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Big End Array
(8-Bit bus)
AD7
AD0
Address n
31
30
29
28
27
26
25
24
Address n+1
23
22
21
20
19
18
17
16
Address n+2
15
14
13
12
11
10
09
08
Address n+3
07
06
05
04
03
02
01
00
Little End Array
(8-Bit bus)
AD7
AD0
Address n
07
06
05
04
03
02
01
00
Address n+1
15
14
13
12
11
10
09
08
Address n+2
23
22
21
20
19
18
17
16
Address n+3
31
30
29
28
27
26
25
24
Figure 12. Array-Chained Bit Ordering
Note:
Bit 12 in DCR is used to control the byte ordering of addresses and counts stored in memory in the
Array and Linked Array Modes. The above figure shows the two cases for both bus bandwidths.
PS97USC0200
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Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 00100 (Shared)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Tx Channel Array Count (RO)
Rx Channel Array Count (RO)
Reserved
Figure 13a. DMA Array Count Register (DACR)
Getlink (in DCMR)
Channel Array Count 3
Channel Array Count 2
Channel Array Count 1
Channel Array Count 0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Array Operation Not Started
Fetched Last Byte of Array
Fetched Fifth Byte of Array
Fetched Fourth Byte of Array
Fetched Third Byte of Array
Fetched Second Byte of Array
Fetched First Byte of Array
Fetched Last Byte of Buffer
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Array Operation Not Started
Fetched Last Byte of Array
Fetched Fifth Byte of Array
Fetched Fourth Byte of Array
Fetched Third Byte of Array
Fetched Second Byte of Array
Fetched First Byte of Array
Fetched Last Byte of Linked Address
Invalid
Invalid
Invalid
Invalid
Fetched Third Byte of Linked Address
Fetched Second Byte of Linked Address
Fetched First Byte of Linked Address
Fetched Last Byte of Buffer
Array-Chained
Linked Array-Chained
Figure 13b. Channel Array Count Bit Combinations
Note: See the Z16C32 Technical Manual for the appropriate table with Linked Status Transfer feature enabled.
28
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Z16C32 IUSC™
Address: 01001 (Shared)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Clock Cycle Limit (Bit 3)
Clock Cycle Limit (Bit 4)
Clock Cycle Limit (Bit 5)
Clock Cycle Limit (Bit 6)
Clock Cycle Limit (Bit 7)
Clock Cycle Limit (Bit 8)
Clock Cycle Limit (Bit 9)
Clock Cycle Limit (Bit 10)
Transaction Limit (Bit 0)
Transaction Limit (Bit 1)
Transaction Limit (Bit 2)
Transaction Limit (Bit 3)
Transaction Limit (Bit 4)
Transaction Limit (Bit 5)
Transaction Limit (Bit 6)
Transaction Limit (Bit 7)
Figure 14. Burst Dwell Control Register (BDCR)
Notes:
BDCR Controls the amount of time that DMA may remain bus master.
Bits 15 through 8 are used to select a limit for the number of DMA transfers on the Bus
while the DMA is bus master. This limit is a binary number, a value of zero disables
the transaction limit function.
Bits 7 through 0 are used to select a limit for the number of clock cycles that the DMA
may remain on the bus as bus master.
Bus transaction will always complete, even if the clock cycle limit is exceeded during
the bus cycle, and even if the cycle is extended by external hardware signalling
through /WAIT//RDY.
PS97USC0200
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Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 01010 (Shared)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
IV <0>
IV <1>
IV <2>
IV <3>
IV <4>
IV <5>
IV <6>
IV <7>
IV <0> (RO)
0
0
1
1
0
1
0
1
None
Not Used
Tx Channel
Rx Channel
Type Code (RO)
IV <3> (RO)
IV <4> (RO)
IV <5> (RO)
IV <6> (RO)
IV <7> (RO)
Figure 15. DMA Interrupt Vector Register (DIVR)
Address: 01100 (Shared)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Tx IE
Rx IE
Reserved
VIS
NV
DLC
MIE
Figure 16. DMA Interrupt Control Register (DICR)
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Z16C32 IUSC™
Address: 01101 (Shared)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Reset Tx IP (WO)
Reset Rx IP (WO)
Reserved
Reset Tx IUS (WO)
Reset Rx IUS (WO)
Reserved
Figure 17. Clear DMA Interrupt Register (CDIR)
Address: 01110 (Shared)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Set Tx IP
Set Rx IP
Reserved
Set Tx IUS
Set Rx IUS
Reserved
Figure 18. Set DMA Interrupt Register (SDIR)
Address: 01111 *
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Software Abort IA
Hardware Abort IA
Buffer Termination IA
Array Termination IA
Reserved
Figure 19. Tx/Rx DMA Interrupt Arm (TDIAR)/(RDIAR)
Notes:
* The format of this register is the same for the receiver and transmitter. The transmit register
is accessed by addressing it with the D//C pin Low (0). The receive register is accessed by
addressing it with the D//C pin High (1). This applies to Figures 19 through 25.
PS97USC0200
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Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 10101 *
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TTC <0>
TTC <1>
TTC <2>
TTC <3>
TTC <4>
TTC <5>
TTC <6>
TTC <7>
TTC <8>
TTC <9>
TTC <10>
TTC <11>
TTC <12>
TTC <13>
TTC <14>
TTC <15>
Figure 20. Tx/Rx Byte Count Register (TBCR)/(RBCR)
Address: 10110 *
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TAR <0>
TAR <1>
TAR <2>
TAR <3>
TAR <4>
TAR <5>
TAR <6>
TAR <7>
TAR <8>
TAR <9>
TAR <10>
TAR <11>
TAR <12>
TAR <13>
TAR <14>
TAR <15>
Figure 21. Tx/Rx Address Register (lower) (TARL)/(RARL)
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Z16C32 IUSC™
Address: 10111 *
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TAR <16>
TAR <17>
TAR <18>
TAR <19>
TAR <20>
TAR <21>
TAR <22>
TAR <23>
TAR <24>
TAR <25>
TAR <26>
TAR <27>
TAR <28>
TAR <29>
TAR <30>
TAR <31>
Figure 22. Tx/Rx Address Register (Upper) (TARU)/(RARU)
Address: 11101 *
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BTC <0>
BTC <1>
BTC <2>
BTC <3>
BTC <4>
BTC <5>
BTC <6>
BTC <7>
BTC <8>
BTC <9>
BTC <10>
BTC <11>
BTC <12>
BTC <13>
BTC <14>
BTC <15>
Figure 23. Next Tx/Rx Byte Counter Register (NTBCR)/(RTBCR)
PS97USC0200
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Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 11110 *
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BAR <0>
BAR <1>
BAR <2>
BAR <3>
BAR <4>
BAR <5>
BAR <6>
BAR <7>
BAR <8>
BAR <9>
BAR <10>
BAR <11>
BAR <12>
BAR <13>
BAR <14>
BAR <15>
Figure 24. Next Tx/Rx Address Register (Lower) (NTARL)/(RTARL)
Address: 11111 *
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BAR <16>
BAR <17>
BAR <18>
BAR <19>
BAR <20>
BAR <21>
BAR <22>
BAR <23>
BAR <24>
BAR <25>
BAR <26>
BAR <27>
BAR <28>
BAR <29>
BAR <30>
BAR <31>
Figure 25. Next Tx/Rx Address Register (Upper) (NTARU)/(RTARU)
34
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AD0
AD15
Base Address
Buffer #1
Base Address + 2
Base Address + 4
Buffer #2
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
CNT<15-8>
CNT<7-0>
AD<31-24>
AD<23-16>
Base Address + 8
AD<15-8>
AD<7-0>
Base Address + 10
CNT<15-8>
CNT<7-0>
AD<31-24>
AD<23-16>
Base Address + 14
AD<15-8>
AD<7-0>
Base Address + 16
CNT<15-8>
CNT<7-0>
Ignored
Ignored
Last Base Address + 2
Ignored
Ignored
Last Base Address + 4
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Base Address + 6
Base Address + 12
Last Base Address
Buffer #3
Dummy
Base Address Register
After Termination
Figure 26a. Array-Chained, 16-Bit Bus, Big End Array
Note:
The addition of frame status/control information in the array with Linked Frame
Status Transfer Enabled is similar for Big and Little End Array. See Figure 26b.
PS97USC0200
35
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
AD0
AD15
Base Address
Buffer #1
AD<31-24>
AD<23-16>
Base Address + 2
AD<15-8>
AD<7-0>
Base Address + 4
CNT <15-8>
CNT <7-0>
Base Address + 6
RSB/TCB <15-8>
RSB/TCB <7-0>
Base Address + 8
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
Base Address + 10
Base Address + 12
Buffer #2
0
0
AD<31-24>
AD<23-16>
Base Address + 14
AD<15-8>
AD<7-0>
Base Address + 16
CNT <15-8 >
CNT <7-0>
Base Address + 18
RSB/TCB <15-8>
RSB/TCB <7-0>
Base Address + 20
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
Base Address + 22
0
0
AD<31-24>
AD<23-16>
Base Address + 26
AD<15-8>
AD<7-0>
Base Address + 28
CNT <15-8>
CNT <7-0>
RSB/TCB <15-8>
RSB/TCB <7-0>
Base Address + 24
Buffer #3
Base Address + 30
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
Base Address + 32
Base Address + 34
Last Base Address
Dummy
0
0
Ignored
Ignored
Last Base Address + 2
Ignored
Ignored
Last Base Address + 4
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Base Address Register
After Termination
Figure 26b. Array-Chained, 16-Bit Bus, Big End Array
Linked Frame Status Transfer Enabled
36
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AD0
AD15
Buffer #1
AD<15-8>
AD<7-0>
Base Address + 2
AD<31-24>
AD<23-16>
Base Address + 4
CNT<15-8>
CNT<7-0>
AD<15-8>
AD<7-0>
Base Address + 8
AD<31-24>
AD<23-16>
Base Address + 10
CNT<15-8>
CNT<7-0>
AD<15-8>
AD<7-0>
Base Address + 14
AD<31-24>
AD<23-16>
Base Address + 16
CNT<15-8>
CNT<7-0>
Ignored
Ignored
Last Base Address + 2
Ignored
Ignored
Last Base Address + 4
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Base Address
Base Address + 6
Base Address + 12
Last Base Address
Buffer #2
Buffer #3
Dummy
Base Address Register
After Termination
Figure 27. Array-Chained, 16-Bit Bus, Little End Array
PS97USC0200
37
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
AD0
AD7
Base Address
Buffer #1
AD<31-24>
Base Address + 1
AD<23-16>
Base Address + 2
AD<15-8>
Base Address + 3
AD<7-0>
Base Address + 4
CNT<15-8>
Base Address + 5
Base Address + 6
CNT<7-0>
Buffer #2
AD<31-24>
Base Address + 7
AD<23-16>
Base Address + 8
AD<15-8>
Base Address + 9
AD<7-0>
Base Address + 10
CNT<15-8>
Base Address + 11
CNT<7-0>
Last Base Address
Dummy
Ignored
Last Base Address + 1
Ignored
Last Base Address + 2
Ignored
Last Base Address + 3
Ignored
Last Base Address + 4
0 0 0 0 0 0 0 0
Last Base Address + 5
0 0 0 0 0 0 0 0
Base Address Register
After Termination
Figure 28a. Array-Chained, 8-Bit Bus, Big End Array
Note:
The addition of frame status/control information in the array with Linked Frame
Status Transfer Enabled is similar for Big and Little End Array. See Figure 28b.
38
PS97USC0200
ZILOG
P R E L I M I N A R Y
Z16C32 IUSC™
AD0
AD7
Base Address
Buffer #1
AD<31-24>
Base Address + 1
AD<23-16>
Base Address + 2
AD<15-8>
Base Address + 3
AD<7-0>
Base Address + 4
CNT<15-8>
Base Address + 5
CNT<7-0>
Base Address + 6
RSB/TCB <15-8>
Base Address + 7
RSB/TCB <7-0>
Base Address + 8
RCHR/TCLR <15-8>
Base Address + 9
RSHR/TCLR <7-0>
Base Address + 10
0
Base Address + 11
0
Base Address + 12
Buffer #2
AD<31-24>
Base Address + 13
AD<23-16>
Base Address + 14
AD<15-8>
Base Address + 15
AD<7-0>
Base Address + 16
CNT<15-8>
Base Address + 17
CNT<7-0>
Base Address + 18
RSB/TCB <15-8>
Base Address + 19
RSB/TCB <7-0>
Base Address + 20
RCHR/TCLR <15-8>
Base Address + 21
RSHR/TCLR <7-0>
Base Address + 22
0
Base Address + 23
0
Last Base Address
Dummy
Ignored
Last Base Address + 1
Ignored
Last Base Address + 2
Ignored
Last Base Address + 3
Ignored
Last Base Address + 4
0 0 0 0 0 0 0 0
Last Base Address + 5
0 0 0 0 0 0 0 0
Base Address Register
After Termination
Figure 28b. Array-Chained, 8-Bit Bus, Big End Array,
Linked Frame Status Transfer Enabled
PS97USC0200
39
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
AD0
AD7
Base Address
Buffer #1
AD<7-0>
Base Address + 1
AD<15-8>
Base Address + 2
AD<23-16>
Base Address + 3
AD<31-24>
Base Address + 4
CNT<7-0>
Base Address + 5
Base Address + 6
CNT<15-8>
Buffer #2
AD<7-0>
Base Address + 7
AD<15-8>
Base Address + 8
AD<23-16>
Base Address + 9
AD<31-24>
Base Address + 10
CNT<7-0>
Base Address + 11
CNT<15-8>
Last Base Address
Dummy
Ignored
Last Base Address + 1
Ignored
Last Base Address + 2
Ignored
Last Base Address + 3
Ignored
Last Base Address + 4
0 0 0 0 0 0 0 0
Last Base Address + 5
0 0 0 0 0 0 0 0
Base Address Register
After Termination
Figure 29. Array-Chained, 8-Bit Bus, Little End Array
40
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AD15
Base Address
Buffer #1
AD0
AD<31-24>
AD<23-16>
Base Address + 2
AD<15-8>
AD<7-0>
Base Address + 4
CNT<15-8>
CNT<7-0>
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
AD<31-24>
AD<23-16>
Base Address + 6
Base #2
Base Address + 8
#2 Base Address
Buffer #2
#2 Base Address + 2
AD<15-8>
AD<7-0>
#2 Base Address + 4
CNT<15-8>
CNT<7-0>
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
#2 Base Address + 6
Base #3
#2 Base Address + 8
AD<31-24>
AD<23-16>
#3 Base Address + 2
AD<15-8>
AD<7-0>
#3 Base Address + 4
CNT<15-8>
CNT<7-0>
#3 Base Address
#n - 1 Base Address + 6
Buffer #3
Base #n
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
Ignored
Ignored
#n Base Address + 2
Ignored
Ignored
#n Base Address + 4
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
#n - 1 Base Address + 8
#n Base Address
Buffer #n
Figure 30a. Linked Array-Chained, 16-Bit Bus, Big End Array
Note:
The addition of frame status/control information in the array with Linked Frame
Status Transfer Enabled is similar for Big and Little End Array. See Figure 30b.
PS97USC0200
41
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
AD0
AD15
Base Address
Buffer #1
Base Address + 2
AD<31-24>
AD<23-16>
AD <15-8>
AD<7-0>
Base Address + 4
CNT<15-8>
CNT<7-0>
Base Address + 6
RSB/TCB <15-8>
RSB/TCB <7-0>
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
Base Address + 8
0
0
Base #2
AD<31-24>
AD<23-16>
AD <15-8>
AD<7-0>
Buffer #2
AD<31-24>
AD<23-16>
#2 Base Address + 2
AD <15-8>
AD<7-0>
#2 Base Address + 4
CNT<15-8>
CNT<7-0>
#2 Base Address + 6
RSB/TCB <15-8>
RSB/TCB <7-0>
Base Address + 10
Base Address + 12
Base Address + 14
#2 Base Address
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
#2 Base Address + 8
#2 Base Address + 10
#2 Base Address + 12
Base #3
#2 Base Address + 14
#3 Base Address
Buffer #3
0
0
AD<31-24>
AD<23-16>
AD <15-8>
AD<7-0>
AD<31-24>
AD<23-16>
#3 Base Address + 2
AD <15-8>
AD<7-0>
#3 Base Address + 4
CNT<15-8>
CNT<7-0>
#3 Base Address + 6
RSB/TCB <15-8>
RSB/TCB <7-0>
#3 Base Address + 8
#3 Base Address + 10
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
0
0
Figure 30b. Linked Array-Chained, 16-Bit Bus, Big End Array
42
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AD15
AD0
AD<15-8>
AD<7-0>
Base Address + 2
AD<31-24>
AD<23-16>
Base Address + 4
CNT<15-8>
CNT<7-0>
AD<15-8>
AD<7-0>
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
#2 Base Address + 2
AD<31-24>
AD<23-16>
#2 Base Address + 4
CNT<15-8>
CNT<7-0>
AD<15-8>
AD<7-0>
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
#3 Base Address + 2
AD<31-24>
AD<23-16>
#3 Base Address + 4
CNT<15-8>
CNT<7-0>
Base Address
Base Address + 6
Buffer #1
Base #2
Base Address + 8
#2 Base Address
#2 Base Address + 6
Buffer #2
Base #3
#2 Base Address + 8
#3 Base Address
#n - 1 Base Address + 6
Buffer #3
Base #n
#n - 1 Base Address + 8
AD<15-8>
AD<7-0>
AD<31-24>
AD<23-16>
Ignored
Ignored
#n Base Address + 2
Ignored
Ignored
#n Base Address + 4
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
#n Base Address
Buffer #n
Figure 31. Linked Array-Chained, 16-Bit Bus, Little End Array
PS97USC0200
43
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
AD7
Base Address
Buffer #1
AD0
AD<7-0>
Base Address + 1
AD<15-8>
Base Address + 2
AD<23-16>
Base Address + 3
AD<31-24>
Base Address + 4
CNT<7-0>
Base Address + 5
CNT<15-8>
Base Address + 6
Base #2
AD<7-0>
Base Address + 7
AD<15-8>
Base Address + 8
AD<23-16>
Base Address + 9
AD<31-24>
#2 Base Address
Buffer #2
AD<7-0>
#2 Base Address + 1
AD<15-8>
#2 Base Address + 2
AD<23-16>
#2 Base Address + 3
AD<31-24>
#2 Base Address + 4
CNT<7-0>
#2 Base Address + 5
CNT<15-8>
#2 Base Address + 6
Base #3
AD<7-0>
#2 Base Address + 7
AD<15-8>
#2 Base Address + 8
AD<23-16>
#2 Base Address + 9
AD<31-24>
Figure 32a. Linked Array-Chained, 8-Bit Bus, Big End Array
Note:
The addition of frame status/control information in the array with Linked
Frame Status Transfer Enabled is similar to Big End Array. See Figure 32b.
44
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AD0
AD7
Base Address
Buffer #1
AD<31-24>
Base Address + 1
AD<23-16>
Base Address + 2
AD<15-8>
Base Address + 3
AD<7-0>
Base Address + 4
CNT<15-8>
Base Address + 5
CNT<7-0>
Base Address + 6
RSB/TCB <15-8>
Base Address + 7
RSB/TCB <7-0>
Base Address + 8
RCHR/TCLR <15-8>
Base Address + 9
RCHR/TCLR <7-0>
Base Address + 10
0
Base Address + 11
0
Base Address + 12
Base #2
AD<31-24>
Base Address + 13
AD<23-16>
Base Address + 14
AD<15-8>
Base Address + 15
AD<7-0>
#2 Base Address
Buffer #2
AD<31-24>
#2 Base Address + 1
AD<23-16>
#2 Base Address + 2
AD<15-8>
#2 Base Address + 3
AD<7-0>
#2 Base Address + 4
CNT<15-8>
#2 Base Address + 5
CNT<7-0>
#2 Base Address + 6
RSB/TCB <15-8>
#2 Base Address + 7
RSB/TCB <7-0>
#2 Base Address + 8
RCHR/TCLR <15-8>
#2 Base Address + 9
RCHR/TCLR <7-0>
#2 Base Address + 10
0
#2 Base Address + 11
0
Figure 32b. Linked Frame Status Transfer Enables
PS97USC0200
45
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
AD7
Base Address
Buffer #1
AD0
AD<31-24>
Base Address + 1
AD<23-16>
Base Address + 2
AD<15-8>
Base Address + 3
AD<7-0>
Base Address + 4
CNT<15-8>
Base Address + 5
CNT<7-0>
Base Address + 6
Base #2
AD<31-24>
Base Address + 7
AD<23-16>
Base Address + 8
AD<15-8>
Base Address + 9
AD<7-0>
#2 Base Address
Buffer #2
AD<31-24>
#2 Base Address + 1
AD<23-16>
#2 Base Address + 2
AD<15-8>
#2 Base Address + 3
AD<7-0>
#2 Base Address + 4
CNT<15-8>
#2 Base Address + 5
CNT<7-0>
#2 Base Address + 6
Base #3
AD<31-24>
#2 Base Address + 7
AD<23-16>
#2 Base Address + 8
AD<15-8>
#2 Base Address + 9
AD<7-0>
Figure 33. Linked Array-Chained 8-Bit Bus, Little End Array
46
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 00000
D15 D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Upper//Lower Byte Select (WO)
Address 0 (WO)
Address 1 (WO)
Address 2 (WO)
Address 3 (WO)
Address 4 (WO)
Byte//Word Access (WO)
Channel Load DMA (WO)
0
0
1
1
0
1
0
1
Normal Operation
Auto Echo
External Local Loopback
Internal Local Loopback
Rx/Tx
Mode
Rx/Tx Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Null Command
Reserved
Reset Highest IUS
Reserved
Trigger Channel Load DMA
Trigger Rx DMA
Trigger Tx DMA
Trigger Rx & Tx DMA
Reserved
Rx FIFO Purge
Tx FIFO Purge
Rx & Tx FIFO Purge
Reserved
Load Rx Character Count
Load Tx Character Count
Load Rx & Tx Character Count
Reserved
Load TC0
Load TC1
Load TC0 & TC1
Select Serial Data LSB First *
Select Serial Data MSB First
Select Straight Memory Data *
Select Swapped Memory Data
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Channel
Command
(WO)
*
Selected
Upon Reset
Figure 34. Channel Command/Address Register (CCAR)
PS97USC0200
47
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Asynchronous
External Synchronous
Isochronous
Asynchronous with CV
Monosync
Bisync
HDLC
Transparent Bisync
NBIP
802.3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Receiver
Mode
Rx Submode 0
Rx Submode 1
Rx Submode 2
Rx Submode 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Asynchronous
Reserved
Isochronous
Asynchronous with CV
Monosync
Bisync
HDLC
Transparent Bisync
NBIP
802.3
Reserved
Reserved
Slaved Monosync
Reserved
HDLC Loop
Reserved
Transmitter
Mode
Tx Submode 0
Tx Submode 1
Tx Submode 2
Tx Submode 3
Figure 35. Channel Mode Register (CMR)
48
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
0
0
1
1
0
1
0
1
D3
D2
D1
D0
0
0
0
0
16X Data Rate
32X Data Rate
64X Data Rate
Reserved
Asynchronous
Receiver
Mode
Rx Clock
Rate
Reserved
Reserved
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
16X Data Rate
32X Data Rate
64X Data Rate
Reserved
One Stop Bit
Two Stop Bits
One Stop Bit, Shaved
Two Stop Bits, Shaved
Transmitter
Mode
Asynchronous
Tx Clock
Rate
Tx Stop
Bits
Figure 36. Channel Mode Register, Asynchronous Mode
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
External Sync
Receiver
Mode
Reserved
0
0
0
1
Reserved
Transmitter
Mode
Reserved
Figure 37. Channel Mode Register, External Sync Mode
PS97USC0200
49
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
Isochronous
Receiver
Mode
Reserved
0
0
1
0
Isochronous
Transmitter
Mode
Reserved
Tx Two Stop Bits
Reserved
Figure 38. Channel Mode Register, Isochronous Mode
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
Receiver
Mode
Asynchronous with CV
Rx Extended Word
Reserved
0
0
1
1
Asynchronous with CV
Transmitter
Mode
CV Polarity
Tx Extended Word
0
0
1
1
0
1
0
1
One Stop Bit
Two Stop Bits
No Stop Bit
Reserved
Tx
Stop Bits
Figure 39. Channel Mode Register, Asynchronous Mode
with Code Violation (MIL STD 1553)
50
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
Monosync
Receiver
Mode
Rx Short Sync Character
Rx Sync Strip
Reserved
0
1
0
0
Transmitter
Mode
Monosync
Tx Short Sync Character
Tx Preamble Enable
Reserved
Tx CRC on Underrun
Figure 40. Channel Mode Register, Monosync Mode
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
Bisync
Receiver
Mode
Rx Short Sync Character
Rx Sync Strip
Reserved
0
1
0
1
Bisync
Transmitter
Mode
Tx Short Sync Character
Tx Preamble Enable
0
0
1
1
0
1
0
1
SYN1
SYN0/SYN1
CRC/SYN1
CRC/SYN0/SYN1
Tx
Underrun
Condition
Figure 41. Channel Mode Register, Bisync Mode
PS97USC0200
51
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
0
0
1
1
D4
0
1
0
1
D3
D2
D1
D0
0
1
1
0
HDLC
Disabled
One Byte, No Control
One Byte, Plus Control
Extended, Plus Control
Receiver
Mode
Rx Address
Search Mode
Rx 16-Bit Control
Rx Logical Control Enable
0
1
1
0
HDLC
Transmitter
Mode
Shared Zero Flags
Tx Preamble Enable
0
0
1
1
0
1
0
1
Abort
Extended Abort
Flag
CRC/Flag
Tx
Underrun
Condition
Figure 42. Channel Mode Register, HDLC Mode
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
Transparent Bisync
Receiver
Mode
EBCDIC
Reserved
0
1
1
1
Transparent Bisync
Transmitter
Mode
EBCDIC
Tx Preamble Enable
0
0
1
1
0
1
0
1
SYN
DLE/SYN
CRC/SYN
CRC/DLE/SYN
Tx
Underrun
Condition
Figure 43. Channel Mode Register, Transparent Bisync Mode
52
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
0
0
1
1
D4
0
1
0
1
D3
D2
D1
D0
1
0
0
0
16X Data Rate
32X Data Rate
64X Data Rate
Reserved
Receiver
Mode
NBIP
Rx Clock
Rate
Rx Parity on Data
Reserved
1
0
0
1
1
0
1
0
1
0
0
0
Transmitter
Mode
NBIP
16X Data Rate
32X Data Rate
64X Data Rate
Reserved
Tx Clock
Rate
Tx Parity on Data
Tx Address Bit
Figure 44. Channel Mode Register, NBIP Mode
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
802.3
Receiver
Mode
Rx Address Search
Reserved
1
0
0
1
802.3
Transmitter
Mode
Reserved
Tx CRC on Underrun
Figure 45. Channel Mode Register, 802.3 Mode
PS97USC0200
53
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
1
1
D1
D0
0
0
Reserved
Receiver
Mode
Reserved
1
1
0
0
Slaved Monosync
Transmitter
Mode
Tx Short Sync Character
Tx Active on Received Sync
Reserved
Tx CRC on Underrun
Figure 46. Channel Mode Register, Slaved Monosync Mode
Address: 00001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
Reserved
Receiver
Mode
Reserved
1
1
1
0
HDLC Loop
Transmitter
Mode
Shared-Zero Flags
Tx Active on Poll
0
0
1
1
0
1
0
1
Abort
Extended Abort
Flag
CRC/Flag
Tx Underrun
Condition
Figure 47. Channel Mode Register, HDLC Loop Mode
54
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 00010
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 Bits
1 Bit
2 Bits
3 Bits
4 Bits
5 Bits
6 Bits
7 Bits
HDLC Tx Last
Character Length
Counter By-pass Enable
Loop Sending (RO)
On Loop (RO)
0
0
1
1
0
1
0
1
Both Edges
Rising Edge Only
Falling Edge Only
Adjust/Sync Inhibit
DPLL Adjust/Sync Edge
Clock Missed Latched/Unlatch
2 Clocks Missed Latched/Unlatch
DPLL in Sync/Quick Sync
RCC FIFO Clear (WO)
RCC FIFO Valid (RO)
RCC FIFO Overflow (RO)
Figure 48. Channel Command/Status Register (CCSR)
PS97USC0200
55
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 00011
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Wait for Rx DMA Trigger
0
0
1
1
0
1
0
1
No Status Block
One Word Status Block
Two Word Status Block
Reserved
Rx Status
Block Transfer
Tx Shaved Bit Length
(Async Only)
0
0
1
1
0
1
0
1
All Zeros
All Ones
Alternating 1 and 0
Alternating 0 and 1
Tx Preamble
Pattern
(All Sync)
0
0
1
1
0
1
0
1
8 Bits
16 Bits
32 Bits
64 Bits
Tx Preamble
Length
Tx Flag Preamble
Wait for Tx DMA Trigger
0
0
1
1
0
1
0
1
No Status Block
One Word Status Block
Two Word Status Block
Reserved
Tx Control
Block Transfer
Figure 49. Channel Control Register (CCR)
56
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 00100
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
/Port Bit 0 (RO)
Port Bit 0 Latched/Unlatch
/Port Bit 1 (RO)
Port Bit 1 Latched/Unlatch
/Port Bit 2 (RO)
Port Bit 2 Latched/Unlatch
/Port Bit 3 (RO)
Port Bit 3 Latched/Unlatch
/Port Bit 4 (RO)
Port Bit 4 Latched/Unlatch
/Port Bit 5 (RO)
Port Bit 5 Latched/Unlatch
/Port Bit 6 (RO)
Port Bit 6 Latched/Unlatch
/Port Bit 7 (RO)
Port Bit 7 Latched/Unlatch
Figure 50. Port Status Register (PSR)
PS97USC0200
57
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 00101
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Tri-State Output
Tx Complete Output
Output 0
Output 1
0
1
0
1
D1
D0
0
0
1
1
0
1
0
1
Tri-State Output
CLK0 Input
Output 0
Output 1
Tri-State Output
CLK1 Input
Output 0
Output 1
Tri-State Output
Reserved
Output 0
Output 1
Tri-State Output
Rx TSA Gate Output
Output 0
Output 1
Tri-State Output
Tx TSA Gate Output
Output 0
Output 1
Tri-State Output
Rx Sync Output
Output 0
Output 1
Tri-State Output
Frame Sync Input
Output 0
Output 1
0
1
0
1
D2
Port Bit 0
Pin Control
Port Bit 1
Pin Control
Port Bit 2
Pin Control
Port Bit 3
Pin Control
Port Bit 4
Pin Control
Port Bit 5
Pin Control
Port Bit 6
Pin Control
Port Bit 7
Pin Control
Figure 51. Port Control Register (PCR)
58
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 00110
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Test Data <0>
Test Data <1>
Test Data <2>
Test Data <3>
Test Data <4>
Test Data <5>
Test Data <6>
Test Data <7>
Test Data <8>
Test Data <9>
Test Data <10>
Test Data <11>
Test Data <12>
Test Data <13>
Test Data <14>
Test Data <15>
Figure 52. Test Mode Data Register (TMDR)
PS97USC0200
59
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 00111
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Null Address
High Byte of Shifters
CRC Byte 0
CRC Byte 1
Rx FIFO (Write)
Clock Multiplexer Outputs
CTR0 and CTR1 Counters
Clock Multiplexer Inputs
DPLL State
Low Byte of Shifters
CRC Byte 2
CRC Byte 3
Tx FIFO (Read)
Reserved
I/O and Device Status Latches
Internal Daisy Chain
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rx Count Holding Register
Reserved
Reserved
Reserved
Reserved
4453H
Reserved
Reserved
Reserved
4453H
Test
Register
Address
Reserved
Figure 53. Test Mode Control Register (TMCR)
Note:
When software writes the value 1F to the LS byte of the Test Mode Control Register (TMCR),
and then reads the Test Mode Data Register (TMDR), current versions of the Z16C32 will return
hex 4453. Future revisions, if any, will return other values.
60
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 01000
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disabled
Port1 Pin
/RxC Pin
/TxC Pin
0
1
0
1
Disabled
Port0 Pin
/RxC Pin
/TxC Pin
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
D3
0
1
0
1
0
1
0
1
BRG0 Output
BRG1 Output
/RxC Pin
/TxC Pin
CTR0 Output
CTR1 Output
/RxC Pin
/TxC Pin
CTR0 Output
CTR1 Output
/RxC Pin
/TxC Pin
D4
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disabled
/RxC Pin
/TxC Pin
DPLL Output
BRG0 Output
BRG1 Output
CTR0 Output
CTR1 Output
Disabled
/RxC Pin
/TxC Pin
DPLL Output
BRG0 Output
BRG1 Output
CTR0 Output
CTR1 Output
Receive Clock
Source
Transmit Clock
Source
DPLL Clock
Source
BRG0 Clock
Source
BRG1 Clock
Source
CTR0 Clock
Source
CTR1 Clock
Source
Figure 54. Clock Mode Control Register (CMCR)
PS97USC0200
61
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 01001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BRG0 Enable
BRG0 Single Cycle/Continuous
Reserved
BRG1 Enable
BRG1 Single Cycle/Continuous
Reserved
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disabled
NRZ/NRZI
Biphase-Mark/Space
Biphase-Level
32x Clock Mode
16x Clock Mode
8x Clock Mode
Reserved
DPLL
Divider
DPLL Clock
Divider
Code Violations OK
CTR1 Rate Match DPLL/CTR0
0
0
1
1
0
1
0
1
32x Clock Mode
16x Clock Mode
8x Clock Mode
4x Clock Mode
CTR0 Clock
Divider
Figure 55. Hardware Configuration Register (HCR)
62
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 01010
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IV <0>
IV <1>
IV <2>
IV <3>
IV <4>
IV <5>
IV <6>
IV <7>
IV <0> (RO)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
Device Status
I/O Status
Transmit Data
Transmit Status
Receive Data
Receive Status
Not Used
Type
Code
IV <4> (RO)
IV <5> (RO)
IV <6> (RO)
IV <7> (RO)
Figure 56. Interrupt Vector Register (IVR)
PS97USC0200
63
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 01011
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
D3
0
1
0
1
0
1
0
1
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3-State Output
Rx Request Output
Output 0
Output 1
Input Pin
Rx Clock Output
Rx Byte Clock Output
SYNC Output
BRG0 Output
BRG1 Output
CTR0 Output
DPLL Rx Output
Input PIn
Tx Clock Output
Tx Byte Clock Output
Tx Complete Output
BRG0 Output
BRG1 Output
CTR1 Output
DPLL Tx Output
Tx Data Output
3-State Output
Output 0
Output 1
3-State Output
Tx Request Output
Output 0
Output 1
/DCD Input
/DCD//SYNC Input
Output 0
Output 1
/CTS Input
/CTS Input
Output 0
Output 1
0
1
0
1
D4
/RxC Pin
Control
/TxC
Pin Control
TxD Pin
Control
/RxREQ
Pin Control
/TxREQ
Pin Control
/DCD
Pin Control
/CTS
Pin Control
Figure 57. I/O Control Register (IOCR)
64
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 01100
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Device Status IE
I/O Status IE
Transmit Data IE
Transmit Status IE
Receive Data IE
Receive Status IE
0
0
1
1
0
1
0
1
Null Command
Null Command
Reset IE
Set IE
IE Command
(WO)
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
All
All
I/O Status and Above
Transmit Data and Above
Transmit Status and Above
Receive Data and Above
Receive Status Only
None
VIS
Level
VIS
NV
DLC
MIE
Figure 58. Interrupt Control Register (ICR)
PS97USC0200
65
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 01101
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Device Status IP
I/O Status IP
Transmit Data IP
Transmit Status IP
Receive Data IP
Receive Status IP
0
0
1
1
0
1
0
1
Null Command
Reset IP and IUS
Reset IP
Set IP
IP Command
(WO)
Device Status IUS
I/O Status IUS
Transmit Data IUS
Transmit Status IUS
Receive Data IUS
Receive Status IUS
0
0
1
1
0
1
0
1
Null Command
Null Command
Reset IUS
Set IUS
IUS Command
(WO)
Figure 59. Daisy-Chain Control Register (DCCR)
66
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 01110
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BRG0 ZC Latched/Unlatch
BRG1 ZC Latched/Unlatch
DPLL SYNC Latched/Unlatch
RCC Overflow Latched/Unlatch
/CTS (RO)
/CTS Latched/Unlatch
/DCD (RO)
/DCD Latched/Unlatch
/TxREQ (RO)
/TxREQ Latched/Unlatch
/RxREQ (RO)
/RxREQ Latched/Unlatch
/TxC (RO)
/TxC Latched/Unlatch
/RxC (RO)
/RxC Latched/Unlatch
Figure 60. Miscellaneous Interrupt Status Register (MISR)
PS97USC0200
67
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 01111
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BRG0 ZC IA
BRG1 ZC IA
DPLL SYNC IA
RCC Overflow IA
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disabled
Rising Edge Only
Falling Edge Only
Both Edges
Disabled
Rising Edge Only
Falling Edge Only
Both Edges
Disabled
Rising Edge Only
Falling Edge Only
Both Edges
Disabled
Rising Edge Only
Falling Edge Only
Both Edges
Disabled
Rising Edge Only
Falling Edge Only
Both Edges
Disabled
Rising Edge Only
Falling Edge Only
Both Edges
0
1
0
1
0
1
0
1
/CTS
Interrupt
Arm
/DCD
Interrupt
Arm
/TxREQ
Interrupt
Arm
/RxREQ
Interrupt
Arm
/TxC
Interrupt
Arm
/RxC
Interrupt
Arm
Figure 61. Status Interrupt Control Register (SICR)
68
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 1x000
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RxDAT <0> (RO)
RxDAT <1> (RO)
RxDAT <2> (RO)
RxDAT <3> (RO)
RxDAT <4> (RO)
RxDAT <5> (RO)
RxDAT <6> (RO)
RxDAT <7> (RO)
RxDAT <8> (RO)
RxDAT <9> (RO)
RxDAT <10> (RO)
RxDAT <11> (RO)
RxDAT <12> (RO)
RxDAT <13> (RO)
RxDAT <14> (RO)
RxDAT <15> (RO)
Figure 62. Receive Data Register (RDR)
PS97USC0200
69
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 10001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
0
0
0
0
1
1
1
1
D3
0
0
1
1
0
0
1
1
D2
0
1
0
1
0
1
0
1
D1
D0
0
0
1
1
0
1
0
1
8 Bits
1 Bit
2 Bits
3 Bits
4 Bits
5 Bits
6 Bits
7 Bits
Disable Immediately
Disable After Reception
Enable Without Auto-Enables
Enable With Auto-Enables
Rx
Enable
Rx Character
Length
Rx Parity Enable
0
0
1
1
0
1
0
1
Even
Odd
Space
Mark
Rx Parity
Type
Abort Frame Status
Rx CRC Enable
Rx CRC Preset Value
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
CRC-CCITT
CRC-16
CRC-32
Reserved
NRZ
NRZB
NRZI-Mark
NRZI-Space
Biphase-Mark
Biphase-Space
Biphase-Level
Diff. Biphase-Level
Rx CRC
Polynomial
Rx Data
Decoding
Figure 63. Receive Mode Register (RMR)
70
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 10010
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Rx Character Available (RO)
Rx Overrun
Parity Error/Rx Frame Abort
CRC/Framing Error (RO)
Rx CV/EOT/EOF
Rx Break/Abort
Rx Idle
Exited Hunt
Short Frame/CV Polarity (RO)
Residue Code 0 (RO)
Residue Code 1 (RO)
Residue Code 2 (RO)
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
Null Command
Reserved
Preset CRC
Enter Hunt Mode
Select Timeslot Assignment
Select FIFO Status
Select FIFO Interrupt Level
Select FIFO Request Level
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Receive
Command (WO)
First Byte in Error (RO)
Second Byte in Error (RO)
Figure 64. Receive Command Status Register (RCSR)
PS97USC0200
71
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 10011
D15 D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TC0R Read Count/TC
Rx Overrun IA
Parity Error/Frame Abort IA
Status on Words
Rx CV/EOT/EOF IA
Rx Break/Abort IA
Rx Idle IA
Exited Hunt IA
Rx FIFO Control and Status
(Fill/Interrupt/DMA Level)
Figure 65a. Receive Interrupt Control Register (RICR)
Address: 10011
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TC0R Read Count/TC
Rx Overrun IA
Parity Error/Frame Abort IA
Status on Words
Rx CV/EOT/EOF IA
Rx Break/Abort IA
Rx Idle IA
Exited Hunt IA
0
Timeslot (0-127)
Figure 65b. Receive Interrupt Control Register (RICR)
72
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 10011
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TC0R Read Count/TC
Rx Overrun IA
Parity Error/Frame Abort IA
Status on Words
Rx CV/EOT/EOF IA
Rx Break/Abort IA
Rx Idle IA
Exited Hunt IA
1 (WO)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No Offset
7 Clocks Offset
6 Clocks Offset
5 Clocks Offset
4 Clocks Offset
3 Clocks Offset
2 Clocks Offset
1 Clock Offset
No Slot (Disabled)
1 Slot
2 Slots
3 Slots
4 Slots
5 Slots
6 Slots
7 Slots
8 Slots
9 Slots
10 Slots
11 Slots
12 Slots
13 Slots
14 Slots
15 Slots
Concatenated
Slots (WO)
Slot Offset
(WO)
Figure 65c. Receive Interrupt Control Register (RICR)
PS97USC0200
73
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 10100
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RSYN <0>
RSYN <1>
RSYN <2>
RSYN <3>
RSYN <4>
RSYN <5>
RSYN <6>
RSYN <7>
RSYN <8>
RSYN <9>
RSYN <10>
RSYN <11>
RSYN <12>
RSYN <13>
RSYN <14>
RSYN <15>
Figure 66. Receive Sync Register (RSR)
74
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 10101
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RCL <0>
RCL <1>
RCL <2>
RCL <3>
RCL <4>
RCL <5>
RCL <6>
RCL <7>
RCL <8>
RCL <9>
RCL <10>
RCL <11>
RCL <12>
RCL <13>
RCL <14>
RCL <15>
Figure 67. Receive Count Limit Register (RCLR)
PS97USC0200
75
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 10110
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RCC <0> (RO)
RCC <1> (RO)
RCC <2> (RO)
RCC <3> (RO)
RCC <4> (RO)
RCC <5> (RO)
RCC <6> (RO)
RCC <7> (RO)
RCC <8> (RO)
RCC <9> (RO)
RCC <10> (RO)
RCC <11> (RO)
RCC <12> (RO)
RCC <13> (RO)
RCC <14> (RO)
RCC <15> (RO)
Figure 68. Receive Character Count Register (RCCR)
76
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 10111
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TC0 <0>
TC0 <1>
TC0 <2>
TC0 <3>
TC0 <4>
TC0 <5>
TC0 <6>
TC0 <7>
TC0 <8>
TC0 <9>
TC0 <10>
TC0 <11>
TC0 <12>
TC0 <13>
TC0 <14>
TC0 <15>
Figure 69. Time Constant 0 Register (TC0R)
PS97USC0200
77
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 1x000
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TxDAT <0> (WO)
TxDAT <1> (WO)
TxDAT <2> (WO)
TxDAT <3> (WO)
TxDAT <4> (WO)
TxDAT <5> (WO)
TxDAT <6> (WO)
TxDAT <7> (WO)
TxDAT <8> (WO)
TxDAT <9> (WO)
TxDAT <10> (WO)
TxDAT <11> (WO)
TxDAT <12> (WO)
TxDAT <13> (WO)
TxDAT <14> (WO)
TxDAT <15> (WO)
Figure 70. Transmit Data Register (TDR)
78
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 11001
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
0
0
0
0
1
1
1
1
D3
0
0
1
1
0
0
1
1
D2
0
1
0
1
0
1
0
1
D1
D0
0
0
1
1
0
1
0
1
8 Bits
1 Bit
2 Bits
3 Bits
4 Bits
5 Bits
6 Bits
7 Bits
Disable Immediately
Disable After Transmission
Enable Without Auto-Enables
Enable With Auto-Enables
Tx
Enable
Tx Character
Length
Tx Parity Enable
0
0
1
1
0
1
0
1
Even
Odd
Space
Mark
Tx Parity
Sense
Tx CRC on EOF/EOM
Tx CRC Enable
Tx CRC Start Value
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
CRC-CCITT
CRC-16
CRC-32
Reserved
NRZ
NRZB
NRZI-Mark
NRZI-Space
Biphase-Mark
Biphase-Space
Biphase-Level
Diff. Biphase-Level
Tx CRC
Type
Tx Data
Encoding
Figure 71. Transmit Mode Register (TMR)
PS97USC0200
79
P R E L I M I N A R Y
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Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 11010
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Tx Buffer Empty (RO)
Tx Underrun
All Sent (RO)
Tx CRC Sent
Tx EOF/EOT Sent
Tx Abort Sent
Tx Idle Sent
Tx Preamble Sent
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SYNC/Flag/Normal
Alternating 1 and 0
All Zeros
All Ones
Reserved
Alternating Mark and Space
Space
Mark
Tx Idle Line
Condition
Reserved
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Null Command
Reserved
Preset CRC
Reserved
Select Timeslot Assignment
Select FIFO Status
Select Interrupt Level
Select Request Level
Send Frame/Message
Send Abort
Reserved
Reserved
Reset DLE Inhibit
Set DLE Inhibit
Reset EOF/EOM
Set EOF/EOM
Transmit
Command (WO)
Figure 72. Transmit Command/Status Register (TCSR)
80
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 11011
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TC1R Read Count/TC
Tx Overrun IA
Wait for Send Command
Tx CRC Sent IA
Tx EOF/EOT Sent IA
Tx Abort Sent IA
Tx Idle Sent IA
Tx Preamble Sent IA
Tx FIFO Control and Status
(Fill/Interrupt/DMA Level)
Figure 73a. Transmit Interrupt Control Register (TICR)
Address: 11011
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TC1R Read Count/TC
Tx Underrun IA
Wait for Send Command
Tx CRC Sent IA
Tx EOF/EOT Sent IA
Tx Abort Sent IA
Tx Idle Sent IA
Tx Preamble Sent IA
0
Timeslot (0-127)
Figure 73b. Transmit Interrupt Control Register (TICR)
PS97USC0200
81
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 11011
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TC1R Read Count/TC
Tx Underrun IA
Wait for Send Command
Tx CRC Sent IA
Tx EOF/EOT Sent IA
Tx Abort Sent IA
Tx Idle Sent IA
Tx Preamble Sent IA
1 (WO)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No Offset
7 Clocks Offset
6 Clocks Offset
5 Clocks Offset
4 Clocks Offset
3 Clocks Offset
2 Clocks Offset
1 Clock Offset
No Slot (Disabled)
1 Slot
2 Slots
3 Slots
4 Slots
5 Slots
6 Slots
7 Slots
8 Slots
9 Slots
10 Slots
11 Slots
12 Slots
13 Slots
14 Slots
15 Slots
Concatenated
Slots (WO)
Slot Offset
(WO)
Figure 73c. Transmit Interrupt Control Register (TICR)
82
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 11100
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TSYN <0>
TSYN <1>
TSYN <2>
TSYN <3>
TSYN <4>
TSYN <5>
TSYN <6>
TSYN <7>
TSYN <8>
TSYN <9>
TSYN <10>
TSYN <11>
TSYN <12>
TSYN <13>
TSYN <14>
TSYN <15>
Figure 74. Transmit Sync Register (TSR)
PS97USC0200
83
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 11101
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TCL <0>
TCL <1>
TCL <2>
TCL <3>
TCL <4>
TCL <5>
TCL <6>
TCL <7>
TCL <8>
TCL <9>
TCL <10>
TCL <11>
TCL <12>
TCL <13>
TCL <14>
TCL <15>
Figure 75. Transmit Count Limit Register (TCLR)
84
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
Address: 11110
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TCC <0> (RO)
TCC <1> (RO)
TCC <2> (RO)
TCC <3> (RO)
TCC <4> (RO)
TCC <5> (RO)
TCC <6> (RO)
TCC <7> (RO)
TCC <8> (RO)
TCC <9> (RO)
TCC <10> (RO)
TCC <11> (RO)
TCC <12> (RO)
TCC <13> (RO)
TCC <14> (RO)
TCC <15> (RO)
Figure 76. Transmit Character Count Register (TCCR)
PS97USC0200
85
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: 11111
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TC1 <0>
TC1 <1>
TC1 <2>
TC1 <3>
TC1 <4>
TC1 <5>
TC1 <6>
TC1 <7>
TC1 <8>
TC1 <9>
TC1 <10>
TC1 <11>
TC1 <12>
TC1 <13>
TC1 <14>
TC1 <15>
Figure 77. Time Constant 1 Register (TC1R)
86
PS97USC0200
P R E L I M I N A R Y
ZILOG
Address: None
Z16C32 IUSC™
*
D15 D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RCC <0>
Rx Overrun
Parity Error Rx/Frame Abort
CRC Error
Rx Bound
0
0
0
Short Frame/CV Polarity
Residue Code 0
Residue Code 1
Residue Code 2
0
0
First Byte in Error
Second Byte in Error
*
Refer to Figure 22 (Channel Control Register)
Bits 6-7 for Access Method
Figure 78. Receive Status Block Register (RSBR)
PS97USC0200
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P R E L I M I N A R Y
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Z16C32 IUSC™
CONTROL REGISTERS (Continued)
Address: None
*
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 Bits
1 Bit
2 Bits
3 Bits
4 Bits
5 Bits
6 Bits
7 Bits
HDLC Tx Last
Character Length
Reserved
Tx Submode 0
Tx Submode 1
Tx Submode 2
Tx Submode 3
*
Refer to Figure 22 (Channel Control Register)
Bits15-14 for Access Method
Figure 79. Transmit Status Block Register (TSBR)
Address: none
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Shift Right Address
/INT Open-Drain
16-Bit Bus
/BUSREQ Type
0
0
1
1
0
1
0
1
Status Acknowledge
Single Pulse Acknowledge
Reserved
Double Pulse Acknowledge
INTACK Mode
0*
Tri-State All Pins
Separate Address for 8-Bit Bus
* Must be programmed as 0.
Figure 80. Bus Configuration Register (BCR)
88
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
ABSOLUTE MAXIMUM RATINGS
Symbol
Description
Min
VCC
TSTG
TA
Supply Voltage (*)
–0.3
Storage Temp
–65°
Oper Ambient Temp
Power Dissipation
Max
Units
+7.0
+150°
†
2.2
V
C
C
W
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Notes:
* Voltage on all pins with respect to GND.
† See Ordering Information.
STANDARD TEST CONDITIONS
+5V
The DC Characteristics and Capacitance Section below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to Ground.
Positive current flows into the referenced pin (Figure 81).
Standard conditions are as follows:
■
+4.5 V < VCC < +5.5 V
■
GND = 0 V
■
TA as specified in Ordering Information
1.73 K
From Output
Under Test
250 µA
50 pF
Figure 81. Standard Test Load
CAPACITANCE
Symbol
CIN
COUT
CI/O
Parameter
Input Capacitance
Output Capacitance
Bidirectional Capacitance
Min
Max
Unit
Condition
10
15
20
pF
pF
pF
*
*
Notes:
F = 1 MHz, over specified temperature range.
* Unmeasured pins returned to Ground.
MISCELLANEOUS
Transistor Count - 100,000
TEMPERATURE RANGE
Standard = 0°C to 70°C
PS97USC0200
89
P R E L I M I N A R Y
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Z16C32 IUSC™
IUSC TIMING
The IUSC interface timing is similar to that found on a static
RAM, except that it is much more flexible. Up to four
separate timing strobe signals are present on the interface: /DS, /RD, /WR and /INTACK. Only one of these timing
strobes is active at any time. Should the external logic
activate more than one of these strobes at the same time,
the IUSC will enter a pre-reset state. This state is only
exited by a hardware reset. Do not allow overlap of timing
strobes. The timing diagrams, beginning on the next page,
illustrate the different bus transactions possible with the
necessary setup, hold, and delay times. IUSC Timing
diagrams are shown from Figure 82 through Figure 106.
DC CHARACTERISTICS
Symbol
Parameter
Min
VIH
VIL
VOH1
Input High Voltage
Input Low Voltage
Output High Voltage
2.2
–0.3
2.4
VOH2
VOL
IIL
IOL
ICC1
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
VCC Supply Current
VCC –0.8
Typ
Max
Unit
VCC +0.3
0.8
V
V
V
V
V
µA
µA
mA
0.4
+10.00
+10.00
50
7
Condition
IOH = –1.6 mA
IOH = –250 µA
IOL = +2.0 mA
0.4 < VIN < +2.4V
0.4 < VOUT < +2.4V
VCC = 5V VIH = 4.8V VIL = 0.2V
Note:
VCC = 5V ± 10% unless otherwise specified, over specified temperature range.
AC CHARACTERISTICS
Timing Diagrams (Figures 82-104)
/RESET
113
114
/STB
115
Figure 82. Reset Timing
/STB
112
1
1
Figure 83. Bus Cycle Timing
Note:
/STB is any of the following: /DS, /RD, /WR or Pulsed /INTACK.
90
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Diagrams (Continued)
/CS
12
13
14
15
16
17
S//D, D//C
/INTACK
(Status)
/AS
6
7
2
3
1
R//W
20
21
/DS
4
5
AD15-AD0
18
19
8
10
11
9
/RxREQ
22
23
/WAIT//RDY
(Wait)
/WAIT//RDY
(Ready)
116
79
80
Figure 84. Multiplexed /DS Read Cycle
PS97USC0200
91
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Diagrams (Continued)
/CS
12
13
14
15
16
17
S//D, D//C
/INTACK
(Status)
/AS
2
6
7
1
R//W
20
21
/DS
4
5
AD15-AD0
18
19
24
25
/TxREQ
26
27
/WAIT//RDY
(Wait)
/WAIT//RDY
(Ready)
116
80
Figure 85. Multiplexed /DS Write Cycle
92
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
/CS
12
13
14
15
16
17
S//D, D//C
/INTACK
(Status)
/AS
2
30
31
1
/RD
28
29
AD15-AD0
18
19
32
34
33
35
/RxREQ
36
37
/WAIT//RDY
(Wait)
/WAIT//RDY
(Ready)
119
79
90
Figure 86. Multiplexed /RD Read Cycle
PS97USC0200
93
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Diagrams (Continued)
/CS
12
13
14
15
16
17
S//D, D//C
/INTACK
(Status)
/AS
2
40
41
1
/WR
38
39
AD15-AD0
18
19
42
43
/TxREQ
44
45
/WAIT//RDY
(Wait)
/WAIT//RDY
(Ready)
117
118
Figure 87. Multiplexed /WR Write Cycle
94
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
/CS
46
47
48
49
50
51
20
21
S//D, D//C
/INTACK
(Status)
R//W
/DS
4
5
1
AD15-AD0
8
10
11
9
/RxREQ
22
23
/WAIT//RDY
(Wait)
/WAIT//RDY
(Ready)
116
79
80
Figure 88. Non-Multiplexed /DS Read Cycle
PS97USC0200
95
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Diagrams (Continued)
/CS
46
47
48
49
50
51
20
21
S//D, D//C
/INTACK
(Status)
R//W
/DS
4
5
1
AD15-AD0
24
25
/TxREQ
26
27
/WAIT//RDY
(Wait)
/WAIT//RDY
(Ready)
116
80
Figure 89. Non-Multiplexed /DS Write Cycle
96
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
/CS
52
53
54
55
56
57
S//D, D//C
/INTACK
(Status)
/RD
28
29
1
AD15-AD0
32
34
33
35
/RxREQ
36
37
/WAIT//RDY
(Wait)
/WAIT//RDY
(Ready)
119
79
90
Figure 90. Non-Multiplexed /RD Read Cycle
PS97USC0200
97
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Diagrams (Continued)
/CS
58
59
60
61
62
63
S//D, D//C
/INTACK
(Status)
/WR
38
39
1
AD15-AD0
42
43
/TxREQ
44
45
/WAIT//RDY
(Wait)
/WAIT//RDY
(Ready)
117
118
Figure 91. Non-Multiplexed /WR Write Cycle
98
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
/AS
2
6
7
1
/INTACK
(Status)
16
17
/DS
4
5
AD15-AD0
18
8
19
10
86
/WAIT//RDY
(Wait)
11
87
88
79
/WAIT//RDY
(Ready)
78
80
IEI
81
82
IEO
83
84
/INT
85
Figure 92. Multiplexed /DS Interrupt Acknowledge Cycle
PS97USC0200
99
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Diagrams (Continued)
/AS
2
30
31
/INTACK
(Status)
16
17
/RD
28
29
AD15-AD0
18
32
19
34
94
/WAIT//RDY
(Wait)
35
95
88
79
/WAIT//RDY
(Ready)
89
90
IEI
91
92
IEO
83
84
/INT
93
Figure 93. Multiplexed /RD Interrupt Acknowledge Cycle
100
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
/AS
2
98
99
1
/INTACK
(Pulsed)
96
97
AD15-AD0
18
100
19
101
102
109
/WAIT//RDY
(Wait)
110
88
79
/WAIT//RDY
(Ready)
107
108
IEI
103
104
IEO
83
105
/INT
106
Figure 94. Multiplexed Pulsed Interrupt Acknowledge Cycle
PS97USC0200
101
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Diagrams (Continued)
/INTACK
(Status)
50
51
/DS
4
5
1
AD15-AD0
8
10
86
11
/WAIT//RDY
(Wait)
87
88
79
/WAIT//RDY
(Ready)
78
80
IEI
81
82
IEO
83
111
/INT
85
Figure 95. Non-Multiplexed /DS Interrupt Acknowledge Cycle
102
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
/INTACK
(Status)
56
57
/RD
28
29
1
AD15-AD0
32
34
35
94
/WAIT//RDY
(Wait)
95
88
79
/WAIT//RDY
(Ready)
89
90
IEI
91
92
IEO
83
111
/INT
93
Figure 96. Non-Multiplexed /RD Pulsed Interrupt Acknowledge Cycle
PS97USC0200
103
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Diagrams (Continued)
/INTACK
(Pulsed)
96
97
1
AD15-AD0
100
101
79
107
102
/WAIT//RDY
(Ready)
108
IEI
103
104
IEO
83
105
/INT
106
109
/WAIT//RDY
(Wait)
110
88
Figure 97. Non-Multiplexed Pulsed Interrupt Acknowledge Cycle
104
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
/AS
2
98
99
99
2
98
1
1
/INTACK
(2-Pulse)
96
96
97
97
AD15-AD0
18
18
19
101
100
19
102
/WAIT//RDY
(Ready)
79
107
108
/WAIT//RDY
(Wait)
109
110
88
IEI
104
103
IEO
83
105
/INT
106
Figure 98. Multiplexed Double-Pulse Intack Cycle
PS97USC0200
105
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Diagrams (Continued)
/INTACK
(2-Pulse)
96
96
97
97
1
1
AD15-AD0
101
100
102
/WAIT//RDY
(Ready)
107
108
79
/WAIT//RDY
(Wait)
109
110
88
IEI
104
103
IEO
83
105
/INT
106
Figure 99. Non-Multiplexed Double-Pulse Intack Cycle
106
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CLK
/UAS
171
/AS
171
/DS
171
R//W
171
/RD
171
/WR
171
S//D, D//C
171
AD15-AD0
148
/BUSREQ
170
/BIN
172
173
172
173
Figure 100. DMA Start-Up
PS97USC0200
107
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Diagrams (Continued)
CLK
123
120
124
121
122
/UAS
125
127
126
/AS
128
130
129
135
136
/DS
131
133
132
134
R//W
137
142
143
/RD
138
140
139
141
S//D, D//C
144
149
150
151
152
AD15-AD0
148
145
146
147
/WAIT//RDY
(Wait)
153
154
155
156
/WAIT//RDY
(Ready)
/BIN
172
173
168
169
/ABORT
Figure 101. Memory Read
108
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CLK
123
120
124
121
122
/UAS
125
127
126
/AS
128
130
129
159
161
/DS
158
160
134
134
R//W
137
163
165
/WR
162
164
166
166
S//D, D//C
144
149
150
151
152
AD15-AD0
145
145
145
157
/WAIT//RDY
(Ready)
153
154
155
156
/WAIT//RDY
(Wait)
/BIN
172
173
168
169
/ABORT
Figure 102. Memory Write
PS97USC0200
109
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Diagrams (Continued)
CLK
/UAS
167
/AS
167
/DS
167
R//W
167
/RD
167
/WR
167
S//D, D//C
167
AD15-AD0
147
Figure 103. Bus Release
110
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
CLK
/BUSREQ
174
175
/BIN
/BOUT
176
Figure 104. Request Timing
PS97USC0200
111
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
Timing Table
No
Symbol
Parameter
Min
1
2
3
4
Tcyc
TwASl
TwASh
TwDSl
Bus Cycle Time
/AS Low Width
/AS High Width
/DS Low Width
160
40
90
70
ns
ns
ns
ns
5
6
7
8
TwDSh
TdAS(DS)
TdDS(AS)
TdDS(DRa)
/DS High Width
/AS Rise to /DS Fall Delay Time
/DS Rise to /AS Fall Delay Time
/DS Fall to Data Active Delay
60
5
5
0
ns
ns
ns
ns
9
10
11
12
TdDS(DRv)
TdDS(DRn)
TdDS(DRz)
TsCS(AS)
/DS Fall to Data Valid Delay
/DS Rise to Data Not Valid Delay
/DS Rise to Data Float Delay
/CS to /AS Rise Setup Time
15
ns
ns
ns
ns
13
14
15
ThCS(AS)
TsADD(AS)
ThADD(AS)
/CS to /AS Rise Hold Time
Direct Address to /AS Rise Setup Time
5
15
ns
ns
16
TsSIA(AS)
Direct Address to /AS Rise Hold Time
Status /INTACK to /AS Rise Setup Time
5
15
ns
ns
17
18
19
20
ThSIA(AS)
TsAD(AS)
ThAD(AS)
TsRW(DS)
Status /INTACK to /AS Rise Hold Time
Address to /AS Rise Setup Time
Address to /AS Rise Hold Time
R//W to /DS Fall Setup Time
5
15
5
0
ns
ns
ns
ns
21
22
23
24
ThRW(DS)
TsDSf(RRQ)
TdDSr(RRQ)
TsDW(DS)
R//W to /DS Fall Hold Time
/DS Fall to /RxREQ Inactive Delay
/DS Rise to /RxREQ Active Delay
Write Data to /DS Rise Setup Time
25
25
26
27
28
ThDW(DS)
TdDSf(TRQ)
TdDSr(TRQ)
TwRDl
Write Data to DS Rise Hold Time
/DS Fall to /TxREQ Inactive Delay
/DS Rise to /TxREQ Active Delay
/RD Low Width
0
70
ns
ns
ns
ns
29
30
31
32
TwRDh
TdAS(RD)
TdRD(AS)
TdRD(DRa)
/RD High Width
/AS Rise to /RD Fall Delay Time
/RD Rise to /AS Fall Delay Time
/RD Fall to Data Active Delay
60
5
5
0
ns
ns
ns
ns
33
34
35
36
TdRD(DRv)
TdRD(DRn)
TdRD(DRz)
TdRDf(RRQ)
/RD Fall to Data Valid Delay
/RD Rise to Data Not Valid Delay
/RD Rise to Data Float Delay
/RD Fall to /RxREQ Inactive Delay
37
38
39
40
TdRDr(RRQ)
TwWRl
TwWRh
TdAS(WR)
/RD Rise to /RxREQ Active Delay
/WR Low Width
/WR High Width
/AS Rise to /WR Fall Delay Time
0
70
60
5
ns
ns
ns
ns
41
42
43
44
TdWR(AS)
TsDW(WR)
ThDW(WR)
TdWRf(TRQ)
/WR Rise to /AS Fall Delay Time
Write Data to /WR Rise Setup Time
Write Data to /WR Rise Hold Time
/WR Fall to /TxREQ Inactive Delay
5
30
0
ns
ns
ns
ns
112
Max
85
0
20
60
0
30
0
60
85
0
20
60
60
Units
ns
ns
ns
ns
ns
ns
ns
ns
Note
[1]
[1]
[4]
[5]
[4]
[5]
PS97USC0200
P R E L I M I N A R Y
ZILOG
No
Symbol
Parameter
45
46
47
48
TdWRr(TRQ)
TsCS(DS)
ThCS(DS)
TsADD(DS)
/WR Rise to /TxREQ Active Delay
/CS to /DS Fall Setup Time
/CS to /DS Fall Hold Time
Direct Address to /DS Fall Setup Time
49
50
51
52
ThADD(DS)
TsSIA(DS)
ThSIA(DS)
TsCS(RD)
53
54
55
56
Z16C32 IUSC™
Min
Max
Units
Note
0
0
25
5
ns
ns
ns
ns
[2]
[2]
[1,2]
Direct Address to /DS Fall Hold Time
Status /INTACK to /DS Fall Setup time
Status /INTACK to /DS Fall Hold Time
/CS to /RD Fall Setup Time
25
5
25
0
ns
ns
ns
ns
[1,2]
[2]
[2]
[2]
ThCS(RD)
TsADD(RD)
ThADD(RD)
TsSIA(RD)
/CS to /RD Fall Hold Time
Direct Address to /RD Fall Setup Time
Direct Address to /RD Fall Hold Time
Status /INTACK to /RD Fall Setup Time
25
5
25
5
ns
ns
ns
ns
[2]
[1,2]
[1,2]
[2]
57
58
59
60
ThSIA(RD)
TsCS(WR)
ThCS(WR)
TsADD(WR)
Status /INTACK to /RD Fall Hold Time
/CS to /WR Fall Setup Time
/CS to /WR Fall Hold Time
Direct Address to /WR Fall Setup Time
25
0
25
5
ns
ns
ns
ns
[2]
[2]
[2]
[1,2]
61
62
63
78
ThADD(WR)
TsSIA(WR)
ThSIA(WR)
TdDSf(RDY)
Direct Address to /WR Fall Hold Time
Status /INTACK to /WR Fall Setup Time
Status /INTACK to /WR Fall Hold Time
/DS Fall (Intack) to /RDY Fall Delay
25
5
25
ns
ns
ns
ns
[1,2]
[2]
[2]
79
80
81
82
TdRDY(DRv)
TdDSr(RDY)
TsIEI(DSI)
ThIEI(DSI)
/RDY Fall to Data Valid Delay
/DS Rise to /RDY Rise Delay
IEI to /DS Fall (Intack) Setup Time
IEI to /DS Rise (Intack) Hold Time
83
84
85
86
TdIEI(IEO)
TdAS(IEO)
TdDSI(INT)
TdDSI(Wf)
87
88
89
90
200
40
40
ns
ns
ns
ns
IEI to IEO Delay
/AS Rise (Intack) to IEO Delay
/DS Fall to /INT Inactive Delay
/DS Fall (Intack) to /WAIT Fall Delay
60
60
200
40
ns
ns
ns
ns
TdDSI(Wr)
TdW(DRv)
TdRDf(RDY)
TdRDr(RDY)
/DS Fall (Intack) to /WAIT Rise Delay
/WAIT Rise to Data Valid Delay
/RD Fall (Intack) to /RDY Fall Delay
/RD Rise to /RDY Rise Delay
200
40
200
40
ns
ns
ns
ns
91
92
93
TsIEI(RDI)
ThIEI(RDI)
TdRDI(INT)
IEI to /RD Fall (Intack) Setup Time
IEI to /RD Rise (Intack) Hold Time
94
TdRDI(Wf)
/RD Fall (Intack) to /INT Inactive Delay
/RD Fall (Intack) to /WAIT Fall Delay
95
96
97
98
TdRDI(Wr)
TwPIAl
TwPIAh
TdAS(PIA)
/RD Fall (Intack) to /WAIT Rise Delay
Pulsed /INTACK Low Width
Pulsed /INTACK High Width
/AS Rise to Pulsed /INTACK Fall Delay Time
99
100
101
102
TdPIA(AS)
TdPIA(DRa)
TdPIA(DRn)
TdPIA(DRz)
Pulsed /INTACK Rise to /AS Fall Delay Time
Pulsed /INTACK Fall to Data Active Delay
Pulsed /INTACK Rise to Data Not Valid Delay
Pulsed /INTACK Rise to Data Float Delay
PS97USC0200
60
0
60
0
ns
ns
200
40
ns
ns
200
ns
ns
ns
ns
70
60
5
5
0
0
20
ns
ns
ns
ns
113
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS (Continued)
Timing Table
No
Symbol
Parameter
Min
103
104
105
106
TsIEI(PIA)
ThIEI(PIA)
TdPIA(IEO)
TdPIA(INT)
IEI to Pulsed /INTACK Fall Setup Time
IEI to Pulsed /INTACK Rise Hold Time
Pulsed /INTACK Fall to IEO Delay
Pulsed /INTACK Fall to /INT Inactive Delay
10
0
107
108
109
110
TdPIAf(RDY)
TdPIAr(RDY)
TdPIA(Wf)
TdPIA(Wr)
Pulsed /INTACK Fall to /RDY Fall Delay
Pulsed /INTACK Rise to /RDY Rise Delay
Pulsed /INTACK Fall to /WAIT Fall Delay
Pulsed /INTACK Fall to /WAIT Rise Delay
111
112
113
114
TdSIA(INT)
TwSTBh
TwRESl
TwRESh
Status /INTACK Fall to IEO Inactive Delay
/Strobe High Width
/RESET Low Width
/RESET High Width
115
116
117
118
TdRES(STB)
TdDSf(RDY)
TdWRf(RDY)
TdWRr(RDY)
/RESET Rise to /STB Fall
/DS Fall to /RDY Fall Delay
/WR Fall to /RDY Fall Delay
/WR Rise to /RDY Rise Delay
119
120
121a
121b
122a
122b
TdRDf(RDY)
TwCLKl
TwCLKh
TwCLKh
TcCLK
TcCLK
/RD Fall to /RDY Fall Delay
CLK Low Width
CLK High Width
CLK High Width (Linked List Mode)
CLK Cycle Time
CLK Cycle Time (Linked List Mode)
123
124
125
126
TfCLK
TrCLK
TdCLKr (UAS)
TwUASl
CLK Fall Time
CLK Rise Time
CLK Rise to /UAS Fall Delay
/UAS Low Width
127
128
129
130
TdCLKf(UAS)
TdCLKr(AS)
TwASl
TdCLKf(AS)
CLK Fall to /UAS Rise Delay
CLK Rise to /AS Fall Delay
/AS Low Width
CLK Fall to /AS Rise Delay
131
132
133
134
TdAS(DSr)
TdCLKr(DS)
TwDSlr
TdCLKf(DS)
/AS Rise to /DS Fall (Read) Delay
CLK Rise to /DS Delay
/DS (Read) Low Width
CLK Fall to /DS Delay
25
135
136
137
138
TsDR(DS)
ThDR(DS)
TdCLK(RW)
TdAS(RD)
Read Data to /DS Rise Setup Time
Read Data to /DS Rise Hold Time
CLK Rise to R//W Delay
/AS Rise to /RD Fall Delay
30
0
139
140
141
142
TdCLKr(RD)
TwRDl
TdCLKf(RD)
TsDR(RD)
CLK Rise to /RD Delay
/RD Low Width
CLK Fall to /RD Delay
Read Data to /RD Rise Setup Time
143
144
145
146
ThDR(RD)
TdCLK(ADD)
TdCLK(AD)
ThAD(PC)
Read Data to /RD Rise Hold Time
CLK Rise to Direct Address Delay
CLK Rise to Address Delay
Address to CLK Rise Hold Time
114
Max
Units
60
200
ns
ns
ns
ns
200
40
40
200
ns
ns
ns
ns
200
ns
ns
ns
ns
[2]
[3]
ns
ns
ns
ns
[3]
50
170
60
60
50
50
40
50
ns
ns
ns
ns
ns
ns
[12]
5
5
30
ns
ns
ns
ns
[6]
[6,7,13]
30
30
ns
ns
ns
ns
[6]
[6]
[6,7,13]
[6]
ns
ns
ns
ns
[6,8]
[6]
[6,9,13]
[6]
ns
ns
ns
ns
[6]
[6]
[6]
[6,8]
ns
ns
ns
ns
[6]
[6,9]
[6]
[6]
ns
ns
ns
ns
[6]
[1,6]
[6]
[6]
25
25
35
50
60
25
25
30
30
75
30
30
25
30
75
30
30
0
TdCLKf(DS)
0
Note
30
35
[12]
PS97USC0200
P R E L I M I N A R Y
ZILOG
No
Symbol
Parameter
147
148
149
150
TdCLK(ADz)
TdCLK(ADa)
TsAD(UAS)
ThAD(UAS)
CLK Rise to Address Float Delay
CLK Rise to Address Active Delay
Address to /UAS Rise Setup Time
Address to /UAS Rise Hold Time
151
152
153
154
TsAD(AS)
ThAD(AS)
TsW(CLK)
ThW(CLK)
155
156
157
158
Z16C32 IUSC™
Max
Units
Note
35
35
10
10
ns
ns
ns
ns
[6]
[6]
[6]
[6]
Address to /AS Rise Setup Time
Address to /AS Rise Hold Time
/WAIT to CLK Fall Setup Time
/WAIT to CLK Fall Hold Time
10
10
10
15
ns
ns
ns
ns
[6]
[6]
[6]
[6]
TsRDY(CLK)
ThRDY(CLK)
ThDW(CLK)
TdAS(DSw)
/READY to CLK Fall Setup Time
/READY to CLK Fall Hold Time
Write Data to CLK Rise Hold Time
/AS Rise to /DS Fall (Write) Delay
10
15
0
40
ns
ns
ns
ns
[6]
[6]
[6]
[6,10,13]
159
160
161
162
TsDW(DS)
TwDSlw
ThDW(DS)
TdAS(WR)
Write Data to /DS Fall Setup Time
/DS (Write) Low Width
Write Data to /DS Rise Hold Time
/AS Rise to /WR Fall Delay
25
45
25
40
ns
ns
ns
ns
[6,7,13]
[6,11,13]
[6,8]
[6,10,13]
163
164
165
166
TsDW(WR)
TwWRl
ThDW(WR)
TdCLK(WR)
Write Data to /WR Fall Setup Time
/WR Low Width
Write Data to /WR Rise Hold Time
CLK Fall to /WR Delay
25
45
25
ns
ns
ns
ns
[6,7,13]
[6,11,13]
[6,8]
[6]
167
168
169
170
TdCLK(BUSz)
TsABT(CLK)
ThABT(CLK)
TdCLK(BRQ)
CLK Rise to Bus Float Delay
/ABORT to CLK Rise Setup Time
/ABORT to CLK Rise Hold Time
CLK Rise to /BUSREQ Delay
20
15
ns
ns
ns
ns
[6]
[6]
[6]
[6]
171
172
173
174
175
176
TdCLK(BUSa)
TsBIN(CLK)
ThBIN(CLK)
TsBRQ(CLK)
ThBRQ(CLK)
TdBIN(BOT)
CLK Rise to Bus Active Delay
/BIN to CLK Rise Setup Time
/BIN to CLK Rise Hold Time
/BUSREQ to CLK Rise Setup Time
/BUSREQ to CLK Rise Hold Time
/BIN to /BOUT Delay
20
15
25
0
ns
ns
ns
ns
ns
ns
[6]
[6]
[6]
[6]
[6]
Notes:
AC Test Conditions:
VCC = 5V ± 5% unless otherwise specified,
over specified temperature range.
VIH = 2.0V VOH = 2.0V
VIL = 0.8V VOL = 0.8V
Float = +0.5V
[1]
[2]
[3]
[4]
[5]
[6]
Direct Address is any of S//D, D//C or AD15-AD8 used
as an address bus.
The parameter applies only when /AS is not present.
Strobe is any of /DS, /RD, /WR or Pulsed /INTACK.
Parameter applies only if read empties the receive FIFO.
Parameter applies only if write fills the transmit FIFO.
Parameter applies only while the IUSC is bus master.
PS97USC0200
Min
[7]
[8]
[9]
[10]
[11]
[12]
[13]
30
30
30
30
60
Parameter is clock-cycle dependent, TwCLKh + TfCLK – 5.
Parameter is clock-cycle dependent, TwCLKl + TrCLK –5
Parameter is clock-cycle dependent,
TcCLK + TwCLKh + TfCLK –5.
Parameter is clock-cycle dependent, TcCLK –10.
Parameter is clock-cycle dependent, TcCLK –5.
Clock cycle parameters TwCLKh and TcCLK have unique
values for Linked List Mode. In Linked List Mode, the system clock
cycle is extended to 60 ns, and the system clock High pulse width
is extended to 35 ns. This is due to the internal timing paths unique
to the Linked List Mode. The transmit and receive bit rates are not
affected.
For Linked List Mode, the minimum for these values should be
calculated using TwCLKh = 35 ns and TcCLK = 60 ns.
115
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
General Timing Diagram
/RxC, /TxC
Receive
1
3
2
4
RxD
5
6
/DCD as
/SYNC
External
/TxC, /RxC
Transmit
7
8
TxD
9
10
/RxC
11
/TxC
12
13
14
/CTS,
/DCD
15
15
16
16
/DCD as
/SYNC
Input
Figure 105. General Timing
116
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
General Timing Table
No
Symbol
Parameter
Min
1
2
3
4
TsRxD(RxCr)
ThRxD(RxCr)
TsRxd(RxCf)
ThRxD(RxCf)
RxD to /RxC Rise Setup Time (x1 Mode)
RxD to /RxC Rise Hold Time (x1 Mode)
RxD to /RxC Fall Setup Time (x1 Mode)
RxD to /RxC Fall Hold Time (x1 Mode)
5
6
7
8
TsSy(RxC)
ThSy(RxC)
TdTxCf(TxD)
TdTxCr(TxD)
9
10
11
12
13
14
15
16
Units
Note
0
20
0
20
ns
ns
ns
ns
[1]
[1]
[1,3]
[1,3]
/DCD as /SYNC to /RxC Rise Setup Time
/DCD as /SYNC to /RxC Rise Hold Time (x1 Mode)
/TxC Fall to TxD Delay
/TxC Rise to TxD Delay
0
20
ns
ns
ns
ns
[1]
[1]
[2]
[2,3]
TwRxCh
TwRxCl
TcRxC
TwTxCh
/RxC High Width
/RxC Low Width
/RxC Cycle Time
/TxC High Width
20
20
50
20
ns
ns
ns
ns
TwTxCl
TcTxC
TwExT
TWSY
/TxC Low Width
/TxC Cycle Time
/DCD or /CTS Pulse Width
/DCD as /SYNC Input Pulse Width
20
50
35
35
ns
ns
ns
ns
PS97USC0200
Max
25
25
117
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
System Timing Diagram
/RxC, /TxC
Receive
/RxREQ
Request
1
/RxC as
Receiver
Output
2
/INT
3
/RxC, /TxC
Transmit
/TxREQ
4
/TxC as
Transmitter
Output
5
/INT
6
/CTS, /DCD,
/TxREQ,
/RxREQ
/INT
7
Figure 106. Z16C32 System Timing
118
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
AC CHARACTERISTICS
System Timing Table
No
Symbol
Parameter
1
2
3
4
TdRxC(REQ)
TdRxC(RxC)
TdRxC(INT)
TdTxC(REQ)
5
6
7
TdTxC(TxC)
TdTxC(INT)
TdEXT(INT)
Min
Max
Units
Note
/RxC Rise to /RxREQ Valid Delay
/TxC Rise to /RxC as Receiver Output Valid Delay
/RxC Rise to /INT Valid Delay
/TxC Fall to /TxREQ Valid Delay
50
50
50
50
ns
ns
ns
ns
[2]
[2]
[2]
[2]
/RxC Fall to /TxC as transmitter Output Valid Delay
/TxC Fall to /INT Valid Delay
/CTS, /DCD, /TxREQ, /RxREQ transition
to /INT Valid Delay
50
50
ns
ns
[2]
50
ns
Notes:
[1] /RxC is /RxC or /TxC, whichever is supplying the receive clock.
[2] /TxC is /TxC or /RxC, whichever is supplying the transmit clock.
[3] Parameter applies only to FM encoding/decoding.
PS97USC0200
119
ZILOG
P R E L I M I N A R Y
Z16C32 IUSC™
PACKAGE INFORMATION
68-Pin PLCC Package Diagram
120
PS97USC0200
P R E L I M I N A R Y
ZILOG
Z16C32 IUSC™
ORDERING INFORMATION
Z16C32 IUSC
20 MHz
68-Pin PLCC
Z16C3220VSC
For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
Package
V = Plastic Chip Carrier
Temperature
S = 0°C to 70°C
Speed
20 = 20 MHz
Environmental
C = Plastic Standard
Example:
Z 16C32 20 V S C
is a Z16C32, 20 MHz, PLCC, 0°C to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
© 1997 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
PS97USC0200
Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
121