HM5118165 Series 16 M EDO DRAM (1-Mword × 16-bit) 1 k Refresh ADE-203-636D (Z) Rev. 4.0 Nov. 1997 Description The Hitachi HM5118165 is a CMOS dynamic RAM organized as 1,048,576-word × 16-bit. It employs the most advanced 0.5 µm CMOS technology for high performance and low power. The HM5118165 offers Extended Data Out (EDO) Page Mode as a high speed access mode. It is packaged in 42-pin plastic SOJ and 50-pin plastic TSOP II. Features • Single 5 V (±10%) • Access time : 50 ns/60 ns/70 ns (max) • Power dissipation Active mode : 1045 mW/935 mW/825 mW (max) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) • EDO page mode capability • Refresh cycles 1024 refresh cycles : 16 ms : 128 ms (L-version) • 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) • 2CAS-byte control • Battery backup operation (L-version) HM5118165 Series Ordering Information Type No. Access time Package HM5118165J-5 HM5118165J-6 HM5118165J-7 50 ns 60 ns 70 ns 400-mil 42-pin plastic SOJ (CP-42D) HM5118165LJ-5 HM5118165LJ-6 HM5118165LJ-7 50 ns 60 ns 70 ns HM5118165TT-5 HM5118165TT-6 HM5118165TT-7 50 ns 60 ns 70 ns HM5118165LTT-5 HM5118165LTT-6 HM5118165LTT-7 50 ns 60 ns 70 ns 2 400-mil 50-pin plastic TSOP II (TTP-50/44DC) HM5118165 Series Pin Arrangement HM5118165J/LJ Series HM5118165TT/LTT Series VCC 1 42 VSS I/O0 2 41 I/O15 I/O1 3 40 I/O14 I/O2 4 39 I/O13 I/O3 5 38 I/O12 VCC 6 37 VSS I/O4 7 36 I/O11 I/O5 8 35 I/O10 I/O6 9 34 I/O9 I/O7 10 33 I/O8 NC 11 32 NC NC 12 31 LCAS WE 13 30 UCAS RAS 14 29 OE NC 15 28 A9 NC 16 27 A8 A0 17 26 A7 A1 18 25 A6 A2 19 24 A5 A3 20 23 A4 21 22 VSS VCC (Top view) VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 V SS I/O15 I/O14 I/O13 I/O12 V SS I/O11 I/O10 I/O9 I/O8 NC NC NC WE RAS NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS (Top view) Pin Description Pin name Function A0 to A9 Address input — Row/Refresh address A0 to A9 — Column address A0 to A9 I/O0 to I/O15 Data input/Data output RAS Row address strobe UCAS, LCAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground NC No connection 3 HM5118165 Series Block Diagram RAS UCAS LCAS WE OE Timing and control A0 Column decoder A1 to Column • • • address buffers • • • Row address buffers 4 Row decoder A9 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array 1M array I/O buffers I/O0 to I/O15 HM5118165 Series Truth Table RAS LCAS UCAS WE OE Output Operation H D D D D Open Standby L L H H L Valid Lower byte Read cycle L H L H L Valid Upper byte L L L H L Valid Word L L L L L L H L L H H L L H L L *2 D Open Lower byte Early write cycle L* 2 D Open Upper byte L* 2 D Open Word L* 2 H Undefined Lower byte Delayed write cycle L* 2 H Undefined Upper byte 2 H Undefined Word L L L L* L L H H to L L to H Valid Lower byte Read-modify-write cycle L H L H to L L to H Valid Upper byte L L L H to L L to H Valid Word L H H D D Open Word RAS-only refresh cycle H to L H L D D Open Word CAS-before-RAS refresh cycle or H to L L H D D Open Word Self refresh cycle (L-version) H to L L L D D Open Word L L L H H Open Read cycle (Output disabled) Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS ≥ 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output High-Z control are done independently by each UCAS, LCAS. ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. 5 HM5118165 Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Notes Supply voltage VCC 4.5 5.0 5.5 V 1, 2 Input high voltage VIH 2.4 — 6.5 V 1 Input low voltage VIL –1.0 — 0.8 V 1 Notes: 1. All voltage referred to VSS 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM5118165 -5 Parameter 1, Operating current* * Standby current Standby current (L-version) 6 2 -6 -7 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 — 200 — 170 — 150 mA t RC = min I CC2 — 2 — 2 — 2 mA TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface RAS, UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z — 150 — 150 µA CMOS interface RAS, UCAS, LCAS ≥ VCC – 0.2 V Dout = High-Z I CC2 150 — HM5118165 Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont.) HM5118165 -5 Parameter -6 -7 Symbol Min Max Min Max Min Max Unit Test conditions I CC3 — 200 — 170 — 150 mA t RC = min Standby current* I CC5 — 5 5 5 RAS = VIH, UCAS, LCAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 190 — 170 — 150 mA t RC = min EDO page mode current*1, * 3 I CC7 — 185 — 165 — 145 mA t HPC = min RAS-only refresh current* 2 1 — — mA Battery backup current* (Standby with CBR refresh) (L-version) I CC10 — 500 — 500 — 500 µA CMOS interface Dout = High-Z CBR refresh: tRC = 125 µs t RAS ≤ 0.3 µs Self refresh mode current (L-version) I CC11 — 300 — 300 — 300 µA CMOS interface RAS, UCAS, LCAS ≤ 0.2 V Dout = High-Z Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 7 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 7 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0.4 0.4 V Low Iout = 2 mA 4 0 0 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while UCAS and LCAS = VIH. 4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V. Capacitance (Ta = 25°C, VCC = 5 V ± 10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 7 pF 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, UCAS and LCAS = VIH to disable Dout. 7 HM5118165 Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *2, *18, *19, *20 Test Conditions • • • • • Input rise and fall time: 2 ns Input levels: 0 V, 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5118165 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Random read or write cycle time t RC 84 — 104 — 124 — ns RAS precharge time t RP 30 — 40 — 50 — ns CAS precharge time t CP 7 — 10 — 13 — ns RAS pulse width t RAS 50 10000 60 10000 70 10000 ns CAS pulse width t CAS 7 10000 10 10000 13 10000 ns Row address setup time t ASR 0 — 0 — 0 — ns Row address hold time t RAH 7 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns 21 Column address hold time t CAH 7 — 10 — 13 — ns 21 RAS to CAS delay time t RCD 11 37 14 45 14 52 ns 3 RAS to column address delay time t RAD 9 25 12 30 12 35 ns 4 RAS hold time t RSH 10 — 13 — 13 — ns CAS hold time t CSH 35 — 40 — 45 — ns 23 CAS to RAS precharge time t CRP 5 — 5 — 5 — ns 22 OE to Din delay time t OED 13 — 15 — 18 — ns 5 OE delay time from Din t DZO 0 — 0 — 0 — ns 6 CAS delay time from Din t DZC 0 — 0 — 0 — ns 6 Transition time (rise and fall) tT 2 50 2 50 2 50 ns 7 8 Notes HM5118165 Series Read Cycle HM5118165 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC — 50 — 60 — 70 ns 8, 9 Access time from CAS t CAC — 13 — 15 — 18 ns 9, 10, 17 Access time from address t AA — 25 — 30 — 35 ns 9, 11, 17 Access time from OE t OEA — 13 — 15 — 18 ns 9 Read command setup time t RCS 0 — 0 — 0 — ns 21 Read command hold time to CAS t RCH 0 — 0 — 0 — ns 12, 22 Read command hold time from RAS t RCHR 50 — 60 — 70 — ns Read command hold time to RAS t RRH 0 — 0 — 0 — ns Column address to RAS lead time t RAL 25 — 30 — 35 — ns Column address to CAS lead time t CAL 15 — 18 — 23 — ns CAS to output in low-Z t CLZ 0 — 0 — 0 — ns Output data hold time t OH 3 — 3 — 3 — ns Output data hold time from OE t OHO 3 — 3 — 3 — ns Output buffer turn-off time t OFF — 13 — 15 — 15 ns 13, 27 Output buffer turn-off to OE t OEZ — 13 — 15 — 15 ns 13 CAS to Din delay time t CDD 13 — 15 — 18 — ns 5 Output data hold time from RAS t OHR 3 — 3 — 3 — ns 27 Output buffer turn-off to RAS t OFR — 13 — 15 — 15 ns 27 Output buffer turn-off to WE t WEZ — 13 — 15 — 15 ns WE to Din delay time t WED 13 — 15 — 18 — ns RAS to Din delay time t RDD 13 — 15 — 18 — ns RAS next CAS delay time t RNCD 50 — 60 — 70 — ns 12 27 9 HM5118165 Series Write Cycle HM5118165 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns 14, 21 Write command hold time t WCH 7 — 10 — 13 — ns 21 Write command pulse width t WP 7 — 10 — 10 — ns Write command to RAS lead time t RWL 7 — 10 — 13 — ns Write command to CAS lead time t CWL 7 — 10 — 13 — ns 23 Data-in setup time t DS 0 — 0 — 0 — ns 15, 23 Data-in hold time t DH 7 — 10 — 13 — ns 15, 23 Notes Read-Modify-Write Cycle -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Read-modify-write cycle time t RWC 111 — 135 — 161 — ns RAS to WE delay time t RWD 67 — 79 — 92 — ns 14 CAS to WE delay time t CWD 30 — 34 — 40 — ns 14 Column address to WE delay time t AWD 42 — 49 — 57 — ns 14 OE hold time from WE t OEH 13 — 15 — 18 — ns Refresh Cycle HM5118165 -5 Parameter -7 Min Max Min Max Min Max Unit Notes CAS setup time (CBR refresh cycle) t CSR 5 — 5 — 5 — ns 21 CAS hold time (CBR refresh cycle) t CHR 7 — 10 — 10 — ns 22 RAS precharge to CAS hold time 5 — 5 — 5 — ns 21 10 Symbol -6 t RPC HM5118165 Series EDO Page Mode Cycle HM5118165 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes EDO page mode cycle time t HPC 20 — 25 30 ns 25 EDO page mode RAS pulse width t RASP — 100000 — 100000 — 100000 ns 16 Access time from CAS precharge t CPA — 28 — 35 — 40 ns 9, 17, 22 RAS hold time from CAS precharge t CPRH 28 — 35 — 40 — ns Output data hold time from CAS low t DOH 3 — 3 — 3 — ns CAS hold time referred OE t COL 7 — 10 — 13 — ns CAS to OE setup time t COP 5 — 5 — 5 — ns Read command hold time from CAS precharge t RCHC 28 — 35 — 40 — ns — — 9 EDO Page Mode Read-Modify-Write Cycle HM5118165 -5 Parameter Symbol -6 -7 Min Max Min Max Min Max Unit EDO page mode read-modify-write t HPRWC cycle time 57 — 68 — 79 — ns WE delay time from CAS precharge t CPW 45 — 54 — 62 — ns Notes 14, 22 Refresh Parameter Symbol Max Unit Note Refresh period t REF 16 ms 1024 cycles Refresh period (L-version) t REF 128 ms 1024 cycles 11 HM5118165 Series Self Refresh Mode (L-version) HM5118165L -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes RAS pulse width (self refresh) t RASS 100 — 100 — 100 — µs 28, 29, 30, 31 RAS precharge time (self refresh) t RPS 90 — 110 — 130 — ns CAS hold time (self refresh) t CHS –50 — –50 — –50 — ns Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD ≥ tRAD (max) + tAA (max) – tCAC (max), then access time is controlled exclusively by t CAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 12 HM5118165 Series 20 All the V CC and VSS pins shall be supplied with the same voltages. 21. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 22. t CRP , t CHR, t RCH, t CPA and tCPW are determined by the later rising edge of UCAS or LCAS. 23. t CWL, t DH, t DS and t CSH should be satisfied by both UCAS and LCAS. 24. t CP is determined by the time that both UCAS and LCAS are high. 25. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 26. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH, and between tOFR and t OFF. 28. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS ≥ 100 µs, then RAS precharge time should use tRPS instead of tRP. 29. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 30. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 16 ms immediately after exiting from and before entering into the self refresh mode. 31. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 32. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 13 HM5118165 Series Notes concerning 2CAS control Please do not separate the UCAS/LCAS operation timing intentionally. However skew between UCAS/LCAS are allowed under the following conditions. 1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following. RAS Delayed write UCAS Early write LCAS WE 3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is satisfied, EDO page mode can be performed. RAS UCAS LCAS t UL 4. Byte control operation by remaining UCAS or LCAS high is guaranteed. 14 HM5118165 Series Timing Waveforms*32 Read Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT UCAS LCAS t RAD t ASR Address t RAH t RAL t ASC t CAL t CAH Column Row t RRH t RCHR t RCH t RCS WE t WED t DZC t CDD t RDD High-Z Din t DZO t OEA t OED OE t OEZ t OHO t OFF t CAC t AA t OH t OFR t OHR t RAC t CLZ t WEZ Dout Dout 15 HM5118165 Series Early Write Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT UCAS LCAS tASR Address tRAH Row tASC tCAH Column tWCS tWCH WE tDS Din Dout tDH Din High-Z* * t WCS 16 t WCS (min) HM5118165 Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT UCAS LCAS t ASR Address t RAH t ASC Row t CAH Column t CWL t RWL t WP t RCS WE t DZC Din t DS High-Z t DH Din t OEH t DZO t OED OE t OEZ t CLZ High-Z Dout Invalid Dout 17 HM5118165 Series Read-Modify-Write Cycle*18 t RWC t RAS t RP RAS tT t RCD t CAS t CRP UCAS LCAS t RAD t ASR Address t RAH t ASC Row t CAH Column t RCS t CWD tCWL t AWD t RWL t RWD t WP WE t DZC t DH t DS High-Z Din Din t OED t DZO t OEH t OEA OE t CAC t OEZ t AA t RAC t OHO Dout Dout t CLZ 18 High-Z HM5118165 Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP t RPC t CRP UCAS LCAS t ASR Address t RAH Row t OFR t OFF High-Z Dout 19 HM5118165 Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RC t RP t RAS t RP RAS tT t RPC t CP t CSR t CHR t RPC t CP t CRP t CSR t CHR UCAS LCAS Address t OFR t OFF Dout 20 High-Z HM5118165 Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP RAS tT t RSH t CHR t CRP t RCD UCAS LCAS t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t RRH t RCH t RCS WE t WED t DZC t CDD t RDD High-Z Din t DZO t OED t OEA OE t CAC t AA t RAC t OFF t OH t CLZ Dout t OEZ t WEZ t OHO Dout t OFR t OHR 21 HM5118165 Series EDO Page Mode Read Cycle t RP t RNCD t HPC t RASP RAS tT t CSH t CP t HPC t CAS UCAS LCAS t HPC t CPRH t CP t t CRP RSH t CAS t RCHR t RCS t CP tCAS tCAS t RCHC t RCH t RCS t RRH t RCH WE tASR Address tRAH tASC Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CAL t RAL t CAH tASC t WED Column 4 t CAL t CAL tRDD tCDD tDZC High-Z Din tCOL tDZO tCOP tOED OE tAA tCAC tCAC tAA tWEZ tCPA tAA tCAC tOEZ tOHO tDOH Dout 2 Dout 2 tOHO Dout 3 tCAC tOHO tOFF tOH tOEA Dout 4 Dout 1 tAA tOEZ tOEA tRAC Dout tOFR tOHR tOEZ tCPA tCPA tOEA 22 HM5118165 Series EDO Page Mode Read Cycle (2CAS) t RP t RNCD t RASP RAS tT t CSH t HPC t CP t CAS LCAS tHPC t CP t HPC t CP t CRP tRSH t CAS tCAS UCAS t CAS t RCHC t RRH t RCH t RCS WE tASR Address tRAH tASC Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CAL t RAL t CAH tASC t WED Column 4 t CAL tRDD t CAL tDZC tCDD High-Z Din tCOL tCOP tOED tDZO OE tOEA tAA tCAC tCAC tAA tOEZ tAA tOEZ tOHO tDOH tRAC L Dout tCPA tCPA tOEA tOHO Dout 1 Dout 2 Dout 2 tCPA tAA tCAC U Dout tCAC Dout 1 tOFR tOHR tOEZ tOHO tOFF tOH Dout 4 tOEA Dout 3 Dout 4 23 HM5118165 Series EDO Page Mode Early Write Cycle tRP tRASP RAS tT tCSH tHPC tCAS tRCD tCP tRSH tCAS tCP tCAS tCRP UCAS LCAS tASR Address Row tRAH tASC tCAH Column 1 tWCS tWCH tASC tCAH Column 2 tWCS tWCH tASC tCAH Column N tWCS tWCH WE tDS Din Dout tDH Din 1 tDS tDH Din 2 tDS tDH Din N High-Z* * t WCS 24 t WCS (min) HM5118165 Series EDO Page Mode Delayed Write Cycle*18 t RASP t RP RAS tT t CP t CSH t RCD t CRP t CP t HPC t CAS t CAS t RSH t CAS UCAS LCAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL Column N t CWL t CWL t RWL t RCS t RCS t RCS WE t WP t WP t WP t DZC t DS t DZC t DS t DZC t DS t DH t DH Din 1 Din Din 2 t DZO Din N t DZO t DZO t DH t OED t OED t OED t OEH t OEH t OEH OE t CLZ t CLZ t OEZ t CLZ t OEZ t OEZ High-Z Dout Invalid Dout Invalid Dout Invalid Dout 25 HM5118165 Series EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t HPRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS UCAS LCAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 t ASC t CAH Column 2 t RWD t CWL Column N t CPW t AWD t CWL t CPW t AWD t CWD t RCS t CWL t AWD t CWD t RCS t RWL t CWD WE t RCS t WP t WP t DZC t DS t WP t DZC t DS t DZC t DS t DH t DH Din 1 Din t DZO t OED t DH Din 2 t OED t DZO t OED t DZO t OEH t OEH t OEH Din N OE t OHO t OEA t CAC t OHO t OEA t CAC t AA t AA t CPA t RAC t OEZ t CLZ t OHO t OEA t CAC t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 26 Dout 2 Dout N HM5118165 Series EDO Page Mode Mix Cycle (1) t RP t RASP RAS tT t CAS UCAS LCAS t CRP t CP t CP t CP t CAS tCAS tCAS t CSH tRSH t RCD t WCS t WCH tCPW tAWD WE t ASC tRAH tASR Address Row tCAH Column 1 t RRH t RCH t RCS t RCS t ASC t CAH tASC t CAH Column 2 Column 3 tWP tASC t RAL t CAH Column 4 t CAL t DS Din Din 1 tRDD tCDD t CAL t DH t DH t DS High-Z Din 3 tOED tWED OE tCPA tAA tCAC Dout tOFR tWEZ tCPA tCPA tAA tOEA t DOH Dout 2 t OEZ tCAC t OHO Dout 3 tAA tOEZ tCAC tOHO tOEA tOFF tOH Dout 4 27 HM5118165 Series EDO Page Mode Mix Cycle (2) t RP t RNCD t RASP RAS tT t CSH t CAS UCAS LCAS t RCD t CAS tCAS t RCH tWCS t WCH tRAH Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t RRH t RCH tWP tCPW t ASC tRSH t RCS t RCS WE Address tCAS t RCHR t RCS tASR t CRP t CP t CP t CP t RAL t CAH tASC Column 4 t CAL t CAL t DS t DS High-Z Din t DH Din 2 Din 3 tOED tOED tCOP t OEA tAA tOEA tCAC tOEZ tCPA tAA tOEZ t OHO t OHO Dout 1 tOFR tWEZ tCPA tCAC tRAC 28 tWED tCOL OE Dout tRDD tCDD t DH Dout 3 tAA tCAC tOEZ tOEA tOFF tOH tOHO Dout 4 HM5118165 Series Self Refresh Cycle (L-version)* 28, 29, 30, 31 t RASS t RP t RPS RAS tT t RPC t CP t CRP t CSR t CHS UCAS LCAS t OFR t OFF Dout High-Z 29 HM5118165 Series Package Dimensions HM5118165J/LJ Series (CP-42D) Unit: mm 27.06 27.43 Max 0.43 ± 0.10 0.41 ± 0.08 1.27 0.10 Dimension including the plating thickness Base material dimension 30 2.50 ± 0.12 1.30 Max 0.80 +0.25 –0.17 10.16 ± 0.13 21 0.74 3.50 ± 0.26 1 11.18 ± 0.13 22 42 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-42D Conforms — 1.75 g HM5118165 Series HM5118165TT/LTT Series (TTP-50/44DC) Unit: mm 26 10.16 50 20.95 21.35 Max 40 36 11 15 0.80 25 0.80 0.27 ± 0.07 0.13 M 0.25 ± 0.05 1.15 Max 11.76 ± 0.20 0.10 Dimension including the plating thickness Base material dimension 0.13 ± 0.05 3.20 0.145 ± 0.05 0.125 ± 0.04 1.20 Max 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) 0.68 1 TTP-50/44DC Conforms — 0.50 g 31 HM5118165 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 32 HM5118165 Series Revision Record Rev. Date Contents of Modification 1.0 Sep. 30, 1996 Initial issue Y. Kasama M. Mishima Addition of HM5118165-5 Series Y. Kasama M. Mishima Y. Kasama Y. Matsuno 2.0 Nov. 26, 1996 Drawn by Approved by Power dissipation (active) 1018/907 mW(max) to 1045/935/825 mW (max) DC Characteristics I CC7 max: 185/165 mA to 185/165/145 mA AC Characteristics t RCD min: t RAD min: t RSH min: t RRH min: t RWC min: t RPC min: 20/20 ns to 11/14/14 ns 15/15 ns to 9/12/12 ns 15/18 ns to 10/13/13 ns 0/0 ns to 5/5/5 ns 136/161 ns to 111/135/161 ns 0/0 ns to 5/5/5 ns Timing Waveforms Addition of t RNCD timing to EDO page mode mix cycle (2) 3.0 Feb. 24, 1997 AC Characteristics t RRH min: 5/5/5 ns to 0/0/0 ns 4.0 Nov. 1997 Change of Subtitle 33