A1PROS EI16C550

Ei16C550
FIFO UART
Semiconductor, Inc.
FEATURES
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Tri-StateÆTTL drive capabilities for bidirectional data bus and control bus
Full duplex asynchronous receiver and transmitter
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Line break generation and detection
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Easily interfaces to most popular microprocessors
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Internal diagnostic capabilities:
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Adds or deletes standard asynchronous
communication bits (start, stop, and parity) to or
from a serial data stream
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5V Operation
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Independently controlled transmitter, receiver,
line status, and data set interrupts
Programmable baud rate generator allows
division of any input clock by 1 to (216-1) and
generates the internal 16 x clock
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Independent receiver clock input
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MODEM control functions (CTS, RTS, DSR,
DTR, RI,and DCD)
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- Break, parity overrun, and framing error simulation
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Fully prioritized interrupt systems controls
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16 byte FIFO for reduced CPU overhead
DESCRIPTION
The Epic Ei16C550 Universal Asynchronous Receiver
Transmitter (UART) is a CMOS-VLSI communication
device in a single package.
Fully programmable serial interface
characteristics:
- 5, 6, 7, or 8 bit characters
- Even, odd, or no-parity bit generation and
detection
- 1, 1.5, or 2 stop bit generation
- Baud generation (DC to 56k baud)
False start bit detection
Complete status reporting capabilities
- Loopback controls for communications link fault
isolation
The UART performs serial to parallel conversion on
data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversions on data characters received from the CPU. The CPU can read the complete
status of the UART at any time during the functional operation.
Status information reported includes the type and condition of
the transfer operation being performed by the UART, as well
as any error conditions (party, overrun, framing, or break
detect).
Part Numbers May Be Marked With "IMP" or "Ei."
40-PIN DIP
44-PIN PLCC
N.C.
D4
D3
D2
D1
D0
VCC
RI ï
CD ï
DSR ï
CTS ï
N.C.
48
47
46
45
44
43
42
41
40
39
38
37
N.C.
1
36
N.C.
D5
2
35
RESET
D6
3
34
OP1 ï
D7
4
33
DTR ï
RCLK
5
32
RTS ï
N.C.
6
31
OP2 ï
RX
7
30
INT
TX
8
29
RXRDY ï
CS0
9
28
A0
Ei16C550
19
20
21
22
23
24
IOR
N.C.
DDIS ï
TXRDY ï
AS
N.C.
IOR ï
25
18
12
GND
A2
BAUDOUT ï
17
A1
26
IOW
27
11
16
10
-IOW
CS1
CS2 ï
15
MR
OUT1ï
DTRï
RTSï
OUT2ï
NC
INTRPT
RXRDYï
A0
A1
A2
XTAL2
Ei16C550
39
38
37
36
35
34
33
32
31
30
29
14
7
8
9
10
11
12
13
14
15
16
17
13
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2ï
BAUDOUTï
N.C.
6
5
4
3
2
1
44
43
42
41
40
VCC
RIï
DCDï
DSRï
CTSï
MR
OUT1ï
DTRï
RTSï
OUT2ï
INTRPT
RXRDYï
A0
A1
A2
ADSï
TXRDYï
DDIS
DISTR
DISTRï
XTAL1
E
i
1
6
C
5
5
0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
XTAL1
XTAL2
DOSTRï
DOSTR
VSS
NC
DISTRï
DISTR
DDIS
TXRDYï
ADSï
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2ï
BAUDOUTï
XTAL1
XTAL2
DOSTRï
VSS
D4
D3
D2
D1
D0
NC
VCC
RIï
DCDï
DSRï
CTSï
PIN CONFIGURATION
48-PIN TQFP
7
For additional information, contact IMP, Inc. at 408.432.9100 or visit www.impweb.com
IMP, Inc. acquired Epic products on January 26, 2001. (see press release at http://www.impweb.com/PRESS/PR012601.htm)
Ei16C550
FIFO UART
Semiconductor, Inc.
The UART includes a programmable baud generator
which is capable of dividing the timing reference clock
input by divisors of 1 to (216-1), and producing a 16 x
clock to drive the receiver logic. Also included in the
UART is a complete MODEM control capability, and
processor interrupt system that may be software tailored to the users requirement to minimize the computing needed to handle the communications link.
BLOCK DIAGRAM
INTERNAL
DATA BUS
D7-D0
A0
A1
A2
CS0
CS1
CS2•
ADR
MR
DISTR
DISTR•
DOSTR
DOSTR•
DDIS
TXRDY•
XTAL1
XTAL2
RXRDY•
DATA
BUS
BUFFER
(1-8)
(28)
(27)
(26)
(12)
(13)
(14)
(25)
(35)
(22)
(21)
(19)
(18)
(23)
(24)
(16)
(17)
(29)
RECEIVER
BUFFER
REGISTER
LINE
CONTROL
REGISTER
DIVISOR
LATCH
(LS)
DIVISOR
LATCH
(MS
SELECT
AND
CONTROL
LOGIC
BAUD
GENERATOR
RECEIVER
SHIFT
REGISTER
(10)
RECEIVER
TIMING
&
CONTROL
(9)
(15)
SUPPLY
(40)
(20)
TRANSMITTER
TIMING
&
CONTROL
LINE
STATUS
REGISTER
FIFO
TRANSMITTER
SHIFT
REGISTER
MODEM
CONTROL
REGISTER
3.3, 5V
GND
INTERRUPT
ENABLE
REGISTER
INTERRUPT
ID
REGISTER
FIFO
CONTROL
REGISTER
8
RCLK
BAUDOUT
(11)
MODEM
STATUS
REGISTER
POWER
SIN
INTERRUPT
CONTROL
LOGIC
MODEM
CONTROL
LOGIC
(30)
SOUT
(32)
RTS•
(36)
CTS•
(33)
DTR•
(37)
DSR•
(38)
(39)
DCD•
•
RI
(34)
OUT1•
(31)
OUT2•
INTRPT