IMP52251 DATA COMMUNICATIONS 18-Line Plug and Play SCSI Terminator Key Features The IMP5225 SCSI terminator is part of IMP's family of highperformance SCSI terminators, which are designed to deliver true UltraSCSI performance. The BiCMOS design offers superior performance over first generation linear passive and active techniques. IMP's new architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible — typically 35MHz, which is 100 times faster than the older linear regulator/terminator approach. Products using the older regulator/resistor architecture have bandwidths which are dominated by the reference stabilization output capacitor and are therefore limited to 500kHz (see further discussion in the Functional Description section). The IMP architecture eliminates the output compensation capacitor required in linear regulator/ resistor designs. The IMP5225 architecture tolerates marginal system designs. A key improvement offered by the IMP5225 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as the use of improper cable lengths and impedances. Frequently, this situation is not controlled by the peripheral or host designer. The IMP5225 has two disconnect pins for SCSI Plug and Play (PnP) applications. To enter the disconnect mode, the disconnect pins must be driven LOW thereby disconnecting the IMP5225 from the SCSI bus. Quiescent current is less than 150µA when disabled. Reduced component count is inherent in the IMP5225 architecture. Traditional termination techniques require large stabilization and ◆ SCSI Plug and Play — Dual active LOW disconnect pins ◆ Ultra-Fast response for Fast-20 SCSI ◆ 35MHz channel bandwidth ◆ Sleep-mode current less than 150µA — Disconnects terminator from lows ◆ NO external compensation capacitors ◆ Compatible with active negation drivers ◆ Compatible with passive and active terminations ◆ Approved for use with SCSI 1, 2, 3 and Ultra SCSI ◆ Hot swap compatible ◆ Pin-for-pin compatible with LX5225, LX5205 and UC5607 transient protection capacitors of up to 20µF in value and size. The IMP5225 architecture does not require these components, allowing all the cost savings associated with inventory, board space, assembly, reliability, and component costs. The IMP5225 is a superior pin-for-pin replacement for the LX5225, LX5205, UC5607. Block Diagrams Term Power Current Biasing Circuit VTERM 24mA Current Limiting Circuit DATA OUTPUT PIN DB (0) 2.85V DISCONNECT 1 Enable Logic DISCONNECT 2 – 1 of 18 Channels + 0.4V VTERM © 2000 IMP, Inc. 5225_01.eps 408-432-9100/www.impweb.com 1 IMP5IMP5225 1 1 1/51 1 2 Pin Configuration SOWB-28 DISCONNECT 1 1 28 DISCONNECT 2 T1 2 27 T18 T2 3 26 T17 T3 4 25 T16 T4 5 24 T15 T5 6 HEAT SINK / GND 7 GND 8 21 HEAT SINK / GND HEAT SINK / GND 9 20 HEAT SINK / GND IMP5225 23 T14 22 HEAT SINK / GND T6 10 19 T13 T7 11 18 T12 T8 12 17 T11 T9 13 16 T10 VTERM 14 15 NC 5225_02.eps DWP Package Ordering Information Part Number Temperature Range Package IMP5225CDWP 0°C to 70°C 28-pin Plastic SOWB IMP5225CDWPT 0°C to 70°C Tape and Reel, 28-pin Plastic SOWB 5225_t01.at3 Absolute Maximum Ratings1 TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . +7V Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . 0V to +7V Differential Voltage . . . . . . . . . . . . . . . . . . . . . 0V to 6.5V Operating Junction Temperature Plastic (DWP Package) . . . . . . . . . . . . . . . . 150°C Storage Temperature Range . . . . . . . . . . . . . . –65°C to 150°C Lead Temperature (Soldering, 10 sec.) . . . . . . 300°C Note: 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Thermal Data DWP Package: Thermal Resistance Junction-to-Leads, θJL . . . . . . . . 18°C/W Thermal Resistance Junction-to-Ambient, θJA . . . . . . 40°C/W Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the ambient airflow is assumed. 2 408-432-9100/www.impweb.com © 2000 IMP, Inc. IMP5IMP5225 1 1 1/51 1 2 Recommended Operating Conditions Parameter Termpwr Voltage Symbol Min VTERM 4.0 Typ Max Units 5.5 V Signal Line Voltage 0 5.0 V Disconnect Input Voltage 0 VTERM V Operating Junction Temperature Range – IMP5225C 0 125 °C Note: 5225_t02.eps 2. Recommended operating conditions indicate the range over which the device is functional. Electrical Characteristics Unless otherwise specified, these specifications apply at an ambient operating temperature of TA = 25°C. TermPwr = 4.75V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature. Parameter Output High Voltage TermPwr Supply Current Symbol Conditions VOUT ICC Min Typ 2.65 2.85 IOUT 15 All data lines = 0.2V 424 450 50 150 µA –22 –24 mA –10 µA 1 µA VOUT = 0.5V –20 IIN DISCONNECT Pins = 0V Output Leakage Current IOL DISCONNECT Pins < 0.8V, VO = 0.2V BW Termination Sink Current, per Channel ISINK V 10 Disconnect Input Current Channel Bandwidth Units All data lines = Open DISCONNECT Pins < 0.8V Output Current Max 35 VOUT = 4V 7 mA MHz mA 5225_t03.eps © 2000 IMP, Inc. Data Communications 3 IMP5IMP5225 1 1 1/51 1 2 Application Information Figure 1. Receiving Waveform – 20MHz Figure 2. Driving Waveform – 20MHz Receiver DISCONNECT 1 Driver 1 Meter, AWG 28 IMP5225 DISCONNECT 1 IMP5225 DISCONNECT 2 DISCONNECT 2 5225_03.eps Figure 3. Cable transmission theory suggests to optimize signal speed and quality, the termination should act both as an ideal voltage reference when the line is released (deasserted) and as an ideal current source when the line is active (asserted). Common active terminators which consist of linear regulators in series with resistors (typically 110Ω) are a compromise. With coventional linear terminators as the line voltage increases the amount of current decreases linearly by the equation; (VREF − VLINE) = I. R The IMP5225, with its unique new architecture, applies the maximum amount of current regardless of line voltage until the termination high threshold (2.85V) is reached. Acting as a near ideal line terminator, the IMP5225 closely reproduces the optimum case when the device is enabled. To enable the device the DISC1 and DISC2 pins are pulled HIGH. During this mode of operation, quiescent current is 10mA, and the device will respond to line demands by delivering 24mA on assertion and by imposing 2.85V on deassertion. In order to disable the device, the DISC1 and DISC2 pins must be driven LOW. In the disable mode, the device is in a sleep state with quiescent current less than 150µA. When disabled, all outputs are in a high impedance state. Sleep mode can be used for power conservation or to remove the terminator from the SCSI chain. An additional feature of the IMP5225 is its compatibility with active negation drivers. Table 1. Power Up/ Power Down Function Table DISCONNECT 1 DISCONNECT 2 Outputs Maximum Quiescent Current H H Disabled 15mA H L Enabled 15mA L H Enabled 15mA L L Disabled 150µA Open Open Disabled 150µA 5225_t04.eps 4 408-432-9100/www.impweb.com © 2000 IMP, Inc. IMP5IMP5225 1 1 1/51 1 2 Application Information HOST TERM POWER VTERM ~ ~ VTERM IMP5225 DB (0) DB (1) DB (0) DB (1) ACK RST MSG ACK RST MSG ~ ~ ~ 4.7µF IMP5225 5V 4.7µF DISCONNECT TERM POWER 5V DISCONNECT PERIPHERAL SCSI CABLE 5225_04.eps Figure 4. Application Schematic © 2000 IMP, Inc. Data Communications 5 IMP5225 1 Package Dimensions SOWB (28-Pin) Inches Min A Millimeters Max Min Max SOWB (28-Pin)* 28 15 1 14 B F P D G M C SEATING PLANE K J 28-Pin (SOWB)DWP.eps IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Fax: 408-432-1085 e-mail: [email protected] http://www.impweb.com The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners. A 0.698 0.713 B 0.291 0.299 C 0.093 0.104 D 0.013 0.018 F 0.016 0.050 G 0.050 BSC J 0.009 0.013 K 0.004 0.012 M 0° 8° P 0.394 0.419 * JEDEC Drawing MO-013AE 17.70 18.10 7.40 7.60 2.35 2.65 0.33 0.51 0.40 1.27 1.27 BSC 0.23 0.32 0.10 0.30 0° 8° 10.00 10.65 5225_t05.at3 © 2000 IMP, Inc. Printed in USA Publication #: 7008 Revision: C Issue Date: 08/19/02 Type: Preliminary