SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 D Members of theTexas Instruments D D D D D D D D D SCOPE Family of Testability Products Compatible With the IEEE Standard 1149.1 (JTAG) Serial Test Bus Allow Partitioning of System Scan Paths Can Be Cascaded Horizontally or Vertically Select One of Four Secondary Scan Paths to Be Included in a Primary Scan Path Provide Communication Between Primary and Remote Test Bus Controllers Include 8-Bit Programmable Binary Counter to Count or Initiate Interrupt Signals Include 8-Bit Identification Bus for Scan Path Identification Inputs Are TTL Compatible EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs DTDI OTMS DCO MCO DTDO DTCK GND DTMS1 DTMS2 DTMS3 DTMS4 DTRST TDO TMS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 DCI MCI ID1 ID2 ID3 ID4 ID5 VCC ID6 ID7 ID8 TRST TDI TCK SN54ACT8999 . . . FK PACKAGE (TOP VIEW) ID2 ID3 ID4 ID5 V CC ID6 ID7 D SN54ACT8999 . . . JT PACKAGE SN74ACT8999 . . . DW OR NT PACKAGE (TOP VIEW) description ID1 MCI DCI DTDI OTMS DCO MCO The ’ACT8999 are members of the Texas Instruments SCOPE testability integratedcircuit family. This family of components facilitates testing of complex circuit-board assemblies. 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 ID8 TRST TDI TCK TMS TDO DTRST DTDO DTCK GND DTMS1 DTMS2 DTMS3 DTMS4 The ’ACT8999 enhance the scan capability of TI’s SCOPE family by allowing augmentation of a system’s primary scan path with secondary scan paths (SSPs), which can be individually selected by the ’ACT8999 for inclusion in the primary scan path. The device also provides buffering of test signals to reduce the need for external logic. 4 5 By loading the proper values into the instruction register and data registers, the user can select one of four secondary scan paths. This has the effect of shortening the scan path to allow maximum test throughput when an individual subsystem (board or box) is to be tested. Any of the device’s six data registers or the instruction register can be placed in the device’s scan path, i.e., placed between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations. All operations of the device except counting are synchronous to the test clock (TCK). The 8-bit programmable up/down counter can be used to count transitions on the device condition input (DCI) and output interrupt signals via the device condition output (DCO). The device can be configured to count on either the rising or falling edge of DCI. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE and EPIC are trademarks of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated !"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(, %$0+*() *$"#$%& ($ )-,*!#!*'(!$") -,% (1, (,%&) $# ,2') ")(%+&,"() )('"0'%0 3'%%'"(4 %$0+*(!$" -%$*,))!"5 0$,) "$( ",*,))'%!/4 !"*/+0, (,)(!"5 $# '// -'%'&,(,%) " -%$0+*() *$&-/!'"( ($ 677 '// -'%'&,(,%) '%, (,)(,0 +"/,)) $(1,%3!), "$(,0 " '// $(1,% -%$0+*() -%$0+*(!$" -%$*,))!"5 0$,) "$( ",*,))'%!/4 !"*/+0, (,)(!"5 $# '// -'%'&,(,%) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 description (continued) If a system’s test architecture contains more than one test bus controller, the 8-bit bidirectional bus can be used to interface a higher-level primary bus controller (PBC) with one or more lower-level remote bus controllers (RBCs). A protocol allows the PBC to pass control of the ’ACT8999 to an RBC, freeing the PBC for other tasks. The 8-bit bus also can be hardwired to provide one of 256 codes for subsystem identification. The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1. The SN54ACT8999 is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74ACT8999 is characterized for operation from 0°C to 70°C. functional block diagram 8 VCC 2 OTMS Remote Test Port VCC DTDI Test Mode Select Circuit 9 10 DTMS1 DTMS2 DTMS3 1 11 DTMS4 VCC TDI 16 5 DCI MCI DTDO 28 3 DCO (3 state or open drain) 4 MCO 27 Data Registers ID1−ID8 13 TDO Instruction Register VCC TMS TCK 14 Primary Test Port 6 15 DTCK VCC TRST 12 17 Pin numbers shown are for the DW, JT, and NT packages. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • DTRST SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 functional block description The ’ACT8999 implements two separate functions in one package. The primary function of the device is to include a selected secondary scan path in the system’s primary scan path to enable a PBC to perform controlling and observing test functions on the selected path. This is accomplished by driving the TMS terminal(s) of a secondary scan path with one of the DTMS pins of the device. This approach allows a system to have built-in testability at all levels without requiring that the primary-system scan path always include all subsystem scan paths. As a result, test throughput is improved and the amount of test data that must be interpreted is reduced. The device includes error-detection circuitry that prevents the user from inadvertently activating more than one secondary scan path at a time. Another function of the device is provided by the 8-bit identification bus. This bus can be hardwired with pullup and pulldown resistors to supply an identification code to the test controller(s) to verify that test operations are being performed on the proper portion of the system. The bus can also transfer data and instructions to another device, such as a local or remote bus controller, and pass control of the scan-path select function to that device. This frees the primary controller to activate another secondary scan path elsewhere in the system or perform higher-level test control functions. When the RBC is ready to return control of the device, interrupt signals alert the primary controller. The least-significant bit (LSB) of any value scanned into any register of the device is the first bit shifted in (nearest to TDO). The most-significant bit (MSB) is the last bit shifted in (nearest to TDI). The ’ACT8999 is divided into functional blocks as detailed below. test ports The test ports decode the signals on TCK, TMS, OTMS, and TRST to control the operation of the circuit. Each test port includes a TAP controller that issues the proper control instructions to the data registers according to the IEEE Standard 1149.1 protocol. The TAP controller state diagram is shown in Figure 1. Two test ports are included on the ’ACT8999, allowing different test controllers to command different sections of the device. TMS circuit The TMS circuit decodes bits in the select and control registers to determine which one, if any, of the DTMS pins (which provide mode-select signals to the secondary scan path(s)) follow the TMS pin or OTMS pin. The unselected DTMS pins are set by the circuit to a static high or low level. instruction register The instruction register (IR) is an 8-bit-wide serial-shift register that issues commands to the device. Data is input to the instruction register via TDI or DTDI and shifted out via TDO. All device operations are initiated by loading the proper instruction or sequence of instructions into the IR. data registers Six parallel data registers are included in the ’ACT8999: bypass, control, counter, boundary-scan, ID-bus, and select. The ID bus register is a part of the boundary-scan register. Each data register is serially loaded via TDI or DTDI and outputs data via TDO. Table 1 summarizes the registers in the ’ACT8999. Table 1. Register Summary REGISTER NAME LENGTH (BITS) FUNCTION Instruction 8 Issue command information to the device Remote Instruction 8 Issue command information to the select register Control 13 Configuration and enable control Counter 8 Count events on DCI, output interrupts via DCO Select 8 Select one of four DTMS pins to follow TMS or OTMS Boundary Scan 15 Capture and force test data at device periphery ID Bus 8 Pass test commands and data between a PBC and RBC(s) Bypass 1 Remove the ’ACT8999 from the scan path • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 Terminal Functions TERMINAL NAME I/O DESCRIPTION DCI I Device condition input. DCI receives interrupt and protocol signals from an RBC and/or the secondary scan path(s). When the counter register is instructed to count up or down, DCI is configured as the counter clock. DCO O Device condition output. DCO is configured by the control register to output protocol and interrupt signals to a PBC. It also can be configured by the control register to output an error signal if the instruction register or select register are loaded with invalid values. DCO is further configured by the control register as: Active high or active low (reset condition = active low) Open drain or 3-state (reset condition = open drain) DTCK O Device test clock. DTCK outputs the buffered test clock TCK to the secondary scan path(s). DTDI I Device test data input. DTDI receives the serial test data output of the selected secondary scan path. An internal pullup forces DTDI to a high logic level if it is left unconnected. DTDO O Device test data output. DTDO outputs serial test data to the TDI input(s) of the secondary scan path(s). DTMS1 DTMS2 DTMS3 DTMS4 O Device test mode select 1−4. Either one or none of these four outputs can be selected to follow TMS or OTMS to include a secondary scan path in the primary scan path. The unselected DTMS outputs can be independently set to a static high or low logic level. The TMS circuit monitors input from the select register to determine the configuration of the DTMS outputs. DTRST O Device test reset. This active-low output transmits a reset signal to the secondary scan path(s). DTRST can be asserted by a bit in the control register or by setting TRST low. GND I/O MCI I Master condition input. MCI receives interrupt and protocol singals from a PBC. MCO O Master condition output. MCO transmits interrupt and protocol signals to an RBC and/or the secondary scan path(s). MCO also outputs an active-low error signal during the Pause-DR TAP state if an RBC loads an invalid value in the select register. OTMS I Optional test mode select. OTMS can be used instead of TMS to control the select register. This is useful when a remote bus controller is available to control the secondary scan path(s). An internal pullup forces OTMS to a high level if left unconnected. TCK I Test clock. One of four terminals required by IEEE Standard 1149.1. All operations of the ’ACT8999 except for the count function are synchronous to TCK. Data on the device inputs is captured on the rising edge of TCK, and outputs change on the falling edge of TCK. TDI I Test data input. One of four terminals required by IEEE Standard 1149.1. TDI is the serial input for shifting information into the instruction register or selected data register. TDI is typically driven by the TDO output of the primary bus controller. An internal pullup forces TDI to a high level if it is left unconnected. TDO O Test data output. One of four terminals required by IEEE Standard 1149.1. TDO is the serial output for shifting information out of the instruction register or selected data register. TDO is typically connected to the TDI input of the next scannable device in the primary scan path. TMS I Test mode select. One of four terminals required by IEEE Standard 1149.1. The level of TMS at the rising edge of TCK directs the ’ACT8999 through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. I Test reset. This active-low input inplements the optional reset terminal of IEEE Standard 1149.1. When asserted, TRST causes the ’ACT8999 to go to the Test-Logic-Reset state and configure the instruction register and data registers to their power-up values. TRST is also output without inversion via DTRST. An internal pullup forces TRST to a high level if left unconnected. TRST VCC 4 Ground ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 Identification 1−8. This 8-bit data bus can be used to communicate with an RBC and pass data and control instructions. By wiring pullup and pulldown resistors to these terminals, one of 255 unique identification codes can be assigned to the device to allow a test controller to determine the identity of the subsystem under test. Supply voltage • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 state diagram description The TAP proceeds through the states in Figure 1 according to IEEE Standard 1149.1. There are six stable states (indicated by a looping arrow) and ten unstable states in the diagram. A stable state is defined as a state the TAP can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state. There are two main paths through the state diagram: one to manipulate a data register and one to manipulate the instruction register. No more than one register can be manipulated at a time. Test-Logic-Reset TMS = H TMS = H TMS = L TMS = H TMS = H Run-Test / Idle Select-DR-Scan Select-IR-Scan TMS = L TMS = L TMS = L TMS = H TMS = H Capture-DR Capture-IR TMS = L TMS = L Shift-DR Shift-IR TMS = L TMS = L TMS = H TMS = H TMS = H TMS = H Exit1-DR Exit1-IR TMS = L TMS = L Pause-DR Pause-IR TMS = L TMS = L TMS = H TMS = L Exit2-DR TMS = H TMS = L Exit2-IR TMS = H Update-DR TMS = L TMS = H TMS = H Update-IR TMS = H TMS = L Figure 1. TAP-Controller State Diagram • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 Test-Logic-Reset In this state, the test logic is inactive and an internal reset signal is applied to all registers in the device. During device operation, the TAP returns to this state in no more than five TCK cycles if the test mode select (TMS) input is high. The TMS pin has an internal pullup that forces it to a high level if it is left unconnected or if a board defect causes it to be open circuited. The device powers up in the Test-Logic-Reset state. Run-Test /Idle The TAP must pass through this state before executing any test operations. The TAP may retain this state indefinitely, and no registers are modified while in Run-Test /Idle. The 8-bit programmable up/down counter can be operated in this state. Select-DR-Scan, Select-IR-Scan No specific function is performed in these states; the TAP exits either of them on the next TCK cycle. Capture-DR The selected data register is placed in the scan path (i.e., between TDI and TDO). Depending on the current instruction, data may or may not be loaded or captured by that register on the rising edge of TCK, causing the TAP state to change. Shift-DR In this state, data is serially shifted through the selected data register from TDI to TDO on each TCK cycle. The first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK cycle in which the TAP changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). On the falling edge of TCK in Shift-DR, TDO goes from the high-impedance state to the active state. TDO enables to the value present in the least-significant bit of the selected data register. Exit1-DR, Exit2-DR These are temporary states used to end the shifting process. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. The last shift occurs on the TCK cycle in which the TAP state changes from Shift-DR to Exit1-DR. TDO changes from the active state to the high-impedance state on the falling edge of TCK in Exit1-DR. Pause-DR The TAP can remain in this state indefinitely. The Pause-DR state suspends and resumes shift operations without loss of data. Update-DR If the current instruction calls for the latches in the selected data register to be updated with current data, the latches are updated only during this state. Capture-IR The instruction register is preloaded with the IR status word (see Table 4) and placed in the scan path. Shift-IR In this state, data is serially shifted through the instruction register from TDI to TDO on each TCK cycle. The first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK cycle in which the TAP changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). On the falling edge of TCK in Shift-IR, TDO goes from the high-impedance state to the active state, and will enable to a high level. 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 Exit1-IR, Exit2-IR These are temporary states used to end the shifting process. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. The last shift occurs on the TCK cycle in which the TAP state changes from Shift-IR to Exit1-IR. TDO changes from the active state to the high-impedance state on the falling edge of TCK in Exit1-IR. Pause-IR The TAP can remain in this state indefinitely. The Pause-IR state suspends and resumes shift operations without loss of data. Update-IR In this state, the latches shadowing the instruction register are updated with the new instruction. instruction register description The instruction register (IR) is an 8-bit serial register that outputs control signals to the device. Table 2 lists the instructions implemented in the ’ACT8999 and the data register selected by each instruction. The MSB of the IR is an even-parity bit. If the value scanned into the IR during Shift-IR does not contain even parity, an error signal (IRERR) is generated internally as shown in Table 3. The ’ACT8999 can be configured to output IRERR via DCO if the TAP enters the Pause-IR state. During the Capture-IR state, the IR status word is loaded. The IR status word contains information about the most recently loaded values of the instruction and select registers and the logic level present at the DCI input. The IR status word is encoded as shown in Table 4. Figure 2 shows the order of scan for the IR. TDI or DTDI Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) TDO Figure 2. Instruction-Register Bits and Order of Scan • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 7 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 Table 2. Instruction-Register Opcodes BINARY CODE BIT 7 → BIT 0 MSB → LSB HEX VALUE 00000000 10000001 SCOPE OPCODE DESCRIPTION SELECTED DATA REGISTER 00 EXTEST Boundary scan Boundary scan Test 81 BYPASS Bypass scan Bypass Normal 10000010 82 SAMPLE/PRELOAD Sample boundary Boundary scan Normal 00000011 03 Boundary scan Boundary scan Test 10000100 84 INTEST BYPASS† Bypass scan Bypass Normal 00000101 05 Bypass scan Bypass Normal 00000110 06 BYPASS† BYPASS† Bypass scan Bypass Normal 10000111 87 BYPASS† Bypass scan Bypass Normal 10001000 88 COUNT Count Bypass Normal 00001001 09 Count Bypass Normal 00001010 0A COUNT BYPASS† 10001011 8B 00001100 10001101 10001110 Bypass scan Bypass Normal Bypass scan Bypass Normal 0C BYPASS† BYPASS† Bypass scan Bypass Normal 8D BYPASS Bypass scan Bypass Normal 8E SCANCN Control register scan Control Normal 00001111 0F SCANCN Control register scan Control Normal 11111010 FA SCANCNT Counter scan Counter Normal 01111011 7B READCNT Counter read Counter Normal 11111100 FC SCANIDB ID bus register scan ID bus Normal 01111101 7D READIDB ID bus register read ID bus Normal 01111110 7E SCANSEL Select register scan Select Normal BYPASS Bypass scan Bypass Normal All others † A SCOPE opcode exists but is not supported by the ’ACT8999. Table 3. IRERR Function Table NO. OF INSTRUCTION REGISTER BITS = 1 IRERR 0, 2, 4, 6, 8 1 1, 3, 5, 7 0 Table 4. Instruction-Register Status Word IR BIT VALUE‡ 7 IRERR (see Table 3) 6 0 5 0 4 0 3 Level present at DCI input (1 = H, 0 = L) 2 SRERR (see Table 8) 1 0 0 1 ‡ This value is loaded in the instruction register during the Capture-IR TAP state. 8 MODE • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 instruction-register opcode description The operation of the ’ACT8999 is dependent on the instruction loaded into the instruction register. Each instruction selects one of the data registers to be placed between TDI or DTDI and TDO during the Shift-DR TAP state. All the required instructions of IEEE Standard 1149.1 are implemented in the ’ACT8999. boundary scan This instruction implements the required EXTEST and optional INTEST operations of IEEE Standard 1149.1. The boundary-scan register (which includes the ID-bus register) is placed in the scan path. Data appearing at input pins included in the boundary-scan register is captured. Data previously loaded into the output pins included in the boundary-scan register is forced through the outputs. bypass scan This instruction implements the required BYPASS operation of IEEE Standard 1149.1. The bypass register is placed in the scan path and preloads with a logic 0 during Capture-DR. sample boundary This instruction implements the required SAMPLE/PRELOAD operation of IEEE Standard 1149.1. The boundary-scan register is placed in the scan path, and data appearing at the inputs and outputs included in the boundary-scan register is sampled on the rising edge of TCK in Capture-DR. count The counter register begins counting on each DCI transition. The count begins from the value present in the register before the count instruction was loaded. The counter can be configured by the control register to count up or down on either the low-to-high or high-to-low transition of DCI. Counting occurs only while in the Run-Test /Idle TAP state. control-register scan The control register is placed in the scan path for a subsequent shift operation. The register is not preloaded during Capture-DR. counter-register scan The counter register is placed in the scan path. During Capture-DR, the current value of the counter is loaded in the counter register. At Update-DR, the newly shifted value is preloaded to the counter. counter-register read The counter register is placed in the scan path. During Capture-DR, the prior preload value of the counter is loaded into the counter register. At Update-DR, the newly shifted value is preloaded to the counter. ID-bus-register scan The ID-bus register (a subset of the boundary-scan register) is placed in the scan path for a subsequent shift operation. The data appearing on the ID bus is loaded into the ID-bus register on the rising edge of TCK in Capture-DR. ID-bus register read The ID-bus register is placed in the scan path for a subsequent shift operation. The register is not preloaded during Capture-DR. select-register scan The select register is placed in the scan path for a subsequent shift operation. The register is not preloaded during Capture-DR. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 9 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 control-register description The control register (CTLR) is a 13-bit serial register that controls the enable and select functions of the ’ACT8999. A reset operation forces all bits to a logic 0. The contents of the control register are latched and decoded during the Update-DR TAP state. The specific function of each bit is listed in Table 5. The enable and select functions of the control register bits are mapped as follows: Table 5. Control-Register Bit Mapping BIT 12 11 10 9, 8 7 6 5 4 3 2 1 0 VALUE FUNCTION 0 Configure counter to count up 1 Configure counter to count down 0 Do not stop counting when the count reaches 00000000 1 Stop counting when the count reaches 00000000 (count down only) 0 Configure DCO as an active-low output 1 Configure DCO as an active-high output 00 DCO = Inactive (level depends on CTLR bit 10) 01 DCO = (IRERR • SRERR) 10 DCO = CE, an internal logic 0 generated when the count is 00000000 (count down) or 11111111 (count up) 11 DCO = DCI 0 Do not mask IRERR and SRERR from DCO 1 Mask IRERR and SRERR from DCO 0 Configure DCO as an open-drain output 1 Configure DCO as a 3-state output 0 Disable DCO 1 Enable DCO 0 Configure DCI as an active-low input 1 Configure DCI as an active-high input 0 Enable DTCK, DTDO, and DTMS(1− 4) 1 Disable DTCK, DTDO, and DTMS(1− 4) 0 Disable ID(1− 8) 1 Enable ID(1− 8) 0 Disable RBC 1 Enable RBC 0 DTRST = TRST 1 DTRST = L Bit 12 − Up/Down This bit sets the count mode of the counter register (reset condition = count up). Bit 11 − Latch on Zero The counter register can be configured to stop counting when its value is 00000000 and ignore subsequent transitions on the counter clock, DCI. The latch-on-zero option is valid only in the count-down mode (reset condition = do not latch on zero). The value of this bit has no effect on the operation of the counter if CTLR bit 12 = 0. Bit 10 − DCO Polarity Select DCO can be configured as an active-low or active-high output (reset condition = active low). 10 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 Bit 9/Bit 8 − DCO Source Select 1/DCO Source Select 0 DCO can be used to output two error signals generated by the ’ACT8999: IRERR (see Table 3) and SRERR (see Table 8). Bits 9 and 8 can be set to output IRERR via DCO on the falling edge of TCK in the Pause-IR state and SRERR via DCO on the falling edge of TCK in the Pause-DR state. DCO also can be configured to become active when the value of the counter is 00000000, to follow DCI, or be set to a static high or low level (reset condition = static high level). Bit 7 − Parity Mask The internal error signals can be masked from appearing on DCO even if bits 9 and 8 are set such that IRERR and SRERR are output in the Pause-IR and Pause-DR states (reset condition = do not mask IRERR or SRERR). Bit 6 − DCO Drive Select DCO can be configured as either an open-drain or 3-state output (reset condition = open drain). The open-drain configuration allows multiple DCO outputs to be used in a wired-OR or wired-AND application. The 3-state configuration allows the DCO output to be connected to a bus. Bit 5 − DCO Enable When configured as a 3-state output, DCO can be placed in the high-impedance state (reset condition = disabled). If configured as an open-drain output and disabled, DCO outputs a high level. Bit 4 − DCI Polarity Select DCI can be configured as an active-low or active-high input (reset condition = active low). Bit 3 − Device Test Pins Output Enable (active low) DTCK, DTDO, and DTMS(1−4) pins can be placed in the high-impedance state (disabled) with this bit (reset condition = enabled). Bit 2 − ID Bus Enable The ID bus (ID1−8) is a bidirectional bus. The output buffers are enabled and disabled with this bit (reset condition = output buffers disabled). Bit 1 − Remote-Bus-Controller (RBC) Enable An RBC can issue protocol and data instructions to the select register if the ’ACT8999 is configured to allow it (reset condition = RBC disabled). When an RBC is enabled, the TAP in the select register operates according to the OTMS signal. Bit 0 − Device Test Reset DTRST can be configured to output a reset signal independently of the level on TRST (reset condition = no reset signal issued). Several control-register bits affect the functionality of the DCO output. The DCO function table is given in Table 6. Figure 3 shows the order of scan for the control register. TDI or DTDI Bit 12 (MSB) Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) TDO Figure 3. Control-Register Bits and Order of Scan • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 11 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 Table 6. DCO Function Table INTERNAL SIGNALS† DCI CONTROL REGISTER BITS‡ DCO IRERR SRERR CE BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 X X X X X X X X 0 0 X X X X X X X X X 1 0 X Z X X X X 0 0 0 X X 1 X H X X X X 1 0 0 X X 1 X L X X X X 0 0 1 1 X 1 X H X X X X 1 0 1 1 X 1 X L X 0 X X 0 0 1 0 X 1 X L in Pause-IR§, H otherwise X X 0 X 0 0 1 0 X 1 X L in Pause-DR§, H otherwise X 1 1 X 0 0 1 0 X 1 X H X 0 X X 1 0 1 0 X 1 X H in Pause-IR§, L otherwise X X 0 X 1 0 1 0 X 1 X H in Pause-DR§, L otherwise L H X 1 1 X 1 0 1 0 X 1 X X X X 0 0 1 0 X X 1 X L X X X 0 1 1 0 X X 1 X H X X X 1 0 1 0 X X 1 X H X X X 1 1 1 0 X X 1 X L L X X X 1 1 1 X X 1 0 H L X X X 1 1 1 X X 1 1 L L X X X 0 1 1 X X 1 0 L L X X X 0 1 1 X X 1 1 H H X X X 1 1 1 X X 1 0 L H X X X 1 1 1 X X 1 1 H H X X X 0 1 1 X X 1 0 H H X X X 0 1 1 X X 1 1 L † These signals are generated as described elsewhere in this data sheet. ‡ The control register must contain these values after the TAP has passed through its most recent Update-DR state. § DCO becomes active on the falling edge of TCK as the TAP enters the appropriate pause state (Pause-IR or Pause-DR) and becomes inactive on the falling edge of TCK as the TAP enters the appropriate exit2 state (Exit2-IR or Exit2-DR). select register description The select register (SR) is an 8-bit serial register that determines which one, if any, of the DTMS lines follows the TMS or OTMS input. A reset operation forces all bits to a logic 0. The register is divided into four 2-bit sections, each of which controls one DTMS output. Figure 4 shows the mapping of the bits to the DTMS outputs and the order of scan. For each DTMS pin, the higher-order bit is the MSB and the lower-order bit is the LSB (e.g., bit 3 is the MSB of DTMS2 and bit 2 is the LSB of DTMS2). TDI or DTDI Bit 7 (MSB) DTMS4 Bit 6 Bit 5 Bit 4 Bit 3 DTMS3 Bit 2 DTMS2 Figure 4. Select Register Bits and Order of Scan 12 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • Bit 0 (LSB) Bit 1 DTMS1 TDO SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 select register description (continued) Only one of the four DTMS outputs can be selected to drive a secondary scan path with TMS or OTMS. If the SR is loaded with an invalid value, an error signal (SRERR) is generated internally as shown in Table 8. If the TAP enters the Pause-DR state, SRERR may be output via DCO (see Table 8). If the TAP enters the Update-DR state while an invalid value is in the SR, all four DTMS outputs are set to a high level. When a new 8-bit value is loaded into the SR, the configuration of one or more DTMS pins may change. If the new value of the SR configures a DTMS pin to a static (high or low) level, it assumes that level on the falling edge of TCK in the Update-DR TAP state. This condition is independent of any previous SR configurations. If the new value of the SR forces a DTMS pin to follow TMS (i.e., select a single secondary scan path) and a DTMS pin is currently in the TMS/OTMS-follow mode, the transfer of the DTMS line occurs on the falling edge of TCK in the Update-DR TAP state. However, if the new configuration forces a DTMS pin to follow TMS/OTMS while no other DTMS pin is selected, the DTMS pin does begin following TMS/OTMS until the falling edge of TCK in the Run-Test/Idle TAP state; therefore, when an SSP is initially selected, the TAP state should travel from Update-DR to Run-Test/Idle, not from Update-DR to Select-DR-Scan. Additionally, when deselecting from any DTMS output the TAP state must proceed back through Capture-DR to fully disconnect from SSP operations. The SR can also be accessed from an RBC. A test port in the register contains a TAP that can be enabled by the control register to monitor the values of TCK and OTMS to perform scan operations on the SR. The SR bit decoding is shown in Table 7. Table 7. Select-Register Bit Decoding MSB LSB DTMS SOURCE 0 0 H 0 1 L 1 0 OTMS 1 1 TMS Table 8. SRERR Function Table SELECT REGISTER BITS SRERR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 X 0 X 0 X 0 X 1 1 X 0 X 0 X 0 X 1 0 X 1 X 0 X 0 X 1 0 X 0 X 1 X 0 X 1 0 X 0 X 0 X 1 X 1 1 X 1 X X X X X 0 1 X X X 1 X X X 0 1 X X X X X 1 X 0 X X 1 X 1 X X X 0 X X 1 X X X 1 X 0 X X X X 1 X 1 X 0 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 13 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 boundary-scan register/ID-bus register description The boundary-scan register (BSR) is a 15-bit serial register that can be used to capture data appearing at selected device inputs, force data through device outputs, and apply data to the device’s internal logic. The BSR is made up of boundary-scan cells (BSCs). Table 9 lists the device signal for each of the 15 BSCs that comprise the BSR. A reset operation does not affect the contents of the BSR. Table 9. Boundary-Scan Register Bit Mapping TERMINAL NAME BIT SIGNAL DESCRIPTION 14 MCI Master condition in 13 MCO Master condition out 12 DCI 11 DCOTS† Enable control for DCO in 3-state configuration (active low) 10 DCOOD† Enable control for DCO in open-drain configuration (active low) 9 8 DCO IDBOE† 7 ID8 Identification bus bit 8 6 ID7 Identification bus bit 7 5 ID6 Identification bus bit 6 4 ID5 Identification bus bit 5 3 ID4 Identification bus bit 4 2 ID3 Identification bus bit 3 1 ID2 Identification bus bit 2 0 ID1 Device condition in Device condition out Enable control for ID bus (active low) Identification bus bit 1 † This internal signal cannot be observed from the I/O pins of the device. The eight BSCs connected to the ID(1−8) pins form a subset of the BSR called the ID-bus register (IDBR). The IDBR can be scanned without accessing the remaining BSCs of the BSR. The IDBR is used when the ID bus is enabled to allow communication between a PBC and one or more RBCs. Figure 5 shows the order of scan for the BSR and IDBR. TDI or DTDI TDO Bit 0 (LSB) Bit 14 (MSB) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 TDI or DTDI Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 IDBR Figure 5. Boundary-Scan Register Bits and Order of Scan 14 Bit 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • Bit 7 BSR SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 bypass register description The bypass register (BR) is a 1-bit serial register. The function of the BR is to provide a means of effectively removing the ’ACT8999 from the primary scan path when it is not needed for the current test operation or other function of the PBC. A selected secondary scan path remains active in the primary scan path as described in the data flow description. At power up, the BR is placed in the scan path. Figure 6 shows the order of scan for the bypass register. TDI or DTDI TDO Bit 0 Figure 6. Bypass-Register Bit and Order of Scan counter register description The counter register (CNTR) is an 8-bit serial register and an associated 8-bit parallel-load up/down counter. A reset operation forces all bits of the shift register to logic 0 but does not affect the counter. The counter can be preloaded with an initial value before counting begins, and the current value of the counter can be scanned out via the shift register. The CNTR can be used to count events occurring on the secondary scan path(s) using DCI as a counter clock and can output interrupt signals via DCO when the count has reached its end value. An internal signal, CE, is generated as a logic 0 when the count reaches its end value (i.e., 00000000 for count down, 11111111 for count up). For any other count value, CE is a logic 1. Many of the features of the CNTR are configured by a bit in the CTLR, including: − Count direction up or down (control register bit 12; reset condition count up) − Stop counting upon counting down to 00000000 (control register bit 11; reset condition = do not latch on zero) − Output CE signals at DCO (control register bits 8 and 9; reset condition = do not output CE at DCO) − Edge of DCI on which to trigger (control register bit 4, reset condition = positive edge) Figure 7 shows the order of scan for the CNTR. TDI or DTDI Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) TDO Figure 7. Counter-Register Bits and Order of Scan • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 15 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 enabling a remote bus controller Bit 1 in the control register allows a remote bus controller to control parts of the ’ACT8999. When an RBC is enabled, the remote test port (RTP) in the select register is activated. The RTP operates according to the same state diagram as the primary test port but only has access to the select register. Operation of the RTP is synchronous to TCK. OTMS is the RTP mode-select pin. The RTP contains an 8-bit instruction register. Data is shifted in via DTDI and shifted out via DTDO. As shown in Table 10, only one instruction selects something other than the bypass register to be included in the scan path. When SCANSEL is executed, the select register is placed between DTDI and DTDO. The function of the select register and the decoding of the select register bits by the TMS circuit is identical, regardless of which test port accesses the register. Table 10. Remote-Test-Port Instruction-Register Opcodes BINARY CODE BIT 7 → BIT 0 MSB → LSB SCOPE OPCODE DESCRIPTION 01111110 SCANSEL Select-register scan Select All other BYPASS Bypass scan Bypass SELECTED DATA REGISTER An internal error signal (RSRERR) is generated if an RBC loads an invalid value in the select register, and the MCO output goes low if the RSRERR is active and the remote TAP enters the Pause-DR state. The function table for RSRERR is shown in Table 11. Table 11. RSRERR Function Table SELECT REGISTER BITS RSRERR MCO† X 1 MCI X 1 MCI 0 X 1 MCI 0 X 1 MCI X 1 X 1 MCI X X X X 0 L 1 X X X 0 L X X 1 X 0 L X 1 X X X 0 L X X X 1 X 0 L BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 X 0 X 0 X 0 1 X 0 X 0 X 0 0 X 1 X 0 X 0 X 0 X 1 X 0 X 0 X 0 1 X 1 X 1 X X X 1 X X X X X 1 X X 1 X X X X 1 X 1 X 0 L † This table is valid only when the remote TAP is in the Pause-DR state. Under any other condition, MCO = MCI. The RTP does not have access to the control register, so it cannot disable itself. The PBC must reset bit 1 in the control register to return control of the select register to the primary test port. 16 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 data flow description The direction of serial data flow in the ’ACT8999 is dependent on the current instruction. Figure 8 shows the data flow for the different operating modes of the device. When a secondary scan path is selected, the ’ACT8999 adds one bit of delay from TDI to DTDO. ’ACT8999 TDI IR or Selected DR TDO RBC DISABLED, NO SECONDARY SCAN PATH SELECTED Selected Scan Path ’ACT8999 TDI (1-bit delay) DTDO TDI ’ACT8999 TDO DTDI IR or Selected DR TDO RBC DISABLED, ONE SECONDARY SCAN PATH SELECTED Remote Bus Controller ’ACT8999 DTDI TDI Secondary IR DTDO or Select Register IR or Selected DR TDI TDO Selected Scan Path TDI TDO TDO RBC ENABLED Figure 8. Data Flow in the ’ACT8999 bus-communication protocol The 8-bit identification bus [ID(1−8)] allows data transfer between a PBC and an RBC. Control register bit 2 configures the ’ACT8999 to transmit or receive command and test data via the IDBR. The DCI, DCO, MCI, and MCO pins are used to signal the PBC and RBC(s) that a data transfer is required. The ’ACT8999 can accommodate either local or global handshake protocol, depending on the number of DCO inputs that the PBC can accommodate. Figure 9 shows a protocol for local communication between the PBC and an RBC. In this mode, communication is initiated by the PBC by driving the MCI input of the ’ACT8999 to a low level. MCI is buffered and output on MCO, which notifies the RBC that control of a scan path is to be relinquished. Prior to activating the MCI signal, the PBC scans the value 00000000 into the IDBR and enables the output buffers of ID(1−8). When the RBC recognizes that MCO has gone low, it samples the ID bus and looks for the 00000000 value to verify that the PBC is going to issue further commands. Upon verifying the value on the ID bus, the RBC drives DCI low, which is buffered and output via DCO. (In this example, DCI is configured as noninverting and DCO is configured as active low). When the PBC sees that DCO is active, it takes MCI high, forcing MCO high. When the RBC sees that MCO is high, it takes DCO high (inactive) completing one handshake cycle. A similar operation can ensue when the RBC initiates communication with the PBC as shown in Figure 9. Commands and test data can be exchanged between two bus controllers via the ID bus. Figure 10 shows one way of using the ID bus to interface a PBC to multiple RBCs. The timing is similar to the local communication example in Figure 9, except that the PBC waits for all RBCs to acknowledge transmissions before switching MCI. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 17 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 ID(1−8) IDCODE 00000000 COMMAND 00000000 IDCODE 00000000 IDCODE MCI DCO LOCAL PBC-TO-RBC HANDSHAKE PROTOCOL ID(1−8) IDCODE 00000000 COMMAND DCI MCO LOCAL RBC-TO-PBC HANDSHAKE PROTOCOL Figure 9. Local Bus-Communication Protocol ID(1−8) IDCODE 00000000 COMMAND 00000000 IDCODE MCI DCO1 DCO2 DCOn GLOBAL PBC-TO-RBC HANDSHAKE PROTOCOL ID(1−8) IDCODE 00000000 COMMAND 00000000 DCI1 DCI2 DCIn MCO GLOBAL RBC-TO-PBC HANDSHAKE PROTOCOL Figure 10. Global Bus-Communication Protocol 18 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • IDCODE SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . . 1.7 W NT package . . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage rating may be exceeded if the input and output clamp-current rating are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the NT package, which has trace length of zero. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. recommended operating conditions SN54ACT8999 VCC VIH Supply voltage VIL VI Low-level input voltage VO Output voltage High-level input voltage MIN MAX MIN MAX 4.5 5.5 4.5 5.5 2 High-level output current 0 0 TA Low-level output current VCC VCC 0 0 0.8 V V −7 −10 DTMS(1−4), DCO (3 state), DTRST, DTCK −11 −16 ID(1−8) 1.5 2 7 10 DTMS(1−4), DCO (3 state or open drain) 11 16 DTRST 16 24 DTCK 32 48 Operating free-air temperature −55 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 125 0 V VCC VCC −2 TDO, DTDO, MCO UNIT V −1.5 TDO, DTDO, MCO IOL 2 0.8 Input voltage ID(1−8) IOH SN74ACT8999 70 V mA mA °C 19 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54ACT8999 PARAMETER TEST CONDITIONS VCC MIN 3.6 MAX SN74ACT8999 TYP† MAX MIN UNIT IOH = −1.5 mA IOH = −2 mA 4.5 V ID(1−8) 4.5 V TDO, DTDO, MCO IOH = −7 mA IOH = −10 mA DTMS(1−4), DCO (3 state), DTRST, DTCK IOH = −11 mA IOH = −16 mA 4.5 V IOL = 1.5 mA IOL = 2 mA 4.5 V ID(1−8) IOL = 7 mA IOL = 10 mA 4.5 V TDO, DTDO, MCO DTMS(1−4), DCO (3 state or open drain) IOL = 11 mA IOL = 16 mA 4.5 V IOL = 16 mA IOL = 24 mA 4.5 V DTRST IOL = 32 mA IOL = 48 mA 4.5 V DTCK IOZ‡ ID(1−8), DTDO, DTMS(1−4), DCO, DTCK VO = VCC or GND 5.5 V ±10 ±5 µA IOH DCO (open drain) VO = VCC VI = VCC or GND 5.5 V 20 10 µA 5.5 V ±1 ±1 VI = VCC VI = GND 5.5 V ±1 ±1 VI = VCC or GND, IO = 0 One input at VI = 3.4 V, Other inputs at VCC or GND 5.5 V 100 100 µA 5.5 V 1 1 mA VOH VOL MCI, DCI, TCK II TDI, DTDI, TMS, OTMS, TRST ICC ∆ICC§ Ci 3.7 3.6 4.5 V MCI, DCI, TCK V 3.7 3.6 4.5 V 3.7 0.5 4.5 V 0.5 0.5 4.5 V 0.5 0.5 4.5 V 0.5 0.5 0.5 4.5 V 5.5 V V 0.5 4.5 V 0.5 −0.1 VI = VCC or GND VO = VCC or GND Cio Co 4.5 V VO = VCC or GND VO = VCC or GND −20 −0.1 −0.1 µA −20 6 pF 15 pF 15 pF Co DCO 10 pF † Typical values are at VCC = 5 V. ‡ For I/O, the parameter IOZ includes the input-leakage current. For DCO, the parameter IOZ includes the open-drain output-leakage current. § This is the increase in supply current for each input being driven at TTL levels rather than VCC or GND. 20 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 11 and 12) SN54ACT8999 fclock Clock frequency MAX MIN MAX TCK 0 20 0 20 DCI (count mode) 0 20 0 20 TCK high or low tw Pulse duration DCI high or low (count mode) th Hold time 9 10 9 9 OTMS before TCK↑ 12 12 TDI before TCK↑ 11 11 DTDI before TCK↑ 5 5 MCI before TCK↑ 5 5 DCI before TCK↑ 9 9 Any ID before TCK↑ 3 3 TMS after TCK↑ 2 2 OTMS after TCK↑ 2 2 TDI after TCK↑ 4 4 DTDI after TCK↑ 4 4 MCI after TCK↑ 5 5 DCI after TCK↑ 5 5 Any ID after TCK↑ 5 5 100* 100 td Delay time Power up to TCK↑ * On products compliant to MIL-PRF-38535, this parameter is not production tested. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • UNIT MHz 16 9 TMS before TCK↑ Setup time 16 10 TRST low tsu SN74ACT8999 MIN ns ns ns ns 21 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 11 and 12) PARAMETER fmax FROM (INPUT) TO (OUTPUT) MAX SN74ACT8999 MIN TCK 20 20 20 20 TCK DTCK tPLH tPHL TCK↓ TDO tPLH tPHL TCK↓ DTDO tPLH tPHL TCK↓ Any DTMS tPLH tPHL TCK↓ DTRST tPLH tPHL TCK↓ Any ID tPLH tPHL TCK↓ MCO tPLH TCK↓ tPHL 3 14 3 19 3 17 7 30 7 28 7 29 8 27 7 31 7 29 7 29 8 27 11 40 11 38 11 37 11 35 9 35 10 33 9 35 10 33 20 64 22 61 22 65 24 62 9 34 9 32 9 31 9 29 DCO (open drain) 14 45 18 42 DCO (3 state) 10 40 11 38 DCO (open drain) 10 39 11 37 DCO (3 state) 10 37 11 35 5 22 6 20 4 23 5 21 5 22 6 20 4 23 5 21 7 26 8 24 6 25 7 23 DCO (open drain) 8 32 9 30 Any DTMS tPLH tPHL OTMS Any DTMS tPLH tPHL MCI MCO tPHL DCO (3 state) 8 30 10 28 DCO (open drain) 8 34 9 32 DCO (3 state) 8 30 9 28 4 20 5 18 5 25 6 23 TRST DTRST • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • UNIT MHz 16 TMS DCI MAX 3 tPLH tPHL tPLH 22 MIN DCI (count mode) tPLH tPHL tPLH tPHL SN54ACT8999 ns ns ns ns ns ns ns ns ns ns ns ns ns SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 11 and 12) (continued) PARAMETER FROM (INPUT) TO (OUTPUT) tPHZ tPLZ TCK↓ TDO tPHZ tPLZ TCK↓ DTDO tPHZ tPLZ TCK↓ Any DTMS tPHZ tPLZ TCK↓ DCO tPHZ tPLZ TCK↓ Any ID tPHZ tPLZ DCI Any ID tPZH tPZL TCK↓ TDO tPZH tPZL TCK↓ DTDO tPZH tPZL TCK↓ Any DTMS tPZH tPZL TCK↓ DCO tPZH tPZL TCK↓ Any ID tPZH tPZL MCI Any ID • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SN54ACT8999 SN74ACT8999 MIN MAX MIN MAX 3 17 4 15 3 18 5 16 3 18 3 16 7 26 7 24 7 26 8 24 7 28 7 26 9 28 12 26 7 31 7 29 12 38 14 36 9 34 10 32 8 27 9 25 10 33 15 31 9 35 9 33 9 36 11 34 10 39 11 37 10 40 12 38 8 34 9 32 8 34 9 32 12 46 14 43 10 38 11 36 20 73 22 70 22 58 24 65 18 65 20 62 20 62 20 59 UNIT ns ns ns ns ns ns ns ns ns ns ns ns 23 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 APPLICATION INFORMATION Subsystem SSP4 TDO TCK TMS TDI SSP3 TDO TCK TMS TRST TDI SSP2 TDO TCK TMS TRST TDI SSP1 TDO TCK TMS TRST TDI TRST INT3 DCI TDI DTDO INT2 MCO TMSOUT DTDI DTCK TDO MCI TCK ID(1−8) TMS 8 TRST OTMS DCO ID ’ACT8999 TDI RBC DTMS(1− 4) DTRST TRST TDO INT1 4 TDO INT1 RSTOUT PBC To Remainder of Primary Scan Path TMSOUT TCKOUT INT2 TDI 24 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V th 1.5 V 3V 1.5 V 1.5 V Data Input 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION Output Control (low-level enabling) 3V Input 1.5 V 1.5 V 0V tPHL tPLH In-Phase Output tPLH tPHL Out-of-Phase Output Output Waveform 2 S1 at GND (see Note B) VOH 50% VCC VOL 50% VCC 0V tPZL tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) VOH 50% VCC VOL 50% VCC 3V 1.5 V 1.5 V 50% VCC tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES [ VCC 20% VCC VOL tPHZ 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. For testing pulse duration: tr = 1 to 3 ns, tf = 1 to 3 ns. Pulse polarity may be either high-to-low-to-high or a low-to-high-to-low. D. The outputs are measured one at a time with one input transition per measurement. Figure 11. Load Circuit and Voltage Waveforms (For All Pins Except ID-Bus Pins) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 25 SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 PARAMETER MEASUREMENT INFORMATION VCC S1 1k Ω From Output Under Test Open GND TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VCC GND CL = 50 pF (see Note A) LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V th 1.5 V 3V 1.5 V 1.5 V Data Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 3V 1.5 V Input 1.5 V 0V tPHL tPLH In-Phase Output tPLH tPHL Out-of-Phase Output Output Waveform 2 S1 at GND (see Note B) VOH 50% VCC VOL 50% VCC 0V tPZL tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) VOH 50% VCC VOL 50% VCC 3V 1.5 V 1.5 V 50% VCC tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES [ VCC 10% VCC VOL tPHZ 50% VCC 90% VCC VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. For testing pulse duration: tr = 1 to 3 ns, tf = 1 to 3 ns. Pulse polarity may be either high-to-low-to-high or a low-to-high-to-low. D. The outputs are measured one at a time with one input transition per measurement. Figure 12. Load Circuit and Voltage Waveforms (ID-Bus Pins) 26 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74ACT8999DW OBSOLETE SOIC DW 28 TBD Call TI Call TI SN74ACT8999NT OBSOLETE PDIP NT 28 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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