TI SN74LVTH182652APM

SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
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Members of the Texas Instruments
SCOPE  Family of Testability Products
Members of the Texas Instruments
Widebus  Family
State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation
Down to 2.7 V
Include D-Type Flip-Flops and Control
Circuitry to Provide Multiplexed
Transmission of Stored and Real-Time Data
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
B-Port Outputs of ’LVTH182652A Devices
Have Equivalent 25-Ω Series Resistors, So
No External Resistors Are Required
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Compatible With the IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture
SCOPE Instruction Set
– IEEE Std 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
Packaged in 64-Pin Plastic Thin Quad Flat
(PM) Packages Using 0.5-mm
Center-to-Center Spacings and 68-Pin
Ceramic Quad Flat (HV) Packages Using
25-mil Center-to-Center Spacings
description
The ’LVTH18652A and ’LVTH182652A scan test devices with 18-bit bus transceivers and registers are
members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices
supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan
access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed
transmission of data directly from the input bus or from the internal registers. They can be used either as two
9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot
samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating
the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers
and registers.
Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and
output-enable (OEAB and OEBA) inputs. For A-to-B data flow, data on the A bus is clocked into the associated
registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation
to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus
(registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the
high-impedance state.
Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA, and OEBA inputs. Since
the OEBA input is active-low, the A outputs are active when OEBA is low and are in the high-impedance state
when OEBA is high. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with the ’LVTH18652A and ’LVTH182652A.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
description (continued)
In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The B-port outputs of ’LVTH182652A, which are designed to source or sink up to 12 mA, include equivalent 25-Ω
series resistors to reduce overshoot and undershoot.
The SN54LVTH18652A and SN54LVTH182652A are characterized for operation over the full military
temperature range of –55°C to 125°C. The SN74LVTH18652A and SN74LVTH182652A are characterized for
operation from –40°C to 85°C.
1A2
1A1
1OEBA
GND
1SAB
1CLKAB
TDO
V CC
NC
TMS
1CLKBA
1SBA
1OEAB
GND
1B1
1B2
1B3
SN54LVTH18652A, SN54LVTH182652A . . . HV PACKAGE
(TOP VIEW)
9
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
NC
VCC
2A1
2A2
2A3
GND
2A4
2A5
2A6
8 7
6 5 4 3 2
1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
VCC
TCK
2CLKBA
2SBA
GND
2OEAB
2B9
2B8
2A7
2A8
2A9
GND
2OEBA
2SAB
2CLKAB
TDI
NC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC – No internal connection
2
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• DALLAS, TEXAS 75265
1B4
1B5
1B6
GND
1B7
1B8
1B9
VCC
NC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
1A2
1A1
1OEBA
GND
1SAB
1CLKAB
TDO
V CC
TMS
1CLKBA
1SBA
1OEAB
GND
1B1
1B2
1B3
SN74LVTH18652A, SN74LVTH182652A . . . PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
VCC
2A1
2A2
2A3
GND
2A4
2A5
2A6
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
1B4
1B5
1B6
GND
1B7
1B8
1B9
VCC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
2A7
2A8
2A9
GND
2OEBA
2SAB
2CLKAB
TDI
VCC
TCK
2CLKBA
2SBA
GND
2OEAB
2B9
2B8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
FUNCTION TABLE
(normal mode, each 9-bit section)
DATA I/O
INPUTS
OPERATION OR FUNCTION
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1–A9
B1–B9
L
H
L
L
X
X
Input disabled
Input disabled
Isolation
Input
Unspecified†
Store A and B data
Store A in both registers
L
H
↑
↑
X
X
Input
X
H
↑
L
X
Input
H
H
↑
↑
X
X‡
X
X
L
↑
X
Input
Hold A, store B
L
L
↑
↑
X
X
X‡
Input
Unspecified†
Output
L
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
X
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
X
X
H
X
Input
Output
Stored A data to B bus
Output
Stored A data to B bus and
stored B data to A bus
H
L
X
X
H
H
Output
Store A, hold B
† The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡ Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
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3
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
OEAB OEBA
L
L
CLKAB CLKBA SAB
X
X
X
BUS B
BUS A
BUS A
BUS B
SCBS312C – MARCH 1994 – REVISED JUNE 1997
SBA
L
OEAB OEBA
H
H
OEBA
H
X
H
CLKAB CLKBA SAB
↑
X
↑
X
↑
↑
X
X
X
SBA
X
X
X
OEAB
H
SBA
X
BUS B
OEBA
L
CLKAB
CLKBA
SAB
SBA
X
X
H
H
TRANSFER STORED DATA
TO A AND/OR B
STORAGE FROM
A, B, OR A AND B
Figure 1. Bus-Management Functions
4
SAB
L
BUS A
BUS A
OEAB
X
L
L
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
CLKAB
X
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
functional block diagram
Boundary-Scan Register
1OEAB
1OEBA
1CLKBA
1SBA
1CLKAB
1SAB
53
62
VCC
GND
55
54
59
60
C1
1D
1A1
63
51
C1
1D
1B1
One of Nine Channels
2OEAB
30
VCC
2OEBA
2CLKBA
2SBA
2CLKAB
2SAB
21
GND
27
28
23
22
C1
1D
2A1
40
10
C1
1D
2B1
One of Nine Channels
Bypass Register
Boundary-Control
Register
Identification
Register
TDI
TMS
TCK
24
56
VCC
58
Instruction
Register
TDO
VCC
26
TAP
Controller
Pin numbers shown are for the PM package.
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5
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
Terminal Functions
TERMINAL NAME
Normal-function A-bus I/O ports. See function table for normal-mode logic.
1B1–1B9,
2B1–2B9
Normal-function B-bus I/O ports. See function table for normal-mode logic.
1CLKAB, 1CLKBA,
2CLKAB, 2CLKBA
GND
Normal-function clock inputs. See function table for normal-mode logic.
Ground
1OEAB, 2OEAB
Normal-function active-high output enables. See function table for normal-mode logic. An internal pulldown at each
terminal forces the terminal to a low level if left unconnected.
1OEBA, 2OEBA
Normal-function active-low output enables. See function table for normal-mode logic. An internal pullup at each terminal
forces the terminal to a high level if left unconnected.
1SAB, 1SBA,
2SAB, 2SBA
6
DESCRIPTION
1A1–1A9,
2A1–2A9
Normal-function select controls. See function table for normal-mode logic.
TCK
Test clock. One of four terminals required by IEEE Std 1149.1-1990. Test operations of the device are synchronous TCK.
Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.
TDI
Test data input. One of four terminals required by IEEE Std 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
TDO
Test data output. One of four terminals required by IEEE Std 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.
TMS
Test mode select. One of four terminals required by IEEE Std 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected.
VCC
Supply voltage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Std 1149.1-1990.
Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller
monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the synchronization (TCK)
and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the
test structures in the device. Figure 2 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Std 1149.1-1990 4-wire test bus and boundary-scan architecture
and the relationship among the test bus, the TAP controller, and the test registers. As shown, the device contains
an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit
boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = H
TMS = H
Run-Test /Idle
TMS = H
Select-DR-Scan
Select-IR-Scan
TMS = L
TMS = L
TMS = L
TMS = H
TMS = H
Capture-DR
Capture-IR
TMS = L
TMS = L
Shift-DR
Shift-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = H
TMS = H
Exit1-DR
Exit1-IR
TMS = L
TMS = L
Pause-DR
Pause-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = L
TMS = L
Exit2-DR
Exit2-IR
TMS = H
Update-DR
TMS = H
TMS = L
TMS = H
Update-IR
TMS = H
TMS = L
Figure 2. TAP-Controller State Diagram
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
state diagram description
The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram shown in Figure 2 is in accordance with IEEE Std 1149.1-1990. The TAP controller proceeds
through its states based on the level of TMS at the rising edge of TCK.
As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is defined as a state the TAP controller can retain for
consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers can also be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the ’LVTH18652A and ’LVTH182652A, the instruction register is reset to the binary value 10000001, which
selects the IDCODE instruction. Bits 47–46 in the boundary-scan register are reset to logic 0 while bits 45–44
are reset to logic 1, ensuring that these cells, which control A-port and B-port outputs, are set to benign values
(i.e., such that if test mode were invoked the outputs would be at high-impedance state). Reset values of other
bits in the boundary-scan register should be considered indeterminate. The boundary-control register is reset
to the binary value 010, which selects the PSA test operation.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test
operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
8
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SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, such update occurs
on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the ’LVTH18652A and
’LVTH182652A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO, and
on the first falling edge of TCK, TDO goes from the high-impedance state to the active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the
first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss
of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
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9
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
register overview
With the exception of the bypass and device-identification registers, any test register can be thought of as a
serial-shift register with a shadow latch on each bit. The bypass and device identification registers differ in that
they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,
Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current
instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted
out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or
Update-DR), the shadow latches are updated from the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the four data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 3 lists the instructions supported by the ’LVTH18652A and ’LVTH182652A. The even-parity feature
specified for SCOPE devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any
instructions that are defined for SCOPE devices but are not supported by this device default to BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 3.
TDI
Bit 7
Parity
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Figure 3. Instruction Register Order of Scan
10
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Bit 1
Bit 0
(LSB)
TDO
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
data register description
boundary-scan register
The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and
output data). The BSR is used 1) to store test data that is to be applied externally to the device output pins,
and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at
the device input pins.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle, as determined by the current instruction. At power up
or in Test-Logic-Reset, BSCs 47–46 are reset to logic 0 while BSCs 45–44 are reset to logic 1, ensuring that
these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked
the outputs would be at high-impedance state). Reset values of other BSCs should be considered
indeterminate.
The BSR order of scan is from TDI through bits 47–0 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.
Table 1. Boundary-Scan Register Configuration
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
47
2OEAB
35
2A9-I/O
17
2B9-I/O
46
1OEAB
34
2A8-I/O
16
2B8-I/O
45
2OEBA
33
2A7-I/O
15
2B7-I/O
44
1OEBA
32
2A6-I/O
14
2B6-I/O
43
2CLKAB
31
2A5-I/O
13
2B5-I/O
42
1CLKAB
30
2A4-I/O
12
2B4-I/O
41
2CLKBA
29
2A3-I/O
11
2B3-I/O
40
1CLKBA
28
2A2-I/O
10
2B2-I/O
39
2SAB
27
2A1-I/O
9
2B1-I/O
38
1SAB
26
1A9-I/O
8
1B9-I/O
37
2SBA
25
1A8-I/O
7
1B8-I/O
36
1SBA
24
1A7-I/O
6
1B7-I/O
––
––
23
1A6-I/O
5
1B6-I/O
––
––
22
1A5-I/O
4
1B5-I/O
––
––
21
1A4-I/O
3
1B4-I/O
––
––
20
1A3-I/O
2
1B3-I/O
––
––
19
1A2-I/O
1
1B2-I/O
––
––
18
1A1-I/O
0
1B1-I/O
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3.3-V ABT SCAN TEST DEVICES
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SCBS312C – MARCH 1994 – REVISED JUNE 1997
boundary-control register
The boundary-control register (BCR) is three bits long. The BCR is used in the context of the RUNT instruction
to implement additional test operations not included in the basic SCOPE instruction set. Such operations include
PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that are decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in Figure 4.
TDI
Bit 2
(MSB)
Bit 1
Bit 0
(LSB)
TDO
Figure 4. Boundary-Control Register Order of Scan
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
reducing the number of bits per test pattern that must be applied to complete a test operation. During
Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 5.
TDI
Bit 0
TDO
Figure 5. Bypass Register Order of Scan
12
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3.3-V ABT SCAN TEST DEVICES
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SCBS312C – MARCH 1994 – REVISED JUNE 1997
device-identification register
The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer,
part number, and version of this device.
For the ’LVTH18652A, the binary value 00100000000000011111000000101111 (2001F02F, hex) is captured
(during Capture-DR state) in the device-identification register to identify this device as TI SN54/74LVTH18652A.
For the ’LVTH182652A, the binary value 00100000000000100100000000101111 (2002402F, hex) is captured
(during Capture-DR state) in the device-identification register to identify this device as TI
SN54/74LVTH182652A.
The device-identification register order of scan is from TDI through bits 31–0 to TDO. Table 2 shows the
device-identification register bits and their significance.
Table 2. Device-Identification Register Configuration
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
31
VERSION3
27
PARTNUMBER15
11
30
VERSION2
26
PARTNUMBER14
10
MANUFACTURER10†
MANUFACTURER09†
29
VERSION1
25
PARTNUMBER13
9
28
VERSION0
24
PARTNUMBER12
8
––
––
23
PARTNUMBER11
7
––
––
22
PARTNUMBER10
6
––
––
21
PARTNUMBER09
5
––
––
20
PARTNUMBER08
4
––
––
19
PARTNUMBER07
3
––
––
18
PARTNUMBER06
2
––
––
17
PARTNUMBER05
1
––
––
16
PARTNUMBER04
0
MANUFACTURER00†
LOGIC1†
––
––
15
PARTNUMBER03
––
––
––
––
14
PARTNUMBER02
––
––
––
––
13
PARTNUMBER01
––
––
––
––
12
PARTNUMBER00
––
MANUFACTURER08†
MANUFACTURER07†
MANUFACTURER06†
MANUFACTURER05†
MANUFACTURER04†
MANUFACTURER03†
MANUFACTURER02†
MANUFACTURER01†
––
† Note that for TI products, bits 11– 0 of the device-identification register always contain the binary value 000000101111
(02F, hex).
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3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
instruction-register opcode description
The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of
each instruction.
Table 3. Instruction-Register Opcodes
BINARY CODE†
BIT 7 → BIT 0
MSB → LSB
SCOPE OPCODE
DESCRIPTION
SELECTED
DATA REGISTER
MODE
00000000
EXTEST
Boundary scan
Boundary scan
Test
10000001
IDCODE
Identification read
Device identification
Normal
10000010
SAMPLE/PRELOAD
BYPASS‡
Sample boundary
Boundary scan
Normal
Bypass scan
Bypass
Normal
Bypass scan
Bypass
Normal
00000101
BYPASS‡
BYPASS‡
Bypass scan
Bypass
Normal
00000110
HIGHZ
Control boundary to high impedance
Bypass
Modified test
10000111
CLAMP
BYPASS‡
Control boundary to 1/0
Bypass
Test
10001000
Bypass scan
Bypass
Normal
00001001
RUNT
Boundary run test
Bypass
Test
00001010
READBN
Boundary read
Boundary scan
Normal
10001011
READBT
Boundary read
Boundary scan
Test
00001100
CELLTST
Boundary self test
Boundary scan
Normal
10001101
TOPHIP
Boundary toggle outputs
Bypass
Test
10001110
SCANCN
Boundary-control register scan
Boundary control
Normal
00001111
SCANCT
Boundary-control register scan
Boundary control
Test
All others
BYPASS
Bypass scan
Bypass
Normal
00000011
10000100
† Bit 7 is used to maintain even parity in the 8-bit instruction.
‡ The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’LVTH18652 or ’LVTH182652.
boundary scan
This instruction conforms to the IEEE Std 1149.1-1990 EXTEST instruction. The BSR is selected in the scan
path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has been
scanned into the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at the device
pins, except for output enables, is passed through the BSCs to the normal on-chip logic. For I/O pins, the
operation of a pin as input or output is determined by the contents of the output-enable BSCs (bits 47–44 of the
BSR). When a given output enable is active (logic 0 for OEBA, logic 1 for OEAB), the associated I/O pins operate
in the output mode. Otherwise, the I/O pins operate in the input mode. The device operates in the test mode.
identification read
This instruction conforms to the IEEE Std 1149.1-1990 IDCODE instruction. The device identification register
is selected in the scan path. The device operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Std 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is selected
in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured in the
associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs
associated with I/O pins in the output mode. The device operates in the normal mode.
14
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SCBS312C – MARCH 1994 – REVISED JUNE 1997
bypass scan
This instruction conforms to the IEEE Std 1149.1-1990 BYPASS instruction. The bypass register is selected in
the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the
normal mode.
control boundary to high impedance
This instruction conforms to the IEEE Std 1149.1a-1993 HIGHZ instruction. The bypass register is selected in
the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a
modified test mode in which all device I/O pins are placed in the high-impedance state, the device input pins
remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Std 1149.1a-1993 CLAMP instruction. The bypass register is selected in
the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the I/O BSCs for
pins in the output mode is applied to the device I/O pins. The device operates in the test mode.
boundary-run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising
edge of TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device
I/O pins on each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data
appearing at the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the
test mode.
boundary-control-register scan
The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to
be executed.
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3.3-V ABT SCAN TEST DEVICES
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SCBS312C – MARCH 1994 – REVISED JUNE 1997
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2 → BIT 0
MSB → LSB
DESCRIPTION
X00
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudo-random pattern generation/36-bit mode (PRPG)
X10
Parallel-signature analysis/36-bit mode (PSA)
011
Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)
While the control input BSCs (bits 47–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
the output-enable BSCs (bits 47–44 of the BSR) control the drive state (active or high impedance) of the selected
device output pins. These BCR instructions are only valid when both bytes of the device are operating in one
direction of data flow (that is, 1OEAB = 1OEBA and 2OEAB = 2OEBA) and in the same direction of data flow
(that is, 1OEAB = 2OEAB and 1OEBA = 2OEBA). Otherwise, the bypass instruction is operated.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the
associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode
BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated
device I/O pins on each falling edge of TCK.
16
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pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each
falling edge of TCK. Figures 6 and 7 illustrate the 36-bit linear-feedback shift-register algorithms through which
the patterns are generated. An initial seed value should be scanned into the BSR prior to performing this
operation. A seed value of all zeroes does not produce additional patterns.
2A9-I/O
2A8-I/O
2A7-I/O
2A6-I/O
2A5-I/O
2A4-I/O
2A3-I/O
2A2-I/O
2A1-I/O
1A9-I/O
1A8-I/O
1A7-I/O
1A6-I/O
1A5-I/O
1A4-I/O
1A3-I/O
1A2-I/O
1A1-I/O
2B9-I/O
2B8-I/O
2B7-I/O
2B6-I/O
2B5-I/O
2B4-I/O
2B3-I/O
2B2-I/O
2B1-I/O
1B9-I/O
1B8-I/O
1B7-I/O
1B6-I/O
1B5-I/O
1B4-I/O
1B3-I/O
1B2-I/O
1B1-I/O
=
Figure 6. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 1)
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2B9-I/O
2B8-I/O
2B7-I/O
2B6-I/O
2B5-I/O
2B4-I/O
2B3-I/O
2B2-I/O
2B1-I/O
1B9-I/O
1B8-I/O
1B7-I/O
1B6-I/O
1B5-I/O
1B4-I/O
1B3-I/O
1B2-I/O
1B1-I/O
2A9-I/O
2A8-I/O
2A7-I/O
2A6-I/O
2A5-I/O
2A4-I/O
2A3-I/O
2A2-I/O
2A1-I/O
1A9-I/O
1A8-I/O
1A7-I/O
1A6-I/O
1A5-I/O
1A4-I/O
1A3-I/O
1A2-I/O
1A1-I/O
=
Figure 7. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 0)
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SCBS312C – MARCH 1994 – REVISED JUNE 1997
parallel-signature analysis (PSA)
Data appearing at the selected device input-mode I/O pins is compressed into a 36-bit parallel signature in the
shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the
selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 8 and 9
illustrate the 36-bit linear-feedback shift-register algorithms through which the signature is generated. An initial
seed value should be scanned into the BSR before performing this operation.
2A9-I/O
2A8-I/O
2A7-I/O
2A6-I/O
2A5-I/O
2A4-I/O
2A3-I/O
2A2-I/O
2A1-I/O
1A9-I/O
1A8-I/O
1A7-I/O
1A6-I/O
1A5-I/O
1A4-I/O
1A3-I/O
1A2-I/O
1A1-I/O
2B9-I/O
2B8-I/O
2B7-I/O
2B6-I/O
2B5-I/O
2B4-I/O
2B3-I/O
2B2-I/O
2B1-I/O
1B9-I/O
1B8-I/O
1B7-I/O
1B6-I/O
1B5-I/O
1B4-I/O
1B3-I/O
1B2-I/O
1B1-I/O
=
=
Figure 8. 36-Bit PSA Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 1)
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2B9-I/O
2B8-I/O
2B7-I/O
2B6-I/O
2B5-I/O
2B4-I/O
2B3-I/O
2B2-I/O
2B1-I/O
1B9-I/O
1B8-I/O
1B7-I/O
1B6-I/O
1B5-I/O
1B4-I/O
1B3-I/O
1B2-I/O
1B1-I/O
2A9-I/O
2A8-I/O
2A7-I/O
2A6-I/O
2A5-I/O
2A4-I/O
2A3-I/O
2A2-I/O
2A1-I/O
1A9-I/O
1A8-I/O
1A7-I/O
1A6-I/O
1A5-I/O
1A4-I/O
1A3-I/O
1A2-I/O
1A1-I/O
=
=
Figure 9. 36-Bit PSA Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 0)
20
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simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in
the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an
18-bit pseudo-random pattern is generated in the shift-register elements of the selected output-mode BSCs on
each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each
falling edge of TCK. Figures 10 and 11 illustrate the 18-bit linear-feedback shift-register algorithms through
which the signature and patterns are generated. An initial seed value should be scanned into the BSR before
performing this operation. A seed value of all zeroes does not produce additional patterns.
2A9-I/O
2A8-I/O
2A7-I/O
2A6-I/O
2A5-I/O
2A4-I/O
2A3-I/O
2A2-I/O
2A1-I/O
1A9-I/O
1A8-I/O
1A7-I/O
1A6-I/O
1A5-I/O
1A4-I/O
1A3-I/O
1A2-I/O
1A1-I/O
2B9-I/O
2B8-I/O
2B7-I/O
2B6-I/O
2B5-I/O
2B4-I/O
2B3-I/O
2B2-I/O
2B1-I/O
1B9-I/O
1B8-I/O
1B7-I/O
1B6-I/O
1B5-I/O
1B4-I/O
1B3-I/O
1B2-I/O
1B1-I/O
=
=
Figure 10. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 1)
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2B9-I/O
2B8-I/O
2B7-I/O
2B6-I/O
2B5-I/O
2B4-I/O
2B3-I/O
2B2-I/O
2B1-I/O
1B9-I/O
1B8-I/O
1B7-I/O
1B6-I/O
1B5-I/O
1B4-I/O
1B3-I/O
1B2-I/O
1B1-I/O
2A9-I/O
2A8-I/O
2A7-I/O
2A6-I/O
2A5-I/O
2A4-I/O
2A3-I/O
2A2-I/O
2A1-I/O
1A9-I/O
1A8-I/O
1A7-I/O
1A6-I/O
1A5-I/O
1A4-I/O
1A3-I/O
1A2-I/O
1A1-I/O
=
=
Figure 11. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 0)
22
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SCBS312C – MARCH 1994 – REVISED JUNE 1997
simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in
the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an
18-bit binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on
each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each
falling edge of TCK. Figures 12 and 13 illustrate the 18-bit linear-feedback shift-register algorithms through
which the signature is generated. An initial seed value should be scanned into the BSR before performing
this operation.
2A9-I/O
2A8-I/O
2A7-I/O
2A6-I/O
2A5-I/O
2A4-I/O
2A3-I/O
2A2-I/O
2A1-I/O
1A9-I/O
1A8-I/O
1A7-I/O
1A6-I/O
1A5-I/O
1A4-I/O
1A3-I/O
1A2-I/O
1A1-I/O
2B8-I/O
2B7-I/O
2B6-I/O
2B5-I/O
2B4-I/O
2B3-I/O
2B2-I/O
2B1-I/O
MSB
2B9-I/O
LSB
=
=
1B9-I/O
1B8-I/O
1B7-I/O
1B6-I/O
1B5-I/O
1B4-I/O
1B3-I/O
1B2-I/O
1B1-I/O
Figure 12. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 1)
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23
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
2B9-I/O
2B8-I/O
2B7-I/O
2B6-I/O
2B5-I/O
2B4-I/O
2B3-I/O
2B2-I/O
2B1-I/O
1B9-I/O
1B8-I/O
1B7-I/O
1B6-I/O
1B5-I/O
1B4-I/O
1B3-I/O
1B2-I/O
1B1-I/O
2A8-I/O
2A7-I/O
2A6-I/O
2A5-I/O
2A4-I/O
2A3-I/O
2A2-I/O
2A1-I/O
MSB
2A9-I/O
LSB
=
=
1A9-I/O
1A8-I/O
1A7-I/O
1A6-I/O
1A5-I/O
1A4-I/O
1A3-I/O
1A2-I/O
1A1-I/O
Figure 13. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 0)
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
timing description
All test operations of the ’LVTH18652A and ’LVTH182652A are synchronous to the TCK signal. Data on the TDI,
TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and
normal-function output pins on the falling edge of TCK. The TAP controller is advanced through its states (as
shown in Figure 2) by changing the value of TMS on the falling edge of TCK and then applying a rising edge
to TCK.
A simple timing example is shown in Figure 14. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan
and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO
is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5 explains
the operation of the test circuitry during each TCK cycle.
Table 5. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
1
Test-Logic-Reset
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
2
Run-Test/Idle
3
Select-DR-Scan
4
Select-IR-Scan
5
Capture-IR
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.
6
Shift-IR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
Shift-IR
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next
TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.
14
Exit1-IR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
15
Update-IR
16
Select-DR-Scan
17
Capture-DR
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.
18
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
19–20
Shift-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
21
Exit1-DR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
22
Update-DR
23
Select-DR-Scan
7–13
24
Select-IR-Scan
25
Test-Logic-Reset
The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
In general, the selected data register is updated with the new data on the falling edge of TCK.
Test operation completed
POST OFFICE BOX 655303
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25
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Test-Logic-Reset
Select-IR-Scan
Update-DR
Exit1-DR
Capture-DR
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Select-DR-Scan
ÎÎ
ÎÎ
Select-DR-Scan
Shift-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
TAP
Controller
State
Test-Logic-Reset
TDO
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Update-IR
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TDI
Exit1-IR
TMS
Shift-DR
TCK
3-State (TDO) or Don’t Care (TDI)
Figure 14. Timing Example
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO (see Note 1) . . . . . . . . . –0.5 V to 7 V
Current into any output in the low state, IO: SN54LVTH18652A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN54LVTH182652A (A port or TDO) . . . . . . . . . . . . . . . . 96 mA
SN54LVTH182652A (B port) . . . . . . . . . . . . . . . . . . . . . . . 30 mA
SN74LVTH18652A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
SN74LVTH182652A (A port or TDO) . . . . . . . . . . . . . . . 128 mA
SN74LVTH182652A (B port) . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Current into any output in the high state, IO (see Note 2): SN54LVTH18652A . . . . . . . . . . . . . . . . . . . . 48 mA
SN54LVTH182652A (A port or TDO) . . . . 48 mA
SN54LVTH182652A (B port) . . . . . . . . . . . 30 mA
SN74LVTH18652A . . . . . . . . . . . . . . . . . . . . 64 mA
SN74LVTH182652A (A port or TDO) . . . . 64 mA
SN74LVTH182652A (B port) . . . . . . . . . . . 30 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 3): PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
recommended operating conditions
SN54LVTH18652A
SN74LVTH18652A
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0.8
0.8
Input voltage
5.5
5.5
V
IOH
IOL
IOL†
High-level output current
–24
–32
mA
Low-level output current
24
32
mA
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
85
°C
High-level input voltage
2
Outputs enabled
TA
Operating free-air temperature
† Current duty cycle ≤ 50%, f ≥ 1 kHz
–55
2
125
–40
V
V
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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27
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 2.7 V,
II = –18 mA
VCC = MIN to MAX‡, IOH = –100 µA
VCC = 2.7 V,
IOH = –3 mA
IOH = –8 mA
VCC = 3 V
IOH = –24 mA
IOH = –32 mA
VOH
VCC = 2
2.7
7V
VOL
VCC = 3 V
–1.2
2.4
2.4
2
0.2
0.5
IOL = 16 mA
IOL = 32 mA
0.4
0.4
0.5
0.5
IOL = 48 mA
IOL = 64 mA
0.55
CLK S
CLK,
S, TCK
OEAB
±1
±1
10
10
50
50
1
1
–25
–100
–25
–100
25
150
25
150
25
100
25
100
A or B ports§
VI = 0
VI or VO = 0 to 4.5 V
–5
–5
20
20
1
1
–5
–5
±100
150
500
75
150
500
–75
–150
–500
–75
–150
–500
µA
µA
µA
II(hold)¶
VCC = 3 V
IOZH
IOZL
VCC = 3.6 V,
VCC = 3.6 V,
VO = 3 V
VO = 0.5 V
TDO
1
1
µA
TDO
–1
–1
µA
IOZPU
IOZPD
VCC = 0 to 1.5 V,
VCC = 1.5 V to 0,
VO = 0.5 V or 3 V
VO = 0.5 V or 3 V
TDO
±50
±50
µA
TDO
±50
±50
µA
ICC
VCC = 3.6 V, IO = 0,
VI = VCC or GND
A or B ports
75
µA
VI = 0.8 V
VI = 2 V
Outputs high
0.6
2
0.6
2
Outputs low
18.5
24
18.5
24
0.6
2
0.6
2
Outputs
disabled
∆ICC#
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
Cio
0.5
Co
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.5
µA
mA
mA
4
4
pF
10
10
pF
8
pF
VO = 3 V or 0
8
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ Unused pins at VCC or GND
¶ The parameter II(hold) includes the off-state output leakage current.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
28
V
0.55
OEBA, TDI
OEBA
TDI,
TMS
VI = VCC
VI = 0
V
V
0.5
VI = 5.5 V
VI = VCC
VCC = 0,
VCC–0.2
2.4
UNIT
2
VI = 0
VI = 5.5 V
VCC = 3.6 V
–1.2
VCC–0.2
2.4
0.2
VI = 5.5 V
VI = VCC
II
SN74LVTH18652A
MIN TYP†
MAX
IOL = 100 µA
IOL = 24 mA
VCC = 3.6 V, VI = VCC or GND
VCC = 0 or MAX‡, VI = 5.5 V
Ioff
SN54LVTH18652A
MIN TYP†
MAX
TEST CONDITIONS
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (normal mode) (see Figure 15)12
SN54LVTH18652A
VCC = 3.3 V
± 0.3 V
fclock
tw
SN74LVTH18652A
VCC = 2.7 V
MIN
MAX
MIN
MAX
0
120
0
100
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
MAX
MIN
MAX
0
120
0
100
UNIT
Clock frequency
CLKAB or CLKBA
Pulse duration
CLKAB or CLKBA high or low
3.8
5
3.8
5
MHz
ns
tsu
Setup time
A before CLKAB↑ or
B before CLKBA↑
2.9
3.1
2.9
3.1
ns
th
Hold time
A after CLKAB↑ or
B after CLKBA↑
0.8
0.2
0.8
0.2
ns
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (test mode) (see Figure 15)
SN54LVTH18652A
VCC = 3.3 V
± 0.3 V
fclock
tw
tsu
th
td
tr
MIN
MAX
0
50
SN74LVTH18652A
VCC = 2.7 V
MIN
MAX
0
40
VCC = 3.3 V
± 0.3 V
MIN
MAX
0
50
VCC = 2.7 V
MIN
MAX
0
40
UNIT
Clock frequency
TCK
Pulse duration
TCK high or low
9.5
10.5
9.5
10.5
A, B, CLK, OEAB, OEBA or S
before TCK↑
6.5
7
6.5
7
TDI before TCK↑
2.5
3.5
2.5
3.5
TMS before TCK↑
2.5
3.5
2.5
3.5
A, B, CLK, OEAB, OEBA or S
after TCK↑
1.5
1
1.5
1
TDI after TCK↑
1.5
1
1.5
1
TMS after TCK↑
1.5
1
1.5
1
Delay time
Power up to TCK↑
50
50
50
50
ns
Rise time
VCC power up
1
1
1
1
µs
S t time
Setup
ti
H ld time
ti
Hold
MHz
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (normal mode) (see Figure 15)1
SN54LVTH18652A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
CLKAB or CLKBA
MAX
100
A or B
B or A
CLKAB or CLKBA
B or A
SAB or SBA
B or A
OEAB or OEBA
B or A
OEAB or OEBA
B or A
SN74LVTH18652A
VCC = 2.7 V
MIN
MAX
120
VCC = 3.3 V
± 0.3 V
MIN
MAX
100
VCC = 2.7 V
MIN
UNIT
MAX
120
MHz
1.5
5
5.4
1.5
4.7
5.2
1.5
5
5.4
1.5
4.7
5.2
1.5
6.9
7.5
1.5
6.5
7.1
1.5
6.9
7.5
1.5
6.5
7.1
1.5
7.9
8.7
1.5
7.5
8.4
1.5
7.9
8.7
1.5
7.5
8.4
1.5
7.5
8
1.5
7.1
7.5
1.5
7.5
8
1.5
7.1
7.5
2
8.8
9.5
2
8.3
9
2
7.6
8.4
2
7
7.7
ns
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (test mode) (see Figure 15)
SN54LVTH18652A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
TCK
MAX
50
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
VCC = 2.7 V
MIN
MAX
MIN
40
MAX
50
VCC = 2.7 V
MIN
40
MHz
15
18
2.5
14
17
2.5
15
18
2.5
14
17
1
6
7
1
5.5
6.5
1.5
7
8
1.5
6.5
7.5
4
18
21
4
17
20
4
18
21
4
17
20
1
6
7
1
5.5
6.5
1.5
6
7
1.5
5.5
6.5
4
19
21
4
18
20
4
18
19.5
4
17
18.5
1.5
7.5
9
1.5
7
8.5
1.5
7.5
8.5
1.5
7
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
2.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
30
SN74LVTH18652A
VCC = 3.3 V
± 0.3 V
ns
ns
ns
ns
ns
ns
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
recommended operating conditions
SN54LVTH182652A
SN74LVTH182652A
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0.8
0.8
V
Input voltage
5.5
5.5
V
A port, TDO
–24
–32
B port
–12
–12
A port, TDO
24
32
B port
12
12
High-level input voltage
2
2
V
V
IOH
High level output current
High-level
IOL
Low level output current
Low-level
IOL†
∆t/∆v
Low-level output current
A port, TDO
48
64
mA
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
85
°C
TA
Operating free-air temperature
† Current duty cycle ≤ 50%, f ≥ 1 kHz
–55
125
–40
mA
mA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 2.7 V,
II = –18 mA
VCC = MIN to MAX‡, IOH = –100 µA
VCC = 2.7 V,
VOH
VCC = 3 V
7V
VCC = 2
2.7
VOL
VCC = 3 V
IOH = –3 mA
IOH = –8 mA
IOH = –12 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 48 mA
VCC = 3.6 V,
VCC = 0 or MAX‡,
VI = VCC or GND
VI = 5.5 V
VI = 5.5 V
VI = VCC
A port, TDO
VCC = 3.6 V
VI = VCC
VI = 0
VI = 5.5 V
VI = VCC
VCC = 0,
–1.2
VCC–0.2
2.4
VCC–0.2
2.4
2.4
2.4
V
2
B port
2
2
A port,
port TDO
0.2
0.2
0.5
0.5
0.4
0.4
0.5
0.5
V
0.55
0.55
B port
0.8
CLK S,
CLK,
S TCK
OEAB, TDI
OEAB
TDI,
TMS
OEAB
0.8
±1
±1
10
10
50
50
1
1
–25
–100
–25
–100
25
150
25
150
25
100
25
100
–5
–25
–5
20
A or B ports§
VI = 0
VI or VO = 0 to 4.5 V
µA
20
1
1
–5
–5
±100
II(hold)¶
VCC = 3 V
IOZH
IOZL
VCC = 3.6 V,
VCC = 3.6 V,
VO = 3 V
VO = 0.5 V
TDO
1
1
µA
TDO
–1
–1
µA
IOZPU
IOZPD
VCC = 0 to 1.5 V,
VCC = 1.5 V to 0,
VO = 0.5 V or 3 V
VO = 0.5 V or 3 V
TDO
±50
±50
µA
±50
µA
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
Outputs high
0.6
2
0.6
2
Outputs low
18.5
24
18.5
24
0.6
2
0.6
2
∆ICC#
A or B ports
75
150
500
75
150
500
–75
–150
–500
–75
–150
–500
µA
VI = 0.8 V
VI = 2 V
ICC
±50
TDO
Outputs disabled
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
0.5
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ Unused pins at VCC or GND
¶ The parameter II(hold) includes the off-state ouput leakage current.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
32
UNIT
V
2
VI = 0
VI = 5.5 V
II
SN74LVTH182652A
MIN TYP†
MAX
–1.2
IOH = –24 mA
IOH = –32 mA
IOL = 64 mA
IOL = 12 mA
Ioff
SN54LVTH182652A
MIN TYP†
MAX
TEST CONDITIONS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.5
µA
mA
mA
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
Ci
Cio
SN54LVTH182652A
MIN TYP†
MAX
TEST CONDITIONS
VI = 3 V or 0
VO = 3 V or 0
Co
VO = 3 V or 0
† All typical values are at VCC = 3.3 V, TA = 25°C.
SN74LVTH182652A
MIN TYP†
MAX
UNIT
4
4
pF
10
10
pF
8
8
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (normal mode) (see Figure 15)
SN54LVTH182652A
VCC = 3.3 V
± 0.3 V
fclock
tw
SN74LVTH182652A
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
0
120
0
100
0
120
0
100
UNIT
Clock frequency
CLKAB or CLKBA
MHz
Pulse duration
CLKAB or CLKBA high or low
3.8
5
3.8
5
ns
tsu
Setup time
A before CLKAB↑ or
B before CLKBA↑
2.9
3.1
2.9
3.1
ns
th
Hold time
A after CLKAB↑ or
B after CLKBA↑
0.8
0.2
0.8
0.2
ns
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (test mode) (see Figure 15)
SN54LVTH182652A
VCC = 3.3 V
± 0.3 V
fclock
tw
tsu
th
td
tr
MIN
MAX
0
50
SN74LVTH182652A
VCC = 2.7 V
MIN
MAX
0
40
VCC = 3.3 V
± 0.3 V
MIN
MAX
0
50
VCC = 2.7 V
MIN
MAX
0
40
UNIT
Clock frequency
TCK
Pulse duration
TCK high or low
9.5
10.5
9.5
10.5
A, B, CLK, OEAB, OEBA or S
before TCK↑
6.5
7
6.5
7
TDI before TCK↑
2.5
3.5
2.5
3.5
TMS before TCK↑
2.5
3.5
2.5
3.5
A, B, CLK, OEAB, OEBA or S
after TCK↑
1.5
1
1.5
1
TDI after TCK↑
1.5
1
1.5
1
TMS after TCK↑
1.5
1
1.5
1
Delay time
Power up to TCK↑
50
50
50
50
ns
Rise time
VCC power up
1
1
1
1
µs
S t time
Setup
ti
H ld time
Hold
ti
MHz
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (normal mode) (see Figure 15)1
SN54LVTH182652A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
CLKAB or CLKBA
MAX
120
B
A
A
B
CLKBA
A
CLKAB
B
SBA
A
SAB
B
OEAB or OEBA
B or A
OEAB or OEBA
B or A
SN74LVTH182652A
VCC = 2.7 V
MIN
MAX
100
VCC = 3.3 V
± 0.3 V
MIN
MAX
120
VCC = 2.7 V
MIN
UNIT
MAX
100
MHz
1.5
5
5.4
1.5
4.7
5.2
1.5
5
5.4
1.5
4.7
5.2
1.5
5.9
6.5
1.5
5.6
6.2
1.5
5.9
6.5
1.5
5.6
6.2
1.5
6.9
7.5
1.5
6.5
7.1
1.5
6.9
7.5
1.5
6.5
7.1
1.5
7.8
8.7
1.5
7.3
8.2
1.5
7.8
8.7
1.5
7.3
8.2
1.5
7.9
8.7
1.5
7.5
8.4
1.5
7.9
8.7
1.5
7.5
8.4
1.5
8.5
9.2
1.5
8
8.8
1.5
8.5
9.2
1.5
8
8.8
1.5
7.9
8.6
1.5
7.4
8.1
1.5
7.9
8.6
1.5
7.4
8.1
2
8.8
9.5
2
8.3
9
2
7.6
8.4
2
7
7.7
ns
ns
ns
ns
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (test mode) (see Figure 15)
SN54LVTH182652A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
TCK
MAX
50
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
VCC = 2.7 V
MIN
MAX
MIN
40
MAX
50
VCC = 2.7 V
MIN
40
MHz
15
18
2.5
14
17
2.5
15
18
2.5
14
17
1
6
7
1
5.5
6.5
1.5
7
8
1.5
6.5
7.5
4
18
21
4
17
20
4
18
21
4
17
20
1
6
7
1
5.5
6.5
1.5
6
7
1.5
5.5
6.5
4
19
21
4
18
20
4
18
19.5
4
17
18.5
1.5
7.5
9
1.5
7
8.5
1.5
7.5
8.5
1.5
7
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
2.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
34
SN74LVTH182652A
VCC = 3.3 V
± 0.3 V
ns
ns
ns
ns
ns
ns
SN54LVTH18652A, SN54LVTH182652A, SN74LVTH18652A, SN74LVTH182652A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT TRANSCEIVERS AND REGISTERS
SCBS312C – MARCH 1994 – REVISED JUNE 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
6V
Open
S1
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
1.5 V
Timing Input
0V
tw
tsu
2.7 V
1.5 V
Input
3V
1.5 V
0V
1.5 V
Data Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
1.5 V
1.5 V
0V
tPHL
tPLH
VOH
Output
1.5 V
1.5 V
VOL
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPLZ
tPZL
3V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
2.7 V
Output
Control
tPLH
tPHL
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
th
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 15. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
PACKAGE OPTION ADDENDUM
www.ti.com
2-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVTH182652APM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74LVTH18652APM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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