[AK4673] AK4673 Stereo CODEC with MIC/HP-AMP and Touch Screen Controller GENERAL DESCRIPTION The AK4673 is a stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Touch Screen Controller (TSC) which includes the SAR type ADC. The AK4673 features analog mixing circuits, PLL and a 4-wire resistive touch screen I/F that allows easy interfacing in mobile phone and portable A/V player designs. The AK4673 is available in a 57pin BGA package, utilizing less board space than competitive offerings. FEATURES 1. Recording Function • 4 Stereo Input Selectors • Stereo Mic Input (Full-differential or Single-ended) • Stereo Line Input • MIC Amplifier (+32dB/+26dB/+20dB or 0dB) • Digital ALC (Automatic Level Control) (+36dB ∼ −54dB, 0.375dB Step, Mute) • ADC Performance: S/(N+D): 83dB DR, S/N: 86dB (MIC-Amp=+20dB) S/(N+D): 88dB DR, S/N: 95dB (MIC-Amp=0dB) • Wind-noise Reduction Filter • Stereo Separation Emphasis • Programmable EQ 2. Playback Function • Digital De-emphasis Filter (tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz) • Bass Boost • Soft Mute • Digital Volume (+12dB ∼ −115.0dB, 0.5dB Step, Mute) • Digital ALC (Automatic Level Control) (+36dB ∼ −54dB, 0.375dB Step, Mute) • Stereo Separation Emphasis • Programmable EQ • Stereo Line Output - Performance: S/(N+D): 88dB, S/N: 92dB • Stereo Headphone-Amp - S/(N+D): [email protected], S/N: 90dB - Output Power: 70mW@16Ω (HVDD=5V), 62mW@16Ω (HVDD=3.3V) - Pop Noise Free at Power ON/OFF • Analog Mixing: 4 Stereo Input 3. Power Management 4. Master Clock: (1) PLL Mode • Frequencies: - MCKI pin: 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz - LRCK pin: 1fs - BICK pin: 32fs or 64fs (2) External Clock Mode • Frequencies: 256fs, 512fs or 1024fs (MCKI pin) 5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs MS0670-E-00 2007/09 -1- [AK4673] 6. Sampling Rate: • PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz • PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz • PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz • PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz • EXT Master/Slave Mode: 7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs) 7. Master/Slave mode 8. Audio Interface Format: MSB First, 2’s complement • ADC: 16bit MSB justified, I2S, DSP Mode • DAC: 16bit MSB justified, 16bit LSB justified, 16-24bit I2S, DSP Mode 9. Touch Screen Control Function • 12-bit SAR type A/D Converter with S/H circuit • 4-wire Resistive Touch Screen Interface • Pen Pressure Measurement • Auto Power Down • Continuous Read Operation 10. μP I/F: I2C Bus (Ver 1.0, 400kHz Fast-Mode) 11. Ta = -30 ∼ 85°C 12. Power Supply: • AVDD (Analog): 2.6 ∼ 3.6V • DVDD (Digital): 2.6 ∼ 3.6V • HVDD (Headphone): 2.6 ∼ 5.25V • TVDD1 (Digital I/O): 2.5 ∼ 3.6V • TVDD2 (Digital I/O): 1.6 ∼ 3.6V • TSVDD (Touch Screen Controller): 2.5 ∼ 3.6V 13. Package: 57pin BGA (5mm x 5mm, 0.5mm pitch) MS0670-E-00 2007/09 -2- [AK4673] ■ Block Diagram XP YP XN PENIRQN YN TSVDD TVDD1 SCLT SDAT MPWR PMMP MPWR MIC Power Supply Control Register SAR A/D CADT CADA SCLA SDAA PMADL or PMADR RIN1 A/D MIC-Amp LIN2 External MIC I2CA PEN INTERRUPT PMADL or PMMICL LIN1 Internal MIC Touch Panel I/F HPF PDN Wind-Noise Stereo Reduction Separation ALC TVDD2 PMADR or PMMICR BICK RIN2 LRCK SDTO PMAINR2 LIN3/MIN Line In * RIN3 Line In RIN4 SDTI Audio I/F PMAINL2 LIN4 PMAINR3 PMAINR4 PMAINL3 PMAINL4 PMMIN PMLO PMDAC LOUT Stereo Line Out D/A Stereo DATT Bass ALC Separation SMUTE Boost HPF ROUT MCKO PMPLL PMHPL PLL * VCOC HPL Headphone MCKI PMHPR HPR MUTET HVDD VSS2 AVDD VSS1 VSS3 VCOM DVDD (VCOC and RIN3 pins are shared by the same pin.) Figure 1. Block Diagram MS0670-E-00 2007/09 -3- [AK4673] ■ Ordering Guide −30 ∼ +85°C 57pin BGA (0.5mm pitch) Evaluation board for AK4673 AK4673EG AKD4673 ■ Pin Layout 9 8 7 6 AK4673 5 Top View 4 3 2 1 A B C D E F G H J 9 NC MUTET HPL HVDD SCLT CADT NC MCKI NC 8 RIN4/IN4- NC HPR VSS2 SDAT PENIRQN NC MCKO NC 7 ROUT/LON LIN4/IN4+ NC TVDD1 6 LOUT/LOP MIN/LIN3 TVDD2 DVDD 5 NC RIN2/IN2- NC VSS3 4 TSVDD LIN2/IN2+ LRCK BICK 3 LIN1/IN1- NC NC SDTI SDTO 2 VCOM RIN1/IN1+ MPWR I2CA VCOC/ RIN3 NC PDN SCLA SDAA 1 NC VSS1 AVDD XP YP XN YN CADA NC A B C D E F G H J Top View MS0670-E-00 2007/09 -4- [AK4673] PIN/FUNCTION No. Pin Name A1 NC - C2 MPWR O A2 VCOM O B1 C1 VSS1 AVDD - VCOC O RIN3 I F2 NC - D2 I2CA I G2 PDN I H1 H2 CADA SCLA I I J1 NC - J2 H3 J3 H4 J4 SDAA SDTI SDTO LRCK BICK H5 NC - J6 DVDD - H7 NC - H6 TVDD2 - J7 TVDD1 - J8 NC - H9 MCKI I G8 NC - G9 NC - H8 MCKO O J9 NC - D8 D9 C8 C9 VSS2 HVDD HPR HPL O O B8 NC - B9 MUTET O E2 I/O I/O I O I/O I/O Function No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). MIC Power Supply Pin Common Voltage Output Pin, 0.45 x AVDD Bias voltage of ADC inputs and DAC outputs. Ground 1 Pin Analog Power Supply Pin, 2.6 ~ 3.6V Output Pin for Loop Filter of PLL Circuit (AIN3 bit = “0”: PLL is available.) This pin should be connected to VSS1 with one resistor and capacitor in series. Rch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available.) No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). I2C Control Mode Pin. This pin should be tied to AVDD. Power-Down Mode Pin (This pin is valid only for the Audio Block) “H”: Power-up, “L”: Power-down This pin does not apply to a power down and a reset for the TSC block and TSC related registers. Power-down on the TSC block is determined by the PD0 bit shown in Table 61. Audio Block I2C bus Slave Address (CADA) bit Select Pin Audio Block Control Data Clock Pin. No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Audio Block Control Data Input Pin. Audio Serial Data Input Pin Audio Serial Data Output Pin Input / Output Channel Clock Pin Audio Serial Data Clock Pin No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Digital Power Supply Pin, 2.6 ~ 3.6V No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Digital I/O Power Supply Pin (Audio Stream), 1.6 ~ 3.6V Digital I/O Power Supply Pin (uP I/F), 2.5 ~ 3.6V This pin should be connected to TSVDD pin. No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). External Master Clock Input Pin No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Master Clock Output Pin No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Ground 2 Pin Headphone Amp Power Supply Pin, 2.6 ~ 5.25V Rch Headphone-Amp Output Pin Lch Headphone-Amp Output Pin No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Mute Time Constant Control Pin Connected to VSS2 pin with a capacitor for mute time constant. MS0670-E-00 2007/09 -5- [AK4673] A9 NC - RIN4 IN4− LIN4 IN4+ ROUT LON LOUT LOP MIN LIN3 I I I I O O O O I I NC - A4 RIN2 IN2− LIN2 IN2+ LIN1 IN1− RIN1 IN1+ TSVDD I I I I I I I I - B3 NC - D1 XP I/O A8 B7 A7 A6 B6 A5 B5 B4 A3 B2 No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Rch Analog Input 4 Pin (L4DIF bit = “0”: Single-ended Input) Negative Line Input 4 Pin (L4DIF bit = “1”: Full-differential Input) Lch Analog Input 4 Pin (L4DIF bit = “0”: Single-ended Input) Positive Line Input 4 Pin (L4DIF bit = “1”: Full-differential Input) Rch Stereo Line Output Pin (LODIF bit = “0”: Single-ended Stereo Output) Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output) Lch Stereo Line Output Pin (LODIF bit = “0”: Single-ended Stereo Output) Positive Line Output Pin (LODIF bit = “1”: Full-differential Mono Output) Mono Signal Input Pin (AIN3 bit = “0”: PLL is available.) Lch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available.) No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input) Microphone Negative Input 2 Pin (MDIF2 bit = “1”: Full-differential Input) Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input) Microphone Positive Input 2 Pin (MDIF2 bit = “1”: Full-differential Input) Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input) Microphone Negative Input 1 Pin (MDIF1 bit = “1”: Full-differential Input) Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input) Microphone Positive Input 1 Pin (MDIF1 bit = “1”: Full-differential Input) TSC Power Supply Pin, 2.5 ~ 3.6V. This pin should be connected to TVDD1 pin. No Connection pin No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Touch Screen X+ plate Voltage supply X axis Measurement: Supplies the voltage to X+ position input of the touch panel. Y axis Measurement: This pin is used as the input for the A/D converter Pen Pressure Measurement: This pin is the input for the A/D converter at Z1 measurement. Pen Waiting State: Pulled up by an internal resistor (typ.10K ohm). Touch Screen Y+ plate Voltage supply E1 YP I/O X axis Measurement: This pin is used as the input for the A/D converter Y axis Measurement: Supplies the voltage to Y+ position input of the touch panel Pen Pressure Measurement: Supplies the voltage to Y+ position input of the touch panel. Pen Waiting State: OPEN state Touch Screen X- plate Voltage supply F1 XN I/O X axis Measurement: Supplies the voltage to X- position input of the touch panel Y axis Measurement: OPEN state Pen Pressure Measurement: Supplies the voltage to X- position input of the touch panel Pen Waiting State: OPEN state Touch Screen Y- plate Voltage supply G1 YN J5 VSS3 I/O X axis Measurement: OPEN state Y axis Measurement: Supplies the voltage to Y- position input of the touch panel Pen Pressure Measurement: This pin is the input for the A/D converter at Z2 measurement. Pen Waiting State: connected to VSS3. - Ground 3 Pin Pen Interrupt Output F8 PENIRQN O This pin is “L” during the pen down on pen interrupt enabled state otherwise this pin is “H”. This pin is “L” during the pen interrupt disabled regardless pen touch. F9 CADT I TSC block I2C bus Slave Address(CADT) bit Select Pin E8 SDAT I/O TSC block I2C serial data. E9 SCLT I TSC block I2C serial clock. No Connection pin C3 NC No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Note 1. All input pins except analog input pins (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3, RIN4, LIN4, XP, YP, XN and YN) should not be left floating. MS0670-E-00 2007/09 -6- [AK4673] ■ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name MPWR, VCOC/RIN3, HPR, HPL, MUTET, RIN4/IN4−, LIN4/IN4+, ROUT/LOP, LOUT/LON, MIN/LIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+, XP, YP, XN, YN, PENIRQN MCKO MCKI MS0670-E-00 Setting These pins should be open. This pin should be open. This pin should be connected to VSS2. 2007/09 -7- [AK4673] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=0V; Note 2) Parameter Power Supplies: Analog Digital Digital I/O1 Digital I/O2 Headphone-Amp TSC Input Current, Any Pin Except Supplies Analog Input Voltage (Note 3) Digital Input Voltage (Note 4) Digital Input Voltage (Note 5) TSC Input Voltage (Note 6) Touch panel Drive Current Ambient Temperature (powered applied) Storage Temperature Symbol AVDD DVDD TVDD1 TVDD2 HVDD TSVDD IIN VINA VIND1 VIND2 VIND3 IOUTDRV Ta Tstg min −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −30 −65 max 6.0 6.0 6.0 6.0 6.0 6.0 ±10 AVDD+0.3 TVDD1+0.3 TVDD2+0.3 TSVDD+0.3 50 85 150 Units V V V V V V mA V V V V mA °C °C Note 2. All voltages with respect to ground. Note 3. I2CA, RIN4/IN4−, LIN4/IN4+, MIN/LIN3, RIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ pins Note 4 PDN, CADA, SCLA, SDAA pins Pull-up resistors at SDAA and SCLA pins should be connected to (TVDD1+0.3) V or less voltage. Note 5. SDTI, LRCK, BICK, MCKI pins Note 6 XP, XN, YP, YN, CADT, SCLT, SDAT pins Pull-up resistors at SDAT and SCLT pins should be connected to (TSVDD+0.3) V or less voltage. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3=0V; Note 2) Parameter Symbol min typ Power Supplies Analog AVDD 2.6 3.3 (Note 7) Digital DVDD 2.6 3.3 Digital I/O1 TVDD1 2.5 3.3 Digital I/O2 TVDD2 1.6 3.3 HP-Amp HVDD 2.6 3.3 / 5.0 TSC TSVDD 2.5 3.3 max 3.6 3.6 DVDD DVDD 5.25 3.6 Units V V V V V V Note 2. All voltages with respect to ground. Note 7. The power-up sequence among AVDD, DVDD, TVDD1, TVDD2, HVDD and TSVDD is not critical. The PDN pin should be held to “L” when power-up. The PDN pin should be set to “H” after all power supplies are powered-up. The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output. When one of power supplies is partially powered OFF, the power supply current at power-down mode may be increased. All the power supplies should be powered OFF when the power supply is powered OFF. * AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. * SDAA and SDAT are written as SDA, and also SCLA and SCLT are written as SCL unless otherwise specified in this datasheet. MS0670-E-00 2007/09 -8- [AK4673] ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=TVDD1=TVDD2=HVDD=TSVDD=3.3V; VSS1=VSS2=VSS3=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) min typ max Units Parameter MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”); MDIF1=MDIF2 bits = “0” (Single-ended inputs) Input MGAIN1-0 bits = “00” 40 60 80 kΩ Resistance MGAIN1-0 bits = “01”, “10”or “11” 20 30 40 kΩ MGAIN1-0 bits = “00” 0 dB MGAIN1-0 bits = “01” +20 dB Gain MGAIN1-0 bits = “10” +26 dB MGAIN1-0 bits = “11” +32 dB MIC Amplifier: IN1+/IN1−/IN2+/IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input) Input Voltage (Note 8) MGAIN1-0 bits = “01” 0.228 Vpp MGAIN1-0 bits = “10” 0.114 Vpp MGAIN1-0 bits = “11” 0.057 Vpp MIC Power Supply: MPWR pin Output Voltage (Note 9) 2.22 2.47 2.72 V Load Resistance 0.5 kΩ Load Capacitance 30 pF ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”) → ADC → IVOL, IVOL=0dB, ALC=OFF Resolution 16 Bits (Note 11) 0.168 0.198 0.228 Vpp Input Voltage (Note 10) 1.68 1.98 2.28 Vpp (Note 12) (Note 11, LIN1/RIN1/LIN2/RIN2) 71 83 dBFS S/(N+D) (Note 11, LIN3/RIN3/LIN4/RIN4) 83 dBFS (−1dBFS) (Note 12, except for LIN3/RIN3) 88 dBFS (Note 12, LIN3/RIN3) 72 dBFS (Note 11) 76 86 dB D-Range (−60dBFS, A-weighted) 95 dB (Note 12) (Note 11) 76 86 dB S/N (A-weighted) 95 dB (Note 12) (Note 11) 75 90 dB Interchannel Isolation 100 dB (Note 12) (Note 11) 0.1 0.8 dB Interchannel Gain Mismatch 0.1 0.8 dB (Note 12) Note 8. The voltage difference between IN1/2+ and IN1/2− pins. AC coupling capacitor should be inserted in series at each input pin. Full-differential mic input is not available at MGAIN1-0 bits = “00”. Maximum input voltage of IN1+, IN1−, IN2+ and IN2− pins is proportional to AVDD voltage, respectively. Vin = 0.069 x AVDD (max)@MGAIN1-0 bits = “01”, 0.035 x AVDD (max)@MGAIN1-0 bits = “10”, 0.017 x AVDD (max)@MGAIN1-0 bits = “11”. When the signal larger than above value is input to IN1+, IN1−, IN2+ or IN2− pin, ADC does not operate normally. Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ) Note 10. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)@MGAIN1-0 bits = “01” (+20dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = “00” (0dB) Note 11. MGAIN1-0 bits = “01” (+20dB) Note 12. MGAIN1-0 bits = “00” (0dB) MS0670-E-00 2007/09 -9- [AK4673] min typ max Units Parameter DAC Characteristics: Resolution 16 Bits Stereo Line Output Characteristics: DAC → LOUT/ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”, LODIF bit = “0”, RL=10kΩ (Single-ended) Output Voltage (Note 13) LOVL bit = “0” 1.78 1.98 2.18 Vpp LOVL bit = “1” 2.25 2.50 2.75 Vpp 78 88 dBFS S/(N+D) (−3dBFS) S/N (A-weighted) 82 92 dB Interchannel Isolation 80 100 dB Interchannel Gain Mismatch 0.1 0.5 dB Load Resistance 10 kΩ Load Capacitance 30 pF Mono Line Output Characteristics: DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”, LODIF bit = “1”, RL=10kΩ for each pin (Full-differential) Output Voltage (Note 14) LOVL bit = “0” 3.52 3.96 4.36 Vpp LOVL bit = “1” 5.00 Vpp 78 88 dBFS S/(N+D) (−3dBFS) S/N (A-weighted) 85 95 dB Load Resistance (LOP/LON pins, respectively) 10 kΩ Load Capacitance (LOP/LON pins, respectively) 30 pF Note 13. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)@LOVL bit = “0”. Note 14. Output voltage is proportional to AVDD voltage. Vout = (LOP) − (LON) = 1.2 x AVDD (typ)@LOVL bit = “0”. MS0670-E-00 2007/09 - 10 - [AK4673] min typ max Units Parameter Headphone-Amp Characteristics: DAC → HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB, VBAT bit = “0”; unless otherwise specified. Output Voltage (Note 15) 1.58 1.98 2.38 Vpp HPG bit = “0”, 0dBFS, HVDD=3.3V, RL=22.8Ω 2.40 3.00 3.60 Vpp HPG bit = “1”, 0dBFS, HVDD=5V, RL=100Ω HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) 1.0 Vrms HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW) 1.06 Vrms S/(N+D) 60 70 dBFS HPG bit = “0”, −3dBFS, HVDD=3.3V, RL=22.8Ω 80 dBFS HPG bit = “1”, −3dBFS, HVDD=5V, RL=100Ω HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) 20 dBFS HPG bit = “1”, 0dBFS, HVDD=5V, RL=16Ω (Po=70mW) 70 dBFS (Note 16) 80 90 dB S/N (A-weighted) 90 dB (Note 17) (Note 16) 65 75 dB Interchannel Isolation 80 dB (Note 17) (Note 16) 0.1 0.8 dB Interchannel Gain Mismatch 0.1 0.8 dB (Note 17) Load Resistance 16 Ω C1 in Figure 2 30 pF Load Capacitance 300 pF C2 in Figure 2 Note 15. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD(typ)@HPG bit = “0”, 0.91 x AVDD(typ)@HPG bit = “1”. Note 16. HPG bit = “0”, HVDD=3.3V, RL=22.8Ω. Note 17. HPG bit = “1”, HVDD=5V, RL=100Ω. HP-Amp HPL/HPR pin Measurement Point 47μF 6.8Ω C1 0.22μF C2 16Ω 10Ω Figure 2. Headphone-Amp output circuit MS0670-E-00 2007/09 - 11 - [AK4673] min typ Parameter Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20kΩ) Maximum Input Voltage (Note 18) 1.98 Gain (Note 19) MIN Æ LOUT/ROUT LOVL bit = “0” 0 −4.5 LOVL bit = “1” +2 MIN Æ HPL/HPR HPG bit = “0” −24.5 −20 HPG bit = “1” −16.4 Stereo Input: LIN2/RIN2/LIN4/RIN4 pins; LIN3/RIN3 pins (AIN3 bit = “1”) Maximum Input Voltage (Note 20) 1.98 Gain LIN/RIN Æ LOUT/ROUT LOVL bit = “0” 0 −4.5 LOVL bit = “1” +2 LIN/RIN Æ HPL/HPR HPG bit = “0” 0 −4.5 HPG bit = “1” +3.6 Full-differential Mono Input: IN4+/− pins (L4DIF bit = “1”) Maximum Input Voltage (Note 21) 3.96 Gain LOVL bit = “0” IN4+/− Æ LOUT/ROUT −10.5 −6 (LODIF bit = “0”) LOVL bit = “1” −4 LOVL bit = “0” 0 IN4+/− Æ LOP/LON −4.5 (LODIF bit = “1”) (Note 22) LOVL bit = “1” +2 HPG bit = “0” IN4+/− Æ HPL/HPR −10.5 −6 HPG bit = “1” −2.4 max Units - Vpp +4.5 −15.5 - dB dB dB dB - Vpp +4.5 +4.5 - dB dB dB dB - Vpp −1.5 +4.5 −1.5 - dB dB dB dB dB dB Note 18. Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin / 20kΩ (typ). Note 19. The gain is in inverse proportion to external input resistance. Note 20. Maximum Input voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ). Note 21. Maximum Input voltage is proportional to AVDD voltage. Vout = (IN4+) − (IN4−) = 1.2 x AVDD (typ). The signals with same amplitude and inverted phase should be input to IN4+ and IN4− pins, respectively. Note 22. Vout = (LOP) − (LON) at LODIF bit = “1”. MS0670-E-00 2007/09 - 12 - [AK4673] SAR ADC Analog Input Characteristics: XP, YP, YN input → SAR ADC Parameter min. typ. ADC for Touch Screen Resolution 12 No Missing Codes 11 12 Integral Nonlinearity (INL) Error Differential Nonlinearity (DNL) Error ±1 Offset Error Gain Error Throughput Rate 8.2 Touch Panel Driver On-Resistance XP, YP 5 XN, YN 5 XP Pull Up Register (when pen interrupt enable) 10 Power Supplies: Power-Up (PDN pin = “H”, PD0 bit=“0”) All Circuit Power-up: Audio Block AVDD+DVDD+TVDD1+TVDD2 16 (Note 23) HVDD: HP-Amp Normal Operation 5 No Output (Note 24) TSVDD Fast Mode: 0.1 Normal Mode SCL=400KHz Addressed Standard Mode: 0.077 SCL=100KHz Fast Mode: 0.023 Power Down SCL=400KHz Not Addressed Standard Mode: 0.006 SCL=100KHz Power-Down (PDN pin = “L”, PD0 bit = “0”) (Note 25) AVDD+DVDD+TVDD1+TVDD2+HVDD+ 1 TSVDD max. ±2 ±6 ±4 Units Bits Bits LSB LSB LSB LSB ksps Ω Ω kΩ 24 mA 8 mA 0.2 mA 0.15 mA mA mA 100 μA Note 23. PLL Master Mode (MCKI=12.288MHz) and PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = MCKO = PMMIN = PMMP = M/S bits = “1”. MPWR pin outputs 0mA. AVDD=11mA(typ), DVDD=3mA(typ), TVDD1+TVDD2=2mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=10mA(typ), DVDD=3mA(typ), TVDD1+TVDD2=0.03mA(typ). Note 24. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMMIN bits = “1”. Note 25. All digital input pins are fixed to each supply pin (TVDD1, TVDD2 or TSVDD) or (VSS2 or VSS3). MS0670-E-00 2007/09 - 13 - [AK4673] ■ Power Consumption for Each Operation Mode Conditions: Ta=25°C; AVDD=DVDD=TVDD1=TVDD2=HVDD=TSVDD=3.3V; VSS1=VSS2=VSS3=0V; fs=44.1kHz, External Slave Mode, BICK=64fs; 1kHz, 0dBFS input; Headphone = No output. PMADL PMHPL PMHPR PMADR PMMICL PMMICR PMAINL2 PMAINR2 PMAINL3 PMAINR3 PMAINL4 PMAINR4 AVDD [mA] DVDD [mA] TVDD1+TVDD2 [mA] HVDD [mA] Total Power [mW] 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.4 3.8 1.9 5.5 3.5 0 1.8 1.8 0 1.6 1.5 0 0.03 0.03 0 0.03 0.03 0 0.2 5 5 0.2 0.2 0 21.2 35.1 22.8 24.2 17.3 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 8.3 2.7 0.03 5 52.9 20H PMDAC 0 1 0 0 0 0 10H PMLO 0 0 0 0 0 0 01H PMMIN 0 1 1 1 1 1 00H PMVCM Power Management Bit Mode All Power-down DAC Æ Lineout DAC Æ HP LIN2/RIN2 Æ HP LIN2/RIN2 Æ ADC LIN1 (Mono) Æ ADC LIN2/RIN2 Æ ADC & DAC Æ HP Table 1. Power Consumption for each operation mode (typ) MS0670-E-00 2007/09 - 14 - [AK4673] FILTER CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.6 ∼ 3.6V, TVDD1=2.5 ∼ 3.6V, TVDD2=1.6 ∼ 3.6V, HVDD=2.6 ∼ 5.25V, TSVDD=3.3V, fs=44.1kHz; DEM=OFF; FIL1=FIL3=EQ=OFF) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 26) PB 0 17.3 kHz ±0.16dB 19.4 kHz −0.66dB 19.9 kHz −1.1dB 22.1 kHz −6.9dB Stopband SB 26.1 kHz Passband Ripple PR dB ±0.1 Stopband Attenuation SA 73 dB Group Delay (Note 27) GD 19 1/fs Group Delay Distortion 0 ΔGD μs ADC Digital Filter (HPF): (Note 28) Frequency Response (Note 26) −3.0dB FR 0.9 Hz 2.7 Hz −0.5dB 6.0 Hz −0.1dB DAC Digital Filter (LPF): Passband (Note 26) PB 0 19.6 kHz ±0.1dB 20.0 kHz −0.7dB 22.05 kHz −6.0dB Stopband SB 25.2 kHz Passband Ripple PR dB ±0.01 Stopband Attenuation SA 59 dB Group Delay (Note 27) GD 25 1/fs DAC Digital Filter (LPF) + SCF: FR dB Frequency Response: 0 ∼ 20.0kHz ±1.0 DAC Digital Filter (HPF): (Note 28) Frequency Response (Note 26) −3.0dB FR 0.9 Hz 2.7 Hz −0.5dB 6.0 Hz −0.1dB BOOST Filter: (Note 29) Frequency Response MIN FR 20Hz dB 5.76 100Hz dB 2.92 1kHz dB 0.02 MID FR 20Hz dB 10.80 100Hz dB 6.84 1kHz dB 0.13 MAX 20Hz FR dB 16.06 100Hz dB 10.54 1kHz dB 0.37 Note 26. The passband and stopband frequencies scale with fs (system sampling rate). For example, DAC is PB=0.454*fs (@−0.7dB). Each response refers to that of 1kHz. Note 27. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. Group delay of DAC part is 25/fs(typ) at PMADL=PMADR bits = “0”. Note 28. When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is enabled but the HPF of ADC is disabled. Note 29. These frequency responses scale with fs. If a high-level and low frequency signal is input, the analog output clips to the full-scale. MS0670-E-00 2007/09 - 15 - [AK4673] DC CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.6 ∼ 3.6V, TVDD1=TSVDD=2.5 ∼ 3.6V, TVDD2=1.6 ∼ 3.6V, HVDD=2.6 ∼ 5.25V) Parameter Symbol min Typ max Units High-Level Input Voltage 2.5V≤TVDD1≤3.6V VIH1 70%TVDD1 V 2.2V≤TVDD2≤3.6V VIH2 70%TVDD2 V 1.6V≤TVDD2<2.2V VIH2 75%TVDD2 V 2.5V≤TSVDD≤3.6V VIH3 70%TSVDD V Low-Level Input Voltage 2.5V≤TVDD1≤3.6V VIL1 30%TVDD1 V 2.2V≤TVDD2≤3.6V VIL2 30%TVDD2 V 1.6V≤TVDD2<2.2V VIL2 25%TVDD2 V 2.5V≤TSVDD≤3.6V VIL3 30%TSVDD V High-Level Output Voltage Except PENIRQN pin (Iout = −200μA) VOHA TVDD1−0.2 V Except PENIRQN pin (Iout = −200μA) VOHB V TVDD2−0.2 PENIRQN pin VOHT V TSVDD−0.4 (Iout = −250μA) Low-Level Output Voltage VOL 0.2 (Except SDA and PENIRQN pin: Iout = 200μA) V VOL 0.4 (PENIRQN pin: Iout = 250mA) (SDA pin: Iout = 3mA) VOL 0.4 V Input Leakage Current Iin ±10 μA SWITCHING CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.6 ∼ 3.6V; TVDD1 =TSVDD=2.5 ∼ 3.6V; TVDD2=1.6 ~ 3.6V; HVDD=2.6 ∼ 5.25V; CL=20pF; unless otherwise specified) Parameter Symbol min typ max Units PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 27 MHz Pulse Width Low tCLKL 0.4/fCLK ns Pulse Width High tCLKH 0.4/fCLK ns MCKO Output Timing Frequency fMCK 0.2352 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK 33 % LRCK Output Timing Frequency fs 7.35 48 kHz DSP Mode: Pulse Width High tLRCKH tBCK ns Except DSP Mode: Duty Cycle Duty 50 % BICK Output Timing Period BCKO bit = “0” tBCK 1/(32fs) ns BCKO bit = “1” tBCK 1/(64fs) ns Duty Cycle dBCK 50 % MS0670-E-00 2007/09 - 16 - [AK4673] Parameter Symbol PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK Pulse Width Low tCLKL Pulse Width High tCLKH MCKO Output Timing Frequency fMCK Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 256fs at fs=32kHz, 29.4kHz dMCK LRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH PLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Input Timing Period PLL3-0 bits = “0010” tBCK PLL3-0 bits = “0011” tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Slave Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH LRCK Input Timing Frequency 256fs fs 512fs fs 1024fs fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH MS0670-E-00 min typ max Units 11.2896 0.4/fCLK 0.4/fCLK - 27 - MHz ns ns 0.2352 - 12.288 MHz 40 - 50 33 60 - % % 7.35 tBCK−60 45 - 48 1/fs − tBCK 55 kHz ns % 1/(64fs) 0.4 x tBCK 0.4 x tBCK - 1/(32fs) - ns ns ns 7.35 tBCK−60 45 - 48 1/fs − tBCK 55 kHz ns % 1/(64fs) 130 130 - 1/(32fs) - ns ns ns 7.35 tBCK−60 45 - 48 1/fs − tBCK 55 kHz ns % 0.4 x tBCK 0.4 x tBCK 1/(32fs) 1/(64fs) - - ns ns ns ns 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK - 12.288 13.312 13.312 - MHz MHz MHz ns ns 7.35 7.35 7.35 tBCK−60 45 - 48 26 13 1/fs − tBCK 55 kHz kHz kHz Ns % 312.5 130 130 - - ns ns ns 2007/09 - 17 - [AK4673] Parameter Symbol External Master Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH LRCK Output Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BICK Output Timing Period BCKO bit = “0” tBCK BCKO bit = “1” tBCK Duty Cycle dBCK Audio Interface Timing (DSP Mode) Master Mode tDBF LRCK “↑” to BICK “↑” (Note 30) tDBF LRCK “↑” to BICK “↓” (Note 31) tBSD BICK “↑” to SDTO (BCKP bit = “0”) tBSD BICK “↓” to SDTO (BCKP bit = “1”) SDTI Hold Time tSDH SDTI Setup Time tSDS Slave Mode tLRB LRCK “↑” to BICK “↑” (Note 30) tLRB LRCK “↑” to BICK “↓” (Note 31) tBLR BICK “↑” to LRCK “↑” (Note 30) tBLR BICK “↓” to LRCK “↑” (Note 31) tBSD BICK “↑” to SDTO (BCKP bit = “0”) tBSD BICK “↓” to SDTO (BCKP bit = “1”) SDTI Hold Time tSDH SDTI Setup Time tSDS 2 Audio Interface Timing (Right/Left justified & I S) Master Mode tMBLR BICK “↓” to LRCK Edge (Note 30) tLRD LRCK Edge to SDTO (MSB) (Except I2S mode) tBSD BICK “↓” to SDTO SDTI Hold Time tSDH SDTI Setup Time tSDS Slave Mode tLRB LRCK Edge to BICK “↑” (Note 31) tBLR BICK “↑” to LRCK Edge (Note 32) tLRD LRCK Edge to SDTO (MSB) (Except I2S mode) tBSD BICK “↓” to SDTO SDTI Hold Time tSDH SDTI Setup Time tSDS Min typ max Units 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK - 12.288 13.312 13.312 - MHz MHz MHz Ns Ns 7.35 - tBCK 50 48 - kHz ns % - 1/(32fs) 1/(64fs) 50 - ns ns % 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 70 −70 70 −70 50 50 - ns ns ns ns ns ns 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 50 50 - 80 80 - ns ns ns ns ns ns ns ns −40 −70 - 40 70 ns ns −70 50 50 - 70 - ns ns ns 50 50 - - 80 ns ns ns 50 50 - 80 - ns ns ns Note 30. MSBS, BCKP bits = “00” or “11”. Note 31. MSBS, BCKP bits = “01” or “10”. Note 32. BICK rising edge must not occur at the same time as LRCK edge. MS0670-E-00 2007/09 - 18 - [AK4673] Parameter Symbol min 2 Control Interface Timing (I C Bus mode) (Note 33) SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 34) tHD:DAT 0 SDAA, SDAT Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Capacitive Load on Bus Cb Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 Power-down & Reset Timing PDN Pulse Width (Note 35) tPD 150 tPDV PMADL or PMADR “↑” to SDTO valid (Note 36) Note 33. I2C is a registered trademark of Philips Semiconductors. Note 34. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 35. The AK4673 can be reset by the PDN pin = “L”. Note 36. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”. MS0670-E-00 typ max Units - 400 0.3 0.3 400 50 KHz μs μs μs μs μs μs μs μs μs μs pF ns 1059 - ns 1/fs 2007/09 - 19 - [AK4673] ■ Timing Diagram 1/fCLK VIH2 MCKI VIL2 tCLKH tCLKL 1/fs 50%TVDD2 LRCK tLRCKH tLRCKL tBCK Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 50%TVDD2 BICK tBCKH tBCKL dBCK = tBCKH / tBCK x 100 tBCKL / tBCK x 100 1/fMCK 50%TVDD2 MCKO tMCKL dMCK = tMCKL x fMCK x 100 Figure 3. Clock Timing (PLL/EXT Master mode) Note 37. MCKO is not available at EXT Master mode. tLRCKH LRCK 50%TVDD2 tDBF BICK (BCKP = "0") 50%TVDD2 BICK (BCKP = "1") 50%TVDD2 tBSD SDTO MSB tSDS 50%TVDD2 tSDH VIH2 SDTI VIL2 Figure 4. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”) MS0670-E-00 2007/09 - 20 - [AK4673] tLRCKH LRCK 50%TVDD2 tDBF BICK (BCKP = "1") 50%TVDD2 BICK (BCKP = "0") 50%TVDD2 tBSD SDTO 50%TVDD2 MSB tSDS tSDH VIH2 SDTI VIL2 Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “1”) 50%TVDD2 LRCK tMBLR BICK 50%TVDD2 tLRD tBSD SDTO 50%TVDD2 tSDS tSDH VIH2 SDTI VIL2 Figure 6. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode) MS0670-E-00 2007/09 - 21 - [AK4673] 1/fs VIH2 LRCK VIL2 tLRCKH tBLR tBCK VIH2 BICK (BCKP = "0") VIL2 tBCKH tBCKL VIH2 BICK (BCKP = "1") VIL2 Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “0”) 1/fs VIH2 LRCK VIL2 tLRCKH tBLR tBCK VIH2 BICK (BCKP = "1") VIL2 tBCKH tBCKL VIH2 BICK (BCKP = "0") VIL2 Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “1”) MS0670-E-00 2007/09 - 22 - [AK4673] 1/fCLK VIH2 MCKI VIL2 tCLKH tCLKL 1/fs VIH2 LRCK VIL2 tLRCKH tLRCKL tBCK Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 VIH2 BICK VIL2 tBCKH tBCKL fMCK 50%TVDD2 MCKO tMCKL dMCK = tMCKL x fMCK x 100 Figure 9. Clock Timing (PLL Slave mode, Except DSP mode) tLRCKH VIH2 LRCK VIL2 tLRB VIH2 BICK VIL2 (BCKP = "0") VIH2 BICK (BCKP = "1") VIL2 tBSD SDTO MSB tSDS 50%TVDD2 tSDH VIH2 SDTI MSB VIL2 Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = “0”) MS0670-E-00 2007/09 - 23 - [AK4673] tLRCKH VIH2 LRCK VIL2 tLRB VIH2 BICK VIL2 (BCKP = "1") VIH2 BICK (BCKP = "0") VIL2 tBSD SDTO 50%TVDD2 MSB tSDS tSDH VIH2 SDTI MSB VIL2 Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS = “1”) 1/fCLK VIH2 MCKI VIL2 tCLKH tCLKL 1/fs VIH2 LRCK VIL2 tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tBCK VIH2 BICK VIL2 tBCKH tBCKL Figure 12. Clock Timing (EXT Slave mode) MS0670-E-00 2007/09 - 24 - [AK4673] VIH2 LRCK VIL2 tLRB tBLR VIH2 BICK VIL2 tBSD tLRD SDTO 50%TVDD2 MSB tSDH tSDS VIH2 SDTI VIL2 Figure 13. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode) VIH1 SDAA VIL1 tBUF tLOW tR tHIGH tF tSP VIH1 SCLA VIL1 tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA tSU:STO Start Stop Figure 14. I2C Bus Mode Timing (Audio) VIH3 SDAT VIL3 tBUF tLOW tR tHIGH tF tSP VIH3 SCLT VIL3 tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA Start tSU:STO Stop Figure 15. I2C Bus Mode Timing (TSC) MS0670-E-00 2007/09 - 25 - [AK4673] PMADL bit or PMADR bit tPDV SDTO 50%TVDD2 Figure 16. Power Down & Reset Timing 1 tPD PDN VIL1 Figure 17. Power Down & Reset Timing 2 MS0670-E-00 2007/09 - 26 - [AK4673] AUDIO OPERATION OVERVIEW ■ System Clock There are the following four clock modes to interface with external devices (Table 2 and Table 3). Mode PMPLL bit M/S bit PLL3-0 bits Figure PLL Master Mode (Note 38) 1 1 See Table 5 Figure 18 PLL Slave Mode 1 Figure 19 1 0 See Table 5 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 Figure 20 1 0 See Table 5 Figure 21 (PLL Reference Clock: LRCK or BICK pin) EXT Slave Mode 0 0 x Figure 22 EXT Master Mode 0 1 x Figure 23 Note 38. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid clocks are output from MCKO pin when MCKO bit is “1”. Table 2. Clock Mode Setting (x: Don’t care) Mode MCKO bit 0 PLL Master Mode 1 0 PLL Slave Mode (PLL Reference Clock: MCKI pin) 1 MCKO pin “L” Selected by PS1-0 bits “L” Selected by PS1-0 bits MCKI pin Selected by PLL3-0 bits Selected by PLL3-0 bits PLL Slave Mode (PLL Reference Clock: LRCK or BICK pin) 0 “L” GND EXT Slave Mode 0 “L” Selected by FS1-0 bits EXT Master Mode 0 “L” Selected by FS1-0 bits BICK pin Output (Selected by BCKO bit) LRCK pin Input (≥ 32fs) Input (1fs) Input (Selected by PLL3-0 bits) Input (≥ 32fs) Output (Selected by BCKO bit) Output (1fs) Input (1fs) Input (1fs) Output (1fs) Table 3. Clock pins state in Clock Mode ■ Master Mode/Slave Mode The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the AK4673 is power-down mode (PDN pin = “L”) and exits reset state, the AK4673 is slave mode. After exiting reset state, the AK4673 goes to master mode by changing M/S bit = “1”. When the AK4673 is used in master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and BICK pins of the AK4673 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the floating state. M/S bit Mode 0 Slave Mode (default) 1 Master Mode Table 4. Select Master/Slave Mode MS0670-E-00 2007/09 - 27 - [AK4673] ■ PLL Mode (AIN3 bit = “0”, PMPLL bit = “1”) When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time, when the AK4673 is supplied stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes is shown in Table 5. When AIN3 bit = “1”, the PLL is not available. 1) Setting of PLL Mode Mode PLL3 bit PLL2 bit PLL1 bit PLL0 bit PLL Reference Clock Input Pin Input Frequency 0 2 0 0 0 0 0 1 0 0 LRCK pin BICK pin 1fs 32fs 3 0 0 1 1 BICK pin 64fs 4 5 6 7 8 12 13 14 15 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0 0 1 0 1 Others R and C of VCOC pin R[Ω] C[F] 6.8k 220n 10k 4.7n 10k 10n 10k 4.7n 10k 10n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 10n 10k 10n 10k 220n 10k 220n PLL Lock Time (max) 160ms 2ms 4ms 2ms 4ms 40ms 40ms 40ms 40ms 40ms 40ms 40ms 60ms 60ms (default) MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 19.2MHz MCKI pin 13.5MHz MCKI pin 27MHz MCKI pin 13MHz MCKI pin 26MHz Others N/A Table 5. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available) 2) Setting of sampling frequency in PLL Mode When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 6. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency 0 0 0 0 0 8kHz (default) 1 0 0 0 1 12kHz 2 0 0 1 0 16kHz 3 0 0 1 1 24kHz 4 0 1 0 0 7.35kHz 5 0 1 0 1 11.025kHz 6 0 1 1 0 14.7kHz 7 0 1 1 1 22.05kHz 10 1 0 1 0 32kHz 11 1 0 1 1 48kHz 14 1 1 1 0 29.4kHz 15 1 1 1 1 44.1kHz Others Others N/A Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin) (N/A: Not available) MS0670-E-00 2007/09 - 28 - [AK4673] When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3 and FS1-0 bits. (Table 7). FS2 bit is “don’t care”. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range 0 x 0 0 0 (default) 7.35kHz ≤ fs ≤ 8kHz 0 x 1 1 0 8kHz < fs ≤ 12kHz 0 x 0 2 1 12kHz < fs ≤ 16kHz 0 x 1 3 1 16kHz < fs ≤ 24kHz 1 x 0 6 1 24kHz < fs ≤ 32kHz 1 x 1 7 1 32kHz < fs ≤ 48kHz Others Others N/A (x: Don’t care, N/A: Not available) Table 7. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin) ■ PLL Unlock State 1) PLL Master Mode (AIN3 bit = “0”; PMPLL bit = “1”, M/S bit = “1”) In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from the MCKO pins at MCKO bit is “1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, the MCKO pin goes to “L” (Table 8). After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state after a period of 1/fs. When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by setting PMPLL bit to “0”. MCKO pin BICK pin MCKO bit = “0” MCKO bit = “1” After that PMPLL bit “0” Æ “1” “L” Output Invalid “L” Output PLL Unlock (except above case) “L” Output Invalid Invalid PLL Lock “L” Output See Table 10 See Table 11 Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) PLL State LRCK pin “L” Output Invalid 1fs Output 2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”) In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. Then, the clock selected by Table 10 is output from the MCKO pin when PLL is locked. ADC and DAC output invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL and DACH bits. MCKO pin MCKO bit = “0” MCKO bit = “1” After that PMPLL bit “0” Æ “1” “L” Output Invalid PLL Unlock “L” Output Invalid PLL Lock “L” Output Output Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”) PLL State MS0670-E-00 2007/09 - 29 - [AK4673] ■ PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz) is input to the MCKI pin, MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits (Table 10) and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit (Table 11). 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz DSP or μP AK4673 MCKI 256fs/128fs/64fs/32fs MCKO 32fs, 64fs BICK 1fs LRCK MCLK BCLK LRCK SDTO SDTI SDTI SDTO Figure 18. PLL Master Mode Mode PS1 bit PS0 bit MCKO pin 0 0 0 256fs (default) 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs Table 10. MCKO Output Frequency (PLL Mode, MCKO bit = “1”) BICK Output Frequency 0 32fs (default) 1 64fs Table 11. BICK Output Frequency at Master Mode BCKO bit MS0670-E-00 2007/09 - 30 - [AK4673] ■ PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock to the AK4673 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5). a) PLL reference clock: MCKI pin BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not matter. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 10) and the output is enabled by MCKO bit. Sampling frequency can be selected by FS3-0 bits (Table 6). 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz AK4673 DSP or μP MCKI MCKO BICK LRCK 256fs/128fs/64fs/32fs ≥ 32fs 1fs MCLK BCLK LRCK SDTO SDTI SDTI SDTO Figure 19. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) MS0670-E-00 2007/09 - 31 - [AK4673] b) PLL reference clock: BICK or LRCK pin Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (Table 7) AK4673 DSP or μP MCKO MCKI BICK LRCK 32fs or 64fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 20. PLL Slave Mode 2 (PLL Reference Clock: BICK pin) AK4673 DSP or μP MCKO MCKI BICK LRCK ≥ 32fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 21. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin) The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4673 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”). MS0670-E-00 2007/09 - 32 - [AK4673] ■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK4673 becomes EXT mode. The master clock is input from the MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of a normal audio CODEC. The clocks required to operate the AK4673 are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (Table 12). Mode 0 1 2 3 MCKI Input Sampling Frequency Frequency Range x 0 0 256fs (default) 7.35kHz ∼ 48kHz x 0 1 1024fs 7.35kHz ∼ 13kHz x 1 0 256fs 7.35kHz ∼ 48kHz x 1 1 512fs 7.35kHz ∼ 26kHz Table 12. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) (x: Don’t care) FS3-2 bits FS1 bit FS0 bit The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through LOUT/ROUT pins at fs=8kHz is shown in Table 13. S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 83dB 512fs 93dB 1024fs 93dB Table 13. Relationship between MCKI and S/N of LOUT/ROUT pins MCKI The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4673 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”). AK4673 DSP or μP MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK MCLK ≥ 32fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 22. EXT Slave Mode MS0670-E-00 2007/09 - 33 - [AK4673] ■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) The AK4673 becomes EXT master mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The input frequency of MCKI is selected by FS1-0 bits (Table 14). MCKI Input Sampling Frequency Frequency Range x 0 0 0 256fs (default) 7.35kHz ∼ 48kHz x 1 0 1 1024fs 7.35kHz ∼ 13kHz x 2 1 0 256fs 7.35kHz ∼ 48kHz x 3 1 1 512fs 7.35kHz ∼ 26kHz Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (x: Don’t care) Mode FS3-2 bits FS1 bit FS0 bit The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through LOUT/ROUT pins at fs=8kHz is shown in Table 15. S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 83dB 512fs 93dB 1024fs 93dB Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins MCKI MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If MCKI is not provided, the AK4673 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”). AK4673 DSP or μP MCKO 256fs, 512fs or 1024fs MCKI MCLK 32fs or 64fs BICK 1fs LRCK BCLK LRCK SDTO SDTI SDTI SDTO Figure 23. EXT Master Mode BICK Output Frequency 0 32fs (default) 1 64fs Table 16. BICK Output Frequency at Master Mode BCKO bit MS0670-E-00 2007/09 - 34 - [AK4673] ■ System Reset When power-up, the AK4673 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC bits is “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2’s compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete. When PMDAC bit is “1”, the ADC does not require an initialization cycle. The DAC enters an initialization cycle when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2’s compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle. ■ Audio Interface Format Four types of data formats are available and are selected by setting the DIF1-0 bits (Table 17). In all modes, the serial data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK are output from the AK4673 in master mode, but must be input to the AK4673 in slave mode. Mode 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO (ADC) SDTI (DAC) DSP Mode DSP Mode MSB justified LSB justified MSB justified MSB justified I2S compatible I2S compatible Table 17. Audio Interface Format BICK ≥ 32fs ≥ 32fs ≥ 32fs ≥ 32fs Figure Table 18 Figure 28 Figure 29 Figure 30 (default) In Modes 1-3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”). In Mode 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 18). DIF1 0 DIF0 MSB S BCKP 0 0 0 1 1 0 1 1 0 Audio Interface Format MSB of SDTO is output by the rising edge (“↑”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the falling edge (“↓”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by the falling edge (“↓”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the rising edge (“↑”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by next rising edge (“↑”) of the falling edge (“↓”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the falling edge (“↓”) of the BICK just after the output timing of SDTO’s MSB. MSB of SDTO is output by next falling edge (“↓”) of the rising edge (“↑”) of the first BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the rising edge (“↑”) of the BICK just after the output timing of SDTO’s MSB. Table 18. Audio Interface Format in Mode 0 Figure Figure 24 (default) Figure 25 Figure 26 Figure 27 If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1” at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit data. MS0670-E-00 2007/09 - 35 - [AK4673] LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 24 18 25 26 27 26 29 30 31 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 46 34 47 48 49 50 26 27 26 62 63 30 31 BICK(64fs) Lch SDTO(o) Rch 15 14 2 1 0 2 1 0 15 14 1 0 2 1 0 Rch Lch SDTI(i) 2 15 14 15 14 1/fs 15:MSB, 0:LSB Figure 24. Mode 0 Timing (BCKP = “0”, MSBS = “0”) LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 24 18 25 29 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 34 46 47 48 49 50 62 63 BICK(64fs) Lch SDTO(o) 15 14 Rch 2 1 0 2 1 0 15 14 2 1 0 2 1 0 Rch Lch SDTI(i) 15 14 15 14 1/fs 15:MSB, 0:LSB Figure 25. Mode 0 Timing (BCKP = “1”, MSBS = “0”) MS0670-E-00 2007/09 - 36 - [AK4673] LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 24 18 25 26 27 26 29 30 31 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 46 34 47 48 49 50 26 27 26 62 63 30 31 BICK(64fs) Lch SDTO(o) Rch 15 14 2 1 0 15 14 Lch SDTI(i) 2 1 0 2 1 0 Rch 15 14 2 1 0 15 14 1/fs 15:MSB, 0:LSB Figure 26. Mode 0 Timing (BCKP = “0”, MSBS = “1”) LRCK (Master) LRCK (Slave) 15 0 1 8 2 9 10 11 12 13 14 15 16 17 24 18 25 29 0 BICK(32fs) Lch SDTO(o) 0 SDTI(i) 0 Rch 15 14 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Lch 15 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Rch 15 14 0 15 14 14 2 15 16 17 18 30 31 15 14 32 33 34 46 47 48 49 50 62 63 BICK(64fs) Lch SDTO(o) 15 14 Rch 2 1 0 Lch SDTI(i) 15 14 15 14 2 1 0 2 1 0 Rch 2 1 0 15 14 1/fs 15:MSB, 0:LSB Figure 27. Mode 0 Timing (BCKP = “1”, MSBS = “1”) MS0670-E-00 2007/09 - 37 - [AK4673] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) SDTI(i) 1 0 15 14 13 15 14 13 15 14 Don't Care 1 0 1 0 Don't Care 15 15 14 2 1 0 15:MSB, 0:LSB Lch Data Rch Data Figure 28. Mode 1 Timing LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 13 1 0 SDTI(i) 15 14 13 1 0 Don't Care 15 14 13 1 0 15 14 13 1 0 15 Don't Care 15 15:MSB, 0:LSB Lch Data Rch Data Figure 29. Mode 2 Timing MS0670-E-00 2007/09 - 38 - [AK4673] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 SDTI(i) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 2 1 0 SDTI(i) 15 14 2 1 0 Don't Care 15 14 2 1 0 15 14 2 1 0 Don't Care 15:MSB, 0:LSB Lch Data Rch Data Figure 30. Mode 3 Timing ■ Mono/Stereo Mode PMADL, PMADR and MIX bits set mono/stereo ADC operation. When MIX bit = “1”, EQ and FIL3 bits should be set to “0”. ALC operation (ALC bit = “1”) or digital volume operation (ALC bit = “0”) is applied to the data in Table 19. PMADL bit 0 0 1 1 PMADR bit 0 1 0 MIX bit ADC Lch data ADC Rch data x All “0” All “0” x Rch Input Signal Rch Input Signal x Lch Input Signal Lch Input Signal 0 Lch Input Signal Rch Input Signal 1 1 (L+R)/2 (L+R)/2 Table 19. Mono/Stereo ADC operation (x: Don’t care) (default) ■ Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz (@fs=44.1kHz) and scales with sampling rate (fs). When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is enabled but the HPF of ADC is disabled. MS0670-E-00 2007/09 - 39 - [AK4673] ■ MIC/LINE Input Selector The AK4673 has input selector for MIC-Amp. When MDIF1 and MDIF2 bits are “0”, INL1-0 and INR1-0 bits select LIN1/LIN2/LIN3/LIN4 and RIN1/RIN2/RIN3/RIN4, respectively. When MDIF1 and MDIF2 bits are “1”, LIN1, RIN1, LIN2 and RIN2 pins become IN1−, IN1+, IN2+ and IN2− pins respectively. In this case, full-differential input is available (Figure 32). When full-differential input is used, the signal should not be input to the pins marked by “X” in Table 21. MDIF1 bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Others MDIF2 bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 INL1 bit 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 INL0 bit 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 INR1 bit 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 INR0 bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 Lch LIN1 LIN1 LIN1 LIN1 LIN2 LIN2 LIN2 LIN2 LIN3 LIN3 LIN3 LIN3 LIN4 LIN4 LIN4 LIN4 LIN1 LIN3 LIN4 IN1+/− IN1+/− IN1+/− IN1+/− N/A Table 20. MIC/Line In Path Select (N/A: Not available) Rch RIN1 RIN2 RIN3 RIN4 RIN1 RIN2 RIN3 RIN4 RIN1 RIN2 RIN3 RIN4 RIN1 RIN2 RIN3 RIN4 IN2+/− IN2+/− IN2+/− RIN2 RIN3 RIN4 IN2+/− N/A Pin RIN2 LIN1 MIN VCOC LIN4 RIN1 LIN2 AIN3 bit MDIF1 bit MDIF2 bit LIN3 RIN3 IN4+ IN1+ IN2+ IN2− IN1− 0 0 0 O O O O O O 0 0 1 O X O O O O 0 1 0 O O X O O X 0 1 1 O O O O O X 1 0 0 O O O O O O O 1 0 1 O X O O O X O 1 1 0 O O X O X O X 1 1 1 O O O O X X X Table 21. Handling of MIC/Line Input Pins (“-”: Not available, “X”: Signal should not be input.) (default) Register MS0670-E-00 RIN4 IN4− O X O X O X O X 2007/09 - 40 - [AK4673] AK4673 INL1-0 bits LIN1/IN1− pin ADC Lch RIN1/IN1+ pin MDIF1 bit MIC-Amp INR1-0 bits RIN2/IN2− pin ADC Rch LIN2/IN2+ pin MDIF2 bit MIC-Amp These blocks are not available at PLL mode. MIN/LIN3 pin PMAINR2 bit PMAINL2 bit PMAINL4 bit PMAINR4 bit MICR3 bit RIN4/IN4− pin PMAINR3 bit LIN4/IN4+ pin PMAINL3 bit MICL3 bit VCOC/RIN3 pin Lineout, HP-Amp Figure 31. Mic/Line Input Selector AK4673 MPWR pin 1k IN1− pin MIC-Amp IN1+ pin A/D SDTO pin 1k Figure 32. Connection Example for Full-differential Mic Input (MDIF1/2 bits = “1”) <Input Selector Setting Example> In case that IN1+/− pins are used as full-differential mic input and LIN2/RIN2 pins are used as stereo line input, it is recommended that the following two modes are set by register setting according to each case. MDIF1 bit 1 0 MDIF2 bit 0 0 INL1 bit INL0 bit INR1 bit INR0 bit 0 0 0 1 0 1 0 1 Table 22. MIC/Line In Path Select Example MS0670-E-00 Lch IN1+/− LIN2 Rch RIN2 RIN2 2007/09 - 41 - [AK4673] ■ MIC Gain Amplifier The AK4673 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (Table 23). The typical input impedance is 60kΩ(typ)@MGAIN1-0 bits = “00” or 30kΩ(typ)@MGAIN1-0 bits = “01”, “10” or “11”. MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 23. Mic Input Gain (default) ■ MIC Power When PMMP bit = “1”, the MPWR pin supplies power for the microphone. This output voltage is typically 0.75 x AVDD and the load resistance is minimum 0.5kΩ. In case of using two sets of stereo mic, the load resistance is minimum 2kΩ for each channel. Any capacitor must not be connected directly to the MPWR pin (Figure 33). PMMP bit MPWR pin 0 Hi-Z 1 Output Table 24. MIC Power (default) MIC Power ≥ 2kΩ ≥ 2kΩ ≥ 2kΩ ≥ 2kΩ MPWR pin Microphone LIN1 pin Microphone RIN1 pin Microphone LIN2 pin Microphone RIN2 pin Figure 33. MIC Block Circuit MS0670-E-00 2007/09 - 42 - [AK4673] ■ Digital EQ/HPF/LPF The AK4673 has a wind-noise reduction filter, stereo separation emphasis, gain compensation and ALC (Automatic Level Control) by digital domain for A/D converted data (Figure 34). FIL1, FIL3 and EQ blocks are IIR filters of 1st order. The filter coefficient of FIL3, EQ and FIL1 blocks can be set to any value. Refer to the section of “ALC operation” about ALC. When only DAC is powered-up, digital EQ/HPF/LPF circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, digital EQ/HPF/LPF circuit operates at recording path. Even if the path is switched from recording to playback, the register setting of filter coefficient at recording remains. Therefore, FIL3, EQ, FIL1 and GN1-0 bits should be set to “0” if digital EQ/HPF/LPF is not used for playback path. PMADL bit, PMADR bit PMDAC bit 0 1 0 LOOP bit Status Digital EQ/HPF/LPF x Power-down Power-down (default) “00” x Playback Playback path x Recording Recording path “01”, “10” or “11” 0 Recording & Playback Recording path 1 1 Recording Monitor Playback Recording path Note 39. Stereo separation emphasis circuit is effective only at stereo operation. Table 25. Digital EQ/HPF/LPF Circuit Setting (x: Don’t care) FIL3 coefficient also sets the attenuation of the stereo separation emphasis. The combination of GN1-0 bits (Table 26) and EQ coefficient set the compensation gain. FIL1 and FIL3 blocks become HPF when F1AS and F3AS bits are “0” and become LPF when F1AS and F3AS bits are “1”, respectively. When EQ and FIL1 bits are “0”, EQ and FIL1 blocks become “through” (0dB). When FIL3 bit is “0”, FIL3 block become “MUTE”. When each filter coefficient is changed, each filter should be set to “through” (“MUTE” in case of FIL3). When MIX bit = “1”, only FIL1 is available. In this case, EQ and FIL3 bits should be set to “0”. Wind-noise reduction FIL1 An y coefficient F1A13-0 F1B13-0 F1AS Stereo separation emphasis FIL3 Gain compensation EQ An y coefficient 0dB ∼ -10dB F3A13-0 MUTE F3B13-0 (set by F3AS FIL3 coefficient) Gain ALC An y coefficient GN1-0 EQA15-0 +24/+12/0dB EQB13-0 EQC15-0 +12dB ∼ 0dB Figure 34. Digital EQ/HPF/LPF GN1 GN0 Gain 0 0 0dB (default) 0 1 +12dB 1 x +24dB Table 26. Gain select of gain block (x: Don’t care) MS0670-E-00 2007/09 - 43 - [AK4673] [Filter Coefficient Setting] 1) When FIL1 and FIL3 are set to “HPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of should be set to 0dB.) Register setting FIL1: F1AS bit = “0”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 − 1 / tan (πfc/fs) 1 / tan (πfc/fs) A = 10K/20 x , B= 1 + 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function Amplitude 1 − z −1 H(z) = A 2 − 2cos (2πf/fs) M(f) = A 1 + Bz −1 Phase θ(f) = tan −1 1 + B2 + 2Bcos (2πf/fs) (B+1)sin (2πf/fs) 1 - B + (B−1)cos (2πf/fs) 2) When FIL1 and FIL3 are set to “LPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of FIL1 should be set to 0dB.) Register setting FIL1: F1AS bit = “1”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 − 1 / tan (πfc/fs) 1 A = 10K/20 x , 1 + 1 / tan (πfc/fs) Transfer function 1 + Bz −1 1 + 1 / tan (πfc/fs) Amplitude 1 + z −1 H(z) = A B= 2 + 2cos (2πf/fs) M(f) = A 1 + B2 + 2Bcos (2πf/fs) MS0670-E-00 Phase θ(f) = tan −1 (B−1)sin (2πf/fs) 1 + B + (B+1)cos (2πf/fs) 2007/09 - 44 - [AK4673] 3) EQ fs: Sampling frequency fc1: Pole frequency fc2: Zero-point frequency f: Input signal frequency K: Filter gain [dB] (Maximum +12dB) Register setting EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C (MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0) A = 10K/20 x 1 − 1 / tan (πfc1/fs) 1 + 1 / tan (πfc2/fs) , B= 1 + 1 / tan (πfc1/fs) A + Cz Amplitude −1 1 + Bz −1 C =10K/20 x 1 + 1 / tan (πfc1/fs) Transfer function H(z) = , 2 1 − 1 / tan (πfc2/fs) 1 + 1 / tan (πfc1/fs) Phase 2 A + C + 2ACcos (2πf/fs) M(f) = 1 + B2 + 2Bcos (2πf/fs) θ(f) = tan −1 (AB−C)sin (2πf/fs) A + BC + (AB+C)cos (2πf/fs) [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 213 X should be rounded to integer, and then should be translated to binary code (2’s complement). MSB of each filter coefficient setting register is sine bit. [Filter Coefficient Setting Example] 1) FIL1 block Example: HPF, fs=44.1kHz, fc=100Hz F1AS bit = “0” F1A[13:0] bits = 01 1111 1100 0110 F1B[13:0] bits = 10 0000 0111 0100 2) EQ block Example: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB Gain[dB] +8dB fc1 fc2 Frequency EQA[15:0] bits = 0000 1001 0110 1110 EQB[13:0] bits = 10 0001 0101 1001 EQC[15:0] bits = 1111 1001 1110 1111 MS0670-E-00 2007/09 - 45 - [AK4673] ■ ALC Operation The ALC (Automatic Level Control) is executed by ALC block when ALC bit is “1”. When only DAC is powered-up, ALC circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, ALC circuit operates at recording path. PMADL bit, PMADR bit PMDAC bit 0 1 0 “00” “01”, “10” or “11” 1. 1 LOOP bit Status x Power-down x Playback x Recording 0 Recording & Playback 1 Recording Monitor Playback Table 27. ALC Setting (x: Don’t care) ALC Power-down Playback path Recording path Recording path Recording path (default) ALC Limiter Operation During the ALC limiter operation, if either Lch or Rch exceeds the ALC limiter detection level (Table 28), the IVL and IVR values (same value) are attenuated automatically to the amount defined by the ALC limiter ATT step (Table 29). The IVL and IVR are then set to the same value for both channels. When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout period of both ALC limiter and recovery operation (Table 30). When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits. The attenuate operation is executed continuously until the input signal level becomes ALC limiter detection level (Table 28) or less. After completing the attenuation operation, unless ALC bit is changed to “0”, the operation repeats when the input signal level exceeds LMTH1-0 bits. LMTH1 0 0 1 1 LMTH0 0 1 0 1 ALC Limier Detection Level ALC Recovery Waiting Counter Reset Level ALC Output ≥ −2.5dBFS −2.5dBFS > ALC Output ≥ −4.1dBFS ALC Output ≥ −4.1dBFS −4.1dBFS > ALC Output ≥ −6.0dBFS ALC Output ≥ −6.0dBFS −6.0dBFS > ALC Output ≥ −8.5dBFS ALC Output ≥ −8.5dBFS −8.5dBFS > ALC Output ≥ −12dBFS Table 28. ALC Limiter Detection Level / Recovery Counter Reset Level ZELMN 0 1 ZTM1 ZTM0 0 0 1 1 0 1 0 1 LMAT1 LMAT0 ALC Limiter ATT Step 0 0 1 step 0.375dB 0 1 2 step 0.750dB 1 0 4 step 1.500dB 1 1 8 step 3.000dB x x 1step 0.375dB Table 29. ALC Limiter ATT Step (x: Don’t care) (default) Zero Crossing Timeout Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 30. ALC Zero Crossing Timeout Period MS0670-E-00 (default) (default) 2007/09 - 46 - [AK4673] 2. ALC Recovery Operation The ALC recovery operation waits for the WTM2-0 bits (Table 31) to be set after completing the ALC limiter operation. If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 28) during the wait time, the ALC recovery operation is executed. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 32) up to the set reference level (Table 33) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 30). Then the IVL and IVR are set to the same value for both channels. The ALC recovery operation is executed at a period set by WTM2-0 bits. When zero cross is detected at both channels during the wait period set by WTM2-0 bits, the ALC recovery operation waits until WTM2-0 period and the next recovery operation is executed. If ZTM1-0 is longer than WTM2-0 and no zero crossing occurs, the ALC recovery operation is executed at a period set by ZTM1-0 bits. For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to “01”, IVOL is changed to 32H by the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds the reference level (REF7-0), the IVOL values are not increased. When “ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)” during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When “ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”, the waiting timer of ALC recovery operation starts. The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation (Fast Recovery Operation). When large noise is input to microphone instantaneously, the quality of small signal level in the large noise can be improved by this fast recovery operation. The speed of fast recovery operation is set by RFST1-0 bits (Table 34). WTM2 WTM1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 ALC Recovery Operation Waiting Period 8kHz 16kHz 44.1kHz 0 128/fs 16ms 8ms 2.9ms 1 256/fs 32ms 16ms 5.8ms 0 512/fs 64ms 32ms 11.6ms 1 1024/fs 128ms 64ms 23.2ms 0 2048/fs 256ms 128ms 46.4ms 1 4096/fs 512ms 256ms 92.9ms 0 8192/fs 1024ms 512ms 185.8ms 1 16384/fs 2048ms 1024ms 371.5ms Table 31. ALC Recovery Operation Waiting Period WTM0 RGAIN1 0 0 1 1 RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 32. ALC Recovery GAIN Step MS0670-E-00 (default) (default) 2007/09 - 47 - [AK4673] REF7-0 GAIN(dB) Step F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 0.375dB E1H +30.0 (default) E0H +29.625 : : 03H −53.25 02H −53.625 01H −54.0 00H MUTE Table 33. Reference Level at ALC Recovery operation RFST1 bit RFST0 bit Recovery Speed 0 0 4 times (default) 0 1 8 times 1 0 16times 1 1 N/A Table 34. Fast Recovery Speed Setting (N/A: Not available) MS0670-E-00 2007/09 - 48 - [AK4673] 3. Example of ALC Operation Table 35 shows the examples of the ALC setting for mic recording. Register Name Comment LMTH1-0 ZELMN ZTM1-0 Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM2-0 bits should be the same or longer data as ZTM1-0 bits. Maximum gain at recovery operation WTM2-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 RFST1-0 ALC Gain of IVOL Limiter ATT step Recovery GAIN step Fast Recovery Speed ALC enable Data 01 0 01 fs=8kHz Operation −4.1dBFS Enable 32ms Data 01 0 11 fs=44.1kHz Operation −4.1dBFS Enable 23.2ms 001 32ms 011 23.2ms E1H +30dB E1H +30dB E1H +30dB E1H +30dB 00 00 00 1 1 step 1 step 4 times Enable 00 1 step 00 1 step 00 4 times 1 Enable Table 35. Example of the ALC setting The following registers should not be changed during the ALC operation. These bits should be changed after the ALC operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”. • LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0 Example: Limiter = Zero crossing Enable Recovery Cycle = 32ms@8kHz Zero Crossing Timeout Period = 32ms@8kHz Limiter and Recovery Step = 1 Fast Recovery Speed = 4 step Gain of IVOL = +30dB Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS ALC bit = “1” Manual Mode WR (ZTM1-0, WTM2-0, RFST1-0) (1) Addr=06H, Data=14H WR (REF7-0) (2) Addr=08H, Data=E1H WR (IVL/R7-0) * The value of IVOL should be (3) Addr=09H&0CH, Data=E1H the same or smaller than REF’s WR (RGAIN1, LMTH1) (4) Addr=0BH, Data=00H WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”) (5) Addr=07H, Data=21H ALC Operation Note : WR : Write Figure 35. Registers set-up sequence at ALC operation MS0670-E-00 2007/09 - 49 - [AK4673] ■ Input Digital Volume (Manual Mode) The input digital volume becomes manual mode when ALC bit is “0”. This mode is used in the case shown below. 1. 2. 3. After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH1-0 and etc) When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed. For example; when the sampling frequency is changed. When IVOL is used as a manual volume. IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 36). The IVOL value is changed at zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVL7-0 or IVR7-0 bits are written during PMADL=PMADR bits = “0”, IVOL operation starts with written values at the end of the ADC initialization cycle after PMADL or PMADR bit is changed to “1”. Even if the path is switched from recording to playback, the register setting of IVOL remains. Therefore, IVL7-0 and IVR7-0 bits should be set to “91H” (0dB). IVL7-0 IVR7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H GAIN (dB) Step +36.0 +35.625 +35.25 : +30.375 0.375dB +30.0 +29.625 : −53.25 −53.625 −54 MUTE Table 36. Input Digital Volume Setting MS0670-E-00 (default) 2007/09 - 50 - [AK4673] When writing to the IVL7-0 and IVR7-0 bits continuously, the control register should be written in an interval more than zero crossing timeout. If not, IVL and IVR are not changed since zero crossing counter is reset at every write operation. If the same register value as the previous write operation is written to IVL and IVR, this write operation is ignored and zero crossing counter is not reset. Therefore, IVL and IVR can be written by an interval less than zero crossing timeout. ALC bit ALC Status Disable Enable IVL7-0 bits E1H(+30dB) IVR7-0 bits C6H(+20dB) Internal IVL E1H(+30dB) Internal IVR C6H(+20dB) E1(+30dB) --> F1(+36dB) (1) Disable E1(+30dB) (2) E1(+30dB) --> F1(+36dB) C6H(+20dB) Figure 36. IVOL value during ALC operation (1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts. The wait time from ALC bit = “1” to ALC operation start by IVL7-0 bits is at most recovery time (WTM2-0 bits) plus zerocross timeout period (ZTM1-0 bits). (2) Writing to IVL and IVR registers (09H and 0CH) is ignored during ALC operation. After ALC is disabled, the IVOL changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1” in an interval more than zero crossing timeout period after ALC bit = “0”. MS0670-E-00 2007/09 - 51 - [AK4673] ■ De-emphasis Filter The AK4673 includes the digital de-emphasis filter (tc = 50/15μs) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 37). DEM1 0 0 1 1 DEM0 Mode 0 44.1kHz 1 OFF (default) 0 48kHz 1 32kHz Table 37. De-emphasis Control ■ Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 38). If the BST1-0 bits are set to “01” (MIN Level), use a 47μF capacitor for AC-coupling. If the boosted signal exceeds full scale, the analog output clips to the full scale. Figure 37 shows the boost frequency response at –20dB signal input. Boost Filter (fs=44.1kHz) 0 MAX Level [dB] -5 MID -10 MIN -15 -20 -25 10 100 1000 10000 Frequency [Hz] Figure 37. Bass Boost Frequency Response (fs=44.1kHz) BST1 0 0 1 1 BST0 Mode 0 OFF 1 MIN 0 MID 1 MAX Table 38. Bass Boost Control MS0670-E-00 (default) 2007/09 - 52 - [AK4673] ■ Digital Output Volume The AK4673 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit = “0”, the DVL7-0 bits control Lch level and DVR7-0 bits control Rch level. This volume has a soft transition function. The DVTM bit sets the transition time between set values of DVL/R7-0 bits as either 1061/fs or 256/fs (Table 40). When DVTM bit = “0”, a soft transition between the set values occurs (1062 levels). It takes 1061/fs (=24ms@fs=44.1kHz) from 00H (+12dB) to FFH (MUTE). DVL/R7-0 00H 01H 02H : 18H : FDH FEH FFH DVTM bit 0 1 Gain Step +12.0dB +11.5dB +11.0dB : 0.5dB 0dB : −114.5dB −115.0dB MUTE (−∞) Table 39. Digital Volume Code Table (default) Transition time between DVL/R7-0 bits = 00H and FFH Setting fs=8kHz fs=44.1kHz 1061/fs 133ms 24ms 256/fs 32ms 6ms Table 40. Transition Time Setting of Digital Output Volume MS0670-E-00 (default) 2007/09 - 53 - [AK4673] ■ Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated to −∞ (“0”) during the cycle set by the DVTM bit. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the value set by the DVL/R7-0 bits during the cycle set of the DVTM bit. If the soft mute is cancelled within the cycle set by the DVTM bit after starting the operation, the attenuation is discontinued and returned to the value set by the DVL/R7-0 bits. The soft mute is effective for changing the signal source without stopping the signal transmission (Figure 38). S M U T E bit D VTM bit D VL/R 7-0 bits D VTM bit (1) (3) A ttenuation -∞ GD (2) GD A nalog O utput Figure 38. Soft Mute Function (1) The output signal is attenuated until −∞ (“0”) by the cycle set by the DVTM bit. (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the value set by the DVL/R7-0 bits. MS0670-E-00 2007/09 - 54 - [AK4673] ■ Analog Mixing: Stereo Input (LIN2/RIN2/LIN4/RIN4, AIN3 bit = “1”: LIN3/RIN3 pins) When PMAINL2=PMAINR2 bits = “1”, LIN2 and RIN2 pins can be used as stereo line input for analog mixing. When the LINH2 and RINH2 bits are set to “1”, the input signal from the LIN2/RIN2 pins is output to Headphone-Amp. When the LINL2/RINR2 bits are set to “1”, the input signal from the LIN2/RIN2 pins is output to the stereo line output amplifier. When PMAINL4=PMAINR4 bits = “1”, LIN4 and RIN4 pins can be used as stereo line input for analog mixing. When the LINH4 and RINH4 bits are set to “1”, the input signal from the LIN4/RIN4 pins is output to Headphone-Amp. When the LINL4/RINR4 bits are set to “1”, the input signal from the LIN4/RIN4 pins is output to the stereo line output amplifier. When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. In this case, the input resistance of LIN2/RIN2/LIN4/RIN4 pins become 30kΩ (typ) at MGAIN1-0 bits = “00” and 20kΩ (typ) at MGAIN1-0 bits = “01”, “10” or “11”, respectively. When AIN3 bit = “1”, the MIN and VCOC pins become LIN3 and RIN3 pins, respectively. In this case, PLL is not available. When PMAINL3=PMAINR3 bits = “1”, LIN3 and RIN3 pins can be used as stereo line input for analog mixing. When PMMICL=PMMICR=MICL3=MICR3 bits = “1”, analog mixing source is changed from LIN3/RIN3 input to MIC-Amp output signal. When the LINH3 and RINH3 bits are set to “1”, the input signal from the LIN3/RIN3 pins is output to Headphone-Amp. When the LINL3/RINR3 bits are set to “1”, the input signal from the LIN3/RIN3 pins is output to the stereo line output amplifier. When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. When the analog mixing is used at MICL3=MICR3 bits = “0”, the input resistance of LIN3/RIN3 pins becomes 30kΩ (typ) at MGAIN1-0 bits = “00” and 20kΩ (typ) at MGAIN1-0 bits = “01”, “10” or “11”, respectively. When the analog mixing is used at MICL3=MICR3 bits = “1”, the input resistance of LIN3/RIN3 pins becomes 60kΩ (typ) at MGAIN1-0 bits = “00” and 30kΩ (typ) at MGAIN1-0 bits = “01”, “10” or “11”, respectively. Table 41, Table 42 and Table 43 show the typical gain. AK4673 INL1-0 bits LIN1/IN1− pin ADC Lch RIN1/IN1+ pin MDIF1 bit MIC-Amp INR1-0 bits RIN2/IN2− pin ADC Rch LIN2/IN2+ pin MDIF2 bit MIC-Amp These blocks are not available at PLL mode. MIN/LIN3 pin MICR3 bit PMAINR3 bit PMAINR2 bit PMAINL2 bit PMAINR4 bit PMAINL4 bit RIN4/IN4− pin MICL3 bit LIN4/IN4+ pin PMAINL3 bit VCOC/RIN3 pin Lineout, HP-Amp Figure 39. Analog Mixing Circuit (Stereo Input) MS0670-E-00 2007/09 - 55 - [AK4673] PMAINL2 bit PMAINR2 bit LINL2/RINR2 LOUT/LOP pin, ROUT/LON pin LIN2/RIN2 LINH2/RINH2 HPL, HPR pins Figure 40. Analog Mixing Circuit (LIN2/RIN2) PMAINL4 bit PMAINR4 bit LINL4/RINR4 LOUT/LOP pin, ROUT/LON pin LIN4/RIN4 LINH4/RINH4 HPL, HPR pins Figure 41. Analog Mixing Circuit (LIN4/RIN4) PMAINL3 bit PMAINR3 bit LINL3/RINR3 LOUT/LOP pin, ROUT/LON pin LIN3/RIN3 LINH3/RINH3 HPL, HPR pins Figure 42. Analog Mixing Circuit (LIN3/RIN3: PLL is not available.) LOVL bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Æ LOUT/ROUT 0 0dB (default) 1 +2dB Table 41. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ LOUT/ROUT Output Gain (typ) LOVL bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Æ LOP/LON 0 0dB (default) 1 +2dB Table 42. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ LOP/LON Output Gain (typ) HPG bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Æ HPL/HPR 0 0dB (default) 1 +3.6dB Table 43. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Æ Headphone-Amp Output Gain (typ) MS0670-E-00 2007/09 - 56 - [AK4673] ■ Analog Mixing: Full-differential Mono Input (L4DIF bit = “1”: IN4+/IN4− pins) When L4DIF bit = “1”, LIN4 and RIN4 pins becomes IN4+ and IN4− pins, respectively. When PMAINL4 bit = “1”, IN4+ and IN4− pins can be used as full-differential mono line input for analog mixing. When the LINH4 and RINH4 bits are set to “1”, the input signal from the IN4+/IN4− pins is output to Headphone-Amp. When the LINL4/RINR4 bits are set to “1”, the input signal from the IN4+/IN4− pins is output to the stereo line output amplifier. Table 44, Table 45 and Table 46 show the typical gain. Input signal amplitude is defined as (IN4+) − (IN4−). AK4673 MIC-Amp Lch LIN4/IN4+ pin L4DIF bit PMAINL4 bit MIC-Amp Rch RIN4/IN4− pin PMAINR4 bit Lineout, HP-Amp Figure 43. Full-differential Mono Analog Mixing Circuit LOVL bit IN4+/IN4− Æ LOUT/ROUT 0 (default) −6dB 1 −4dB Table 44. IN4+/IN4− Input Æ LOUT/ROUT Output Gain (typ) LOVL bit IN4+/IN4− Æ LOP/LON 0 0dB (default) 1 +2dB Table 45. IN4+/IN4− Input Æ LOP/LON Output Gain (typ) HPG bit IN4+/IN4− Æ HPL/HPR 0 (default) −6dB 1 −2.4dB Table 46. IN4+/IN4− Input Æ Headphone-Amp Output Gain (typ) MS0670-E-00 2007/09 - 57 - [AK4673] ■ Analog Mixing: Mono Input (AIN3 bit = “0”: MIN pin) When AIN3 bit = “0”, the MIN pin is used as mono input for analog mixing. When the PMMIN bit is set to “1”, the mono input is powered-up. When the MINH bit is set to “1”, the input signal from the MIN pin is output to Headphone-Amp. When the MINL bit is set to “1”, the input signal from the MIN pin is output to the stereo line output amplifier. The external resister Ri adjusts the signal level of MIN input. Table 47, Table 48 and Table 49 show the typical gain example at Ri = 20kΩ. This gain is in inverse proportion to Ri . Ri MINL MIN LOUT/LOP pin, ROUT/LON pin MINH HPL, HPR pin Figure 7. Block Diagram of MIN pin LOVL bit MIN Æ LOUT/ROUT 0 0dB (default) 1 +2dB Table 47. MIN Input Æ LOUT/ROUT Output Gain (typ) at Ri = 20kΩ LOVL bit MIN Æ LOP/LON 0 +6dB (default) 1 +8dB Table 48. MIN Input Æ LOP/LON Output Gain (typ) at Ri = 20kΩ HPG bit MIN Æ HPL/HPR 0 (default) −20dB 1 −16.4dB Table 49. MIN Input Æ Headphone-Amp Output Gain (typ) at Ri = 20kΩ MS0670-E-00 2007/09 - 58 - [AK4673] ■ Stereo Line Output (LOUT/ROUT pins) When DACL bit is “1”, single-ended Lch/Rch signal of DAC is output from the LOUT/ROUT pins. When DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ (min.). When the PMLO=LOPS bits = “0”, the stereo line output enters power-down mode and the output is pulled-down to VSS1 by 100kΩ(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be pulled-down to VSS1 by 20kΩ after AC coupled as Figure 45. Rise/Fall time is 300ms(max) at C=1μF and AVDD=3.3V. When PMLO bit = “1” and LOPS bit = “0”, stereo line output is in normal operation. LOVL bit set the gain of stereo line output. When LOM bit = “1”, DAC output signal is output to LOUT and ROUT pins as (L+R)/2 mono signal. When LOM3 bit = “1”, the signal selected by MICL3 and MICR3 bits (LIN3/RIN3 inputs or MIC-Amp outputs) to LOUT and ROUT pins as (L+R)/2 mono signal. “DACL” “LOVL” LOUT pin DAC ROUT pin Figure 44. Stereo Line Output LOPS 0 1 PMLO Mode LOUT/ROUT pin 0 Power-down Pull-down to VSS1 1 Normal Operation Normal Operation 0 Power-save Fall down to VSS1 1 Power-save Rise up to VCOM Table 50. Stereo Line Output Mode Select (x: Don’t care) (default) LOVL Gain Output Voltage (typ) 0 0dB 0.6 x AVDD (default) 1 +2dB 0.757 x AVDD Table 51. Stereo Line Output Volume Setting LOUT ROUT 1μF 220Ω 20kΩ Figure 45. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit) MS0670-E-00 2007/09 - 59 - [AK4673] <Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)> (2 ) (5 ) P M L O b it (1 ) (3 ) (4 ) (6 ) L O P S b it L O U T , R O U T p in s N o r m a l O u tp u t ≥ 300 m s ≥ 300 m s Figure 46. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit) (1) Set LOPS bit = “1”. Stereo line output enters the power-save mode. (2) Set PMLO bit = “1”. Stereo line output exits the power-down mode. LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF and AVDD=3.3V. (3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode. Stereo line output is enabled. (4) Set LOPS bit = “1”. Stereo line output enters power-save mode. (5) Set PMLO bit = “0”. Stereo line output enters power-down mode. LOUT and ROUT pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V. (6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode. MS0670-E-00 2007/09 - 60 - [AK4673] <Analog Mixing Circuit for Stereo Line Output> When AIN3 bit = “0”, DACL, MINL, LINL2, RINR2, LINL4 and RINR4 bits controls each path switch. MIN path mixing gain is 0dB(typ)@LOVL bit = “0” when the external input resistance is 20kΩ. LIN2, RIN2, LIN4, RIN4 and DAC pathes mixing gain is 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB LIN4 pin 0dB LINL4 bit M MINL bit MIN pin 0dB I LOUT pin X DACL bit DAC Lch 0dB Figure 47. LOUT Mixing Circuit (AIN3 bit = “0”, LOVL bit = “0”) RINR2 bit RIN2 pin 0dB RINR4 bit RIN4 pin M 0dB MINL bit MIN pin 0dB I ROUT pin X DACL bit DAC Rch 0dB Figure 48. ROUT Mixing Circuit (AIN3 bit = “0”, LOVL bit = “0”) MS0670-E-00 2007/09 - 61 - [AK4673] When AIN3 bit = “1”, DACL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, MICL3 and MICR3 bits controls each path switch. All pathes mixing gain is 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB LINL4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINL3 bit I 0dB MIC-Amp Lch M *These blocks are not available at PLL mode. LOUT pin X DACL bit DAC Lch 0dB Figure 49. LOUT Mixing Circuit (AIN3 bit = “1”, LOVL bit = “0”) RINR2 bit RIN2 pin 0dB RINR4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RIN1 pin RINR3 bit I 0dB MIC-Amp Rch M *These blocks are not available at PLL mode. ROUT pin X DACL bit DAC Rch 0dB Figure 50. ROUT Mixing Circuit (AIN3 bit = “1”, LOVL bit = “0”) MS0670-E-00 2007/09 - 62 - [AK4673] ■ Full-differential Mono Line Output (LOP/LON pins) When LODIF bit = “1”, LOUT/ROUT pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins which is full-differential as (L+R)/2 signal. The load impedance is 10kΩ (min) for LOP and LON pins, respectively. When the PMLO bit = “0”, the mono line output enters power-down mode and the output is Hi-Z. When the PMLO bit is “1” and LOPS bit is “1”, mono line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = “0”. When PMLO bit = “1” and LOPS bit = “0”, mono line output enters in normal operation. LOVL bit set the gain of mono line output. When L4DIF=LODIF bits = “1”, full-differential output signal is as follows: (LOP) − (LON) = (IN4+) − (IN4−). “DACL” “LOVL” LOP pin DAC LON pin Figure 51. Mono Line Output LOVL 0 1 PMLO 0 1 Gain Output Voltage (typ) +6dB 1.2 x AVDD (default) +8dB 1.5 x AVDD Table 52. Mono Line Output Volume Setting LOPS Mode LOP LON x Power-down Hi-Z Hi-Z 1 Power-save Hi-Z VCOM/2 0 Normal Operation Normal Operation Normal Operation Table 53. Mono Line Output Mode Setting (x: Don’t care) (default) PMLO bit LOPS bit LOP pin LON pin Hi-Z Hi-Z Hi-Z VCOM VCOM Hi-Z Figure 52. Power-up/Power-down Timing for Mono Line Output MS0670-E-00 2007/09 - 63 - [AK4673] <Analog Mixing Circuit for Mono Line Output> When AIN3 bit = “0”, DACL, MINL, LINL2, RINR2, LINL4 and RINR4 bits controls each path switch. MIN path mixing gain is +6dB(typ)@LOVL bit = “0” when the external input resistance is 20kΩ. LIN2, RIN2, LIN4, RIN4 and DAC pathes mixing gain is 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB RIN2 pin 0dB RINR2 bit LINL4 bit LIN4 pin 0dB M RINR4 bit RIN4 pin LOP/N pin I 0dB X MINL bit MIN pin +6dB DACL bit DAC Lch 0dB DAC Rch 0dB DACL bit Figure 53. Mono Line Output Mixing Circuit (AIN3 bit = “0”, LOVL bit = “0”) When AIN3 bit = “1”, DACL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, MICL3 and MICR3 bits controls each path switch. All pathes mixing gain is 0dB(typ)@LOVL bit = “0”. LINL2 bit LIN2 pin 0dB LINL4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINL3 bit 0dB MIC-Amp Lch *These blocks are not available at PLL mode. RINR2 bit RIN2 pin M 0dB RINR4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RIN1 pin I LOP/N pin X RINR3 bit 0dB MIC-Amp Rch *These blocks are not available at PLL mode. DACL bit DAC Lch 0dB DACL bit DAC Rch 0dB Figure 54. Mono Line Output Mixing Circuit (AIN3 bit = “1”, LOVL bit = “0”) MS0670-E-00 2007/09 - 64 - [AK4673] ■ Headphone Output Power supply voltage for the Headphone-Amp is supplied from the HVDD pin and centered on the HVDD/2 voltage at VBAT bit = “0”. The load resistance is 16Ω (min). HPG bit selects the output voltage (Table 54). When HPM bit = “1”, DAC output signal is output to HPL and HPR pins as (L+R)/2 mono signal. When HPM3 bit = “1”, the signal selected by MICL3 and MICR3 bits (LIN3/RIN3 inputs or MIC-Amp outputs) to HPL and HPR pins as (L+R)/2 mono signal. HPG bit 0 1 Output Voltage [Vpp] 0.6 x AVDD 0.91 x AVDD Table 54. Headphone-Amp Output Voltage When the HPMTN bit is “0”, the common voltage of Headphone-Amp falls and the outputs (HPL and HPR pins) go to “L” (VSS2). When the HPMTN bit is “1”, the common voltage rises to HVDD/2 at VBAT bit = “0”. A capacitor between the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to HVDD voltage and the capacitor at the MUTET pin. [Example]: A capacitor between the MUTET pin and ground = 1.0μF, HVDD=3.3V: Rise/fall time constant: τ = 100ms(typ), 250ms(max) Time until the common goes to VSS2 when HPMTN bit = “1” Æ “0”: 500ms(max) When PMHPL and PMHPR bits are “0”, the Headphone-Amp is powered-down, and the outputs (HPL and HPR pins) go to “L” (VSS2). PMHPL bit, PMHPR bit HPMTN bit HPL pin, HPR pin (1) (2) (3) (4) Figure 55. Power-up/Power-down Timing for Headphone-Amp (1) Headphone-Amp power-up (PMHPL, PMHPR bit = “1”). The outputs are still VSS2. (2) Headphone-Amp common voltage rises up (HPMTN bit = “1”). Common voltage of Headphone-Amp is rising. (3) Headphone-Amp common voltage falls down (HPMTN bit = “0”). Common voltage of Headphone-Amp is falling. (4) Headphone-Amp power-down (PMHPL, PMHPR bit = “0”). The outputs are VSS2. If the power supply is switched off or Headphone-Amp is powered-down before the common voltage goes to VSS2, some POP noise occurs. <External Circuit of Headphone-Amp > When BOOST=OFF, the cut-off frequency (fc) of Headphone-Amp depends on the external resistor and capacitor. This fc can be shifted to lower frequency by using bass boost function. Table 55 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω. Output powers are shown at HVDD = 3.0, 3.3 and 5.0V. The output voltage of headphone is 0.6 x AVDD (Vpp) @HPG bit = “0” and 0.91 x AVDD (Vpp) @HPG bit = “1”. When an external resistor R is smaller than 12Ω, put an oscillation prevention circuit (0.22μF±20% capacitor and 10Ω±20% resistor) because it has the possibility that the Headphone-Amp oscillates. MS0670-E-00 2007/09 - 65 - [AK4673] HP-AMP C AK4673 0.22μ R Headphone 16Ω 10Ω Figure 56. External Circuit Example of Headphone HPG bit R [Ω] fc [Hz] BOOST =OFF C [μF] 220 100 100 0 6.8 47 100 16 47 220 0 100 1 22 100 10 Note 40. Output power at 16Ω load. Note 41. Output signal is clipped. 0 45 100 70 149 50 106 45 100 62 137 fc [Hz] BOOST =MIN @fs=44.1kHz 17 43 28 78 19 47 17 43 25 69 Output Power [mW]@0dBFS HVDD=3.0V AVDD=3.0V HVDD=3.3V AVDD=3.3V HVDD=5V AVDD=3.3V 25.3 30.6 30.6 12.5 15.1 15.1 6.3 7.7 7.7 51 (Note 41) 62 (Note 41) 70 1.1 1.3 1.3 Table 55. External Circuit Example <Headphone-Amp PSRR> When HVDD is directly supplied from the battery in the mobile phone system, RF noise may influences headphone output performance. When VBAT bit is set to “1”, HP-Amp PSRR for the noise applied to HVDD is improved. In this case, HP-Amp common voltage is 0.64 x AVDD (typ). When AVDD is 3.3V, common voltage is 2.1V. Therefore, when HVDD voltage becomes lower than 4.2V, the output signal will be clipped easily. VBAT bit Common Voltage [V] 0 0.5 x HVDD Table 56. HP-Amp Common Voltage 1 0.64 x AVDD <Wired OR with External Headphone-Amp> When PMVCM=PMHPL=PMHPR bits = “0” and HPZ bit = “1”, HP-Amp is powered-down and HPL/R pins are pulled-down to VSS2 by 200kΩ (typ). In this setting, it is available to connect HP-Amp of AK4673 and external single supply HP-Amp by “wired OR”. In this mode, power supply current is 20μA(typ). PMVCM x 0 1 1 PMHPL/R 0 0 1 1 HPMTN HPZ Mode x 0 Power-down & Mute x 1 Power-down 0 x Mute 1 x Normal Operation Table 57. HP-Amp Mode Setting (x: Don’t care) MS0670-E-00 HPL/R pins VSS2 Pull-down by 200kΩ VSS2 Normal Operation (default) 2007/09 - 66 - [AK4673] HPL pin AK4673 Headphone HPR pin Another HP-Amp Figure 57. Wired OR with External HP-Amp <Analog Mixing Circuit for Headphone Output> When AIN3 bit = “0”, DACH, MINH, LINH2, RINH2, LINH4 and RINH4 bits controls each path switch. MIN path mixing gain is −20dB(typ)@HPG bit = “0” when the external input resistance is 20kΩ. LIN2, RIN2, LIN4, RIN4 and DAC pathes mixing gain is 0dB(typ)@HPG bit = “0”. LINH2 bit LIN2 pin 0dB LINH4 bit LIN4 pin M 0dB MINH bit −20dB MIN pin I HPL pin X DACH bit DAC Lch 0dB Figure 58. HPL Mixing Circuit (AIN3 bit = “0”, HPG bit = “0”) RINH2 bit RIN2 pin 0dB RINH4 bit RIN4 pin M 0dB MINH bit −20dB MIN pin I HPR pin X DACH bit DAC Rch 0dB Figure 59. HPR Mixing Circuit (AIN3 bit = “0”, HPG bit = “0”) MS0670-E-00 2007/09 - 67 - [AK4673] When AIN3 bit = “1”, DACH, LINH2, RINH2, LINH3, RINH3, LINH4, RINH4, MICL3 and MICR3 bits controls each path switch. All pathes mixing gain is 0dB(typ)@HPG bit = “0”. LINH2 bit LIN2 pin 0dB LINH4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINH3 bit I 0dB MIC-Amp Lch M *These blocks are not available at PLL mode. HPL pin X DACH bit DAC Lch 0dB Figure 60. HPL Mixing Circuit (AIN3 bit = “1”, HPG bit = “0”) RINH2 bit RIN2 pin 0dB RINH4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RIN1 pin RINH3 bit I 0dB MIC-Amp Rch M *These blocks are not available at PLL mode. HPR pin X DACH bit DAC Rch 0dB Figure 61. HPR Mixing Circuit (AIN3 bit = “1”, HPG bit = “0”) MS0670-E-00 2007/09 - 68 - [AK4673] TSC OPERATION OVERVIEW ■ A/D Converter for Touch Screen The AK4673 incorporates a 12-bit successive approximation resistor (SAR) A/D converter for position measurement. The architecture is based on a capacitive redistribution algorithm, and an internal capacitor array functions as the sample/hold (S/H) circuit. The SAR A/D converter output is a straight binary format as shown below: Input Voltage Output Code FFFH (ΔVREF-1.5LSB)~ ΔVREF FFEH (ΔVREF-2.5LSB) ~ (ΔVREF-1.5LSB) ----------------0.5LSB ~ 1.5LSB 001H 0 ~ 0.5LSB 000H ΔVREF: (VREF+) – (VREF-) Table 58 Output Code ■ The Block Diagram of TSC block Figure 62 shows the block diagram in touch screen controller block that consists of the 12bit ADC and control block of the driver switches and peninterrupt output. TSVDD XP Driver SW XP TSVDD YP Driver SW YP XN XN Driver SW YN YN Driver SW Control Logic Block VREF+ VREFAIN+ 12bit ADC AIN-(SAR type) PEN INTERRUPT TSVDD PENIRQN VSS3 Figure 62 Touch Screen Controller Block Diagram MS0670-E-00 2007/09 - 69 - [AK4673] ■ The Position Detection of Touch Screen A position detecting (X, Y position) on the touch panel is selected by the control command via the A2, A1, A0 bits in the control register. The mode of the position detecting is differential mode, the full scale (ΔVREF) is the differential voltage between the non-inverting terminal and the inverting terminal of the measured axis (e.g. X-axis measurement: ΔVREF = VXP – VXN). The voltage difference on the A/D converter (ΔAIN) is the voltage between non-inverting terminals of the non-measured axis and the inverting terminal of the measured axis. (E.g. ΔAIN= (AIN+) - (AIN-) = VYP-VXN) The voltage difference (ΔAIN) is charged to the internal capacitor array during the sampling period. No current flows into the internal capacitor after the capacitor has been charged completely. The required settling time to charge the internal capacitor array depends on the source impedance (Rin). If the source impedance is 600 ohm, the settling time needs at least 2.5μs (1 clock cycle period of SCL 400 KHz) The position on the touch screen is detected by taking the voltage of one axis when the voltage is supplied between the two terminals of another axis. At least two A/D conversions are needed to get the two-dimensional (X/Y axis) position. TSVDD TSVDD X-Plate XP-Driver SW ON XP VREF+ XP Y-Plate AIN+ VREF+ YP ADC VREF- X-Plate YP-Driver SW ON AIN+ YP ADC VREF- AIN- Y-Plate AIN- XN XN XN-Driver SW ON YN YN Touch Screen YN-Driver SW ON a) X-Position Measurement Differential Mode b) Y-Position Measurement Differential Mode The X-plate and Y-plate are connected on the dotted line when the panel is touched. XP X-Plate (Top side) XN Y-Plate (Bottom side) YN YP c) 4-wire Touch Screen Construction Figure 63 Axis Measurements The differential mode position detection is typically more accurate than the single-ended mode. As the full scale of single-ended mode is fixed to the VCC, input voltage may exceed the full-scale reference voltage. This problem does not occur in differential mode. In addition to this, the differential mode is less influenced by power supply voltage variation due to the ratio-metric measurement. MS0670-E-00 2007/09 - 70 - [AK4673] ■ The Pen Pressure Measurement The touch screen pen pressure can be derived from the measurement of the contact resistor between two plates. The contact resistance depends on the size of the depressed area and the pressure. The area of the spot is proportional to the contact resistance. This resistance (Rtouch) can be calculated using two different methods. The first method is applied when the total resistance of the X-plate sheet is already known. The resistance, Rtouch, is calculated from the results of three conversions, X-position, Z1-Position, and Z2-Position, and then using the following formula: Rtouch = (Rxplate) * (Xposition/4096) * [(Z2/Z1) – 1] The second method is applied when both the resistances of the X-plate and Y-plate are known. The resistance, Rtouch, is calculated from the results of three conversions, X-position, Y-Position, and Z1-Position, and then using the following formula: Rtouch = (Rxplate*Xposition/4096)*[(4096/Z1) – 1] – Ryplate*[1 – (Yposition/4096)] TSVDD TSVDD YP-Driver SW ON YP-Driver SW ON YP XP VREF+ YP Rtouch XP AIN+ ADC VREF+ AIN+ VREF- AIN- Rtouch ADC VREF- AIN- XN XN-Driver SWON XN XN-Driver SW ON YN a) YN b) Z1-Position Measurement Z2-Position Measurement Figure 64 Pen Pressure Measurements MS0670-E-00 2007/09 - 71 - [AK4673] ■ Digital I/F The AK4673 operates with uP via I2C bus and supports the standard-mode (100 KHz) and the fast-mode (400KHz). Please note that the AK4673 operates in those two modes and does not support a High speed mode I2C-bus system (3.4MHz). The AK4673 can operate as a slave device on the I2C bus network. TSVDD=2.6V – 3.6V CADT MicroProcessor I2C bus controller Rp Rp TSVDD “L” or “H” AK4673 SCL SDA PENIRQN Figure 65 Digital I/F ■ Serial Control Interface The AK4673 supports the fast-mode I2C-bus (max: 400 kHz). Pull-up resistors at the SDA and the SCL pins should be connected to (TVDD1/ TSVDD +0.3) V or less voltage. The TVDD1 pin and the TSVDD pin should be connected together on the same I2C bus. [Start condition and Stop condition] A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start by the START condition or Repeated Start Condition. Repeated Start condition is the same signal tradition as Start condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences are terminated by the STOP or Repeated Start condition. Repeated Start is also the Start condition of next transfer so that I2C bus cannot be idle. SDA SCL S/Sr S : Start condition P : stop condition Sr : Repeated start condition Figure 66 START and STOP Conditions [Data transfer] All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4673 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the master device. [Data validity] The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition. MS0670-E-00 2007/09 - 72 - [AK4673] SDA SCL data line stable; data valid change of data allowed Figure 67 Bit Transfer on the I2C-Bus [ACKNOWLEDGE] ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4673 will generates an acknowledge after each byte is received. In the read mode, the slave, AK4673 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmitting the data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP condition. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 68 Acknowledge A) TSC Control [Address Byte] The sequence of writing data is shown Figure 71. The address byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If the transmitted slave address matches an address for one of the device, the receiver which was addressed pulls down the SDA line (acknowledge). The most significant six bits of the slave address are fixed as “100100”. The next one bit is CADT (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CADT pin) sets CADT bit. The eighth bit (LSB) of the address byte (R/W bit) defines whether the master requests a write or read operation. A “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. 1 0 0 1 0 0 CADT R/W (CADT should match with CADT pins) Figure 69 Address Byte MS0670-E-00 2007/09 - 73 - [AK4673] [WRITE Operations] The second byte that followed by address byte consists of the control command byte of the AK4673. The operational mode is determined by control command. The bit format is MSB first and 8 bits width. Control command is described in the Table 60. The AK4673 generates an acknowledge after each byte is received. A control command transfer is terminated by a STOP condition or Repeated Start condition generated by the master. Refer to the Table 60 in detail. P Command AK4673 ACK S Address AK4673 ACK SDA D0 X2 STOP R/W=”0” D6 D5 D4 D3 D2 D1 A2 A1 A0 X1 PD0 MODE Figure 70 Control Command Byte (X1, X2 : Don’t care) START D7 S Figure 71 Single Write Transmission Sequence [READ Operation] The operation mode is determined by the write command just before read operation. AK4673 features two methods of read operation, single read operation and continuous read operation. The continuous read operation is a series of single read operation. Each single read operation in continuous read operation makes the AK4673 updated A/D conversion on each read operation. Write operation does not need to issue before each read operations are executed. The channel selection of the AK4673 is defined by the control command just before READ operation. When the address byte with R/W = “1” read operations are executed. A/D readout format is MSB first, 1byte or 2bytes width. Upper 8bits are valid on 8-bit mode and upper 12 bits are valid, and lower 4 bits are filled with zero on 12-bit mode. STOP A/D data P MASTER NACK D0 D3 D4 A/D data MASTER ACK S Address AK4673 ACK SDA D11 START R/W=”1” [Single READ mode] Read operation begins with a START condition followed by the address byte with R/W= “1”. When the address matches address byte of the AK4673 (Figure 68), the AK4673 generates ACK. After transmission of the address byte, the master receives upper 8bit A/D data first, and generates ACK. The AK4673 transmits the remaining 4-bit A/D data and followed by 4-bit zero data (12bit mode). Master device receives 8bit A/D data (8bit mode). The master then generates NACK and stop condition or repeated start condition. Figure 72 Single A/D data Read Sequence (12-bit mode) MS0670-E-00 2007/09 - 74 - [AK4673] STOP D0 D3 D4 D11 AK4673 ACK A/D data A/D data N+X N+X P MASTER NACK Address MASTER NACK Sr MASTER ACK A/D data N R/W=”1” RESTART D0 D3 D4 D11 A/D data N MASTER ACK S Address AK4673 ACK SDA R/W=”1” START [Continuous Read mode] This continuous read operation enables the higher sampling rate and lower processor load than a single read operation. Because once control command is sent, it does not need to update control command on each read operation until another control command is rewritten. Repeat Figure 73 Continuous A/D data Read Sequence ■ Power on Sequence It is recommended that the control command must be sent to fix the internal register when power up. This initiates all registers such as A2-0 bit, PD0 bit, and MODE bit. Once sending command to fix the internal register after first power up, the state of the AK4673 is held on the known-condition of state to ensure that the AK4673 is going into desire mode to realize lowest mode. A command with PD0= “0” should be sent so that the AK4673 will be set in the lowest power down mode. ■ Sleep mode The AK4673 supports the sleep mode that enables touch panel interface to put open state and disables pen interrupt function. The AK4673 goes into the sleep mode when control command is sent to the AK4673 as shown Table 59. The selection of the sleep mode is set by “MODE” bit of the control command. The state of both the output of the PENIRQN pin and the connection with touch panel interface (XP, YP, XN, and YN) are the following Table 59. AK4673 keeps the sleep mode until next control command is sent. Command 0111XX1X 0111XX0X MODE bit PENIRQN 1 Hi-z 0 “H” output Table 59 Sleep Command Setting Touch panel Open Open The timing of going into the sleep mode is the rising edge of the 16th SCL of the write operation. A/D conversion does not execute when the sleep command is sent. The SDA pin is “H” since SDA is pull up. In order to go to normal mode from sleep mode, the command (S= “1”) is sent. The timing of going back to normal mode is the rising edge of the 16thSCL. When the sleep command is sent again under the sleep mode the mode continues the same as before. The initial state after power up is in normal mode. MS0670-E-00 2007/09 - 75 - [AK4673] ■ Control Command The control command, 8 bits, provided to the AK4673 via SDA, is shown in the following table. This command includes start bit, channel selection bit, power-down bit and resolution bit. The AK4673 latches the serial command at the rising edge of SCL. Refer to the detailed information regarding the bit order, function, the status of driver switch, ADC input as shown in Table 60. BIT 7 6-4 Name S A2-A0 3 2 1 X1 PD0 MODE 0 X2 Function Start Bit. “1” Accelerate and Axis Command, “0”: Sleep mode Command Channel Selection Bits. Analog inputs to the A/D converter and the activated driver switches are selected. Please see the following table for the detail. Don’t care Power down bit (refer to power-down control) Resolution of A/D converter. “0”: 12 bit output “1”: 8 bit output when S bit is “1”. Sleep mode selection when S bit is “0”. Don’t care Input Status of Driver Switch YN ADC input (ΔAIN) S A2 A1 A0 XP XN YP 0 1 1 0 1 0 1 0 ON ON 1 0 0 1 OFF OFF 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 OFF ON ON OFF XP XN OFF ON ON OFF YN XN ON ON OFF OFF YP XN OFF OFF ON ON XP YN OFF ON ON OFF XP (Z1) XN OFF ON ON OFF YN XN (Z2) Table 60 Control Command List Reference Voltage (ΔVREF) VREF+ VREF - AIN+ AIN- OFF OFF YP XN XP XN ON XP YN YP YN YP YP XP YP YP YP XN XN XN YN XN XN ON Note Sleep Accelerate X-Driver Accelerate Y-Driver Accelerate Y+, X- Driver X-axis Y-axis Z1 (Pen Pressure) Z2 (Pen Pressure) ■ Power-down Control A/D converter and power-down control of touch driver switch are determined by PD0 bit. PD0 0 PENIRQN Enabled 1 Disabled Function Auto power-down Mode A/D converter is automatically powered up at the start of the conversion, and goes to power- down state automatically at the end of the conversion. All touch screen driver switches except for YN switch are turned off and relative pins are open state. Only YN driver switch is turned ON and the YN pin is forced to the ground in this case. PEN interrupt function is enabled except for the sampling time and conversion time. ADC ON Mode When X-axis or Y-axis are selected on the write operation with PD0 = “1” A/D converter and touch panel driver are always powered up until next conversion. This mode is effective if more settling time is required to suppress the electrical bouncing of touch plate. PEN interrupt function is disabled and PENIRQN is forced to “L” state Table 61 Power –Down Control MS0670-E-00 2007/09 - 76 - [AK4673] ■ WRITE Operation Sequence The selection of channel input of the AK4673 is determined by a command byte. When accelerate command (A2= “0”) is sent, the switch on timing of the driver switch is 18th falling edge of SCL regardless of PD0 bit. The accelerate command is to accelerate the timing of desired driver SW ON to ensure that AK4673 needs more settling time. Actually sampling timing is on the time of READ operation, it is possible to take settling time longer even when the impedance of the touch screen is large. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 18 SCL Command Byte Address Byte R/ W 1 SDA 0 0 1 0 0 0 CAD0 S 0 A2 A1 A0 PD0 X1 MODE AK4673 ACK START Touch Driver SW A2=0, PD0=0 or 1 A2=1, PD0=1 0 X2 AK4673 ACK STOP A2=1, PD0=0 I II III IV Figure 74 write operation and Driver SW timing ■ READ Operation Sequence A/D conversion is synchronized with SCL. Sampling time is the one SCL clock period (SCL7↓∼ SCL8↓) on the end of writing address byte and then hold. A/D conversion is held on the next 12 SCL period (except MASTER ACK). After address byte is sent, the readout sequence starts with an acknowledge, which is the responce of the AK4673 when the address maches. The MSB data byte will follow (D11∼D4) then issued acknowledge by master. The LSB data byte (D3∼D0, followed four “0”) will be followed by NOT acknowledge bit (NACK) from master in order to terminate the read transfer. The master will then issued STOP that ends read operation or Repeated Start condition that keeps write or read operation. The master will issue Repeated Start Condition or START condition followed by read operation again. AK4673 repeats A/D data updated [continuous read operation]. Master must issue STOP condition after terminating the last read out of A/D data. 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 0 0 27 28 SCL R/ W 1 SDA 0 0 1 0 0 CAD0 1 D11 0 D10 D9 D8 D7 D6 AK4673 ACK START Address Byte D5 D4 D3 D2 D1 D0 0 0 1 MASTER NACK STOP or MASTER ACK Data Byte (MSB) Sampling 0 Repeated START Data Byte (LSB) AD conversion Touch Driver SW “H” A2=“0” or A2=“1” , PD0=“1” A2=“0”, PD0=“0” A2=“1”, PD0=“0” IV V VI Figure 75 Read data Sequence MS0670-E-00 2007/09 - 77 - [AK4673] ■ Pen Interrupt The AK4673 has a pen-interrupt function to detect the pen touch on the touch panel. This function will be used as the interrupt of the microprocessor. Pen interrupt function is enabled at power-down state. YN driver is on and this pin is connected to GND at the power down state. And the XP pin is pulled up via an internal resister (Ri), typically 10KΩ. If the touch plate is touched by pen or stylus, the current flows via <VCC>-<Ri>-<XP>-<the plates>-<YN>-<GND>. The resistance of the plate is generally 1KΩ or less, the PENIQRN pin is force to “L” level. If the pen is released, the PENIRQN pin returns “H” level because two plates are disconnected, and the current does not flow via two plates. The transition of PENIRQN is related to PD0 bit. PD0 bit is updated as shown below. (Please see “power-down control” for the detail. Once the control command PD0= “1” is sent the pen-interrupt function is disabled. The clock number under the write and the read operation refer to Figure 74 and Figure 14. I. The period from start condition to SCL7↓ The level transition of the PENIRQN pin is determined by PD0 bit of the previous command. When the previous command with PD0= “0” the pen-interrupt function will be enabled. The PENIRQN pin is low when the panel is touch, the PENIRQN pin is “H” when the panel is untouched. When the previous command with PD0= “1” is sent PENIRQN pin is low regardless of pen-touch II. The period SCL7↓ to SCL8↑ on the write operation The level of the PENIRQN pin is always low regardless of PD0 bit and the state of panel (touched/untouched) III. The period from SCL8↑ to SCL18↓ on the write operation The level transition of the PENIRQN pin is determined by PD0 bit of the previous command. When the previous command with PD0= “0” the pen-interrupt function will be enabled. The PENIRQN pin is low when the panel is touch, the PENIRQN pin is “H” when the panel is untouched. When the previous command with PD0= “1” is sent PENIRQN pin is low regardless of pen-touch IV. The period from SCL18↓ on the write operation to SCL7↓ on the read operation The level of PENIRQN pin is determined by the A2 bit and PD0 bit of the present command. The PENIRQN pin is always low regardless pen-touch when command with A2 = “1” or PD0 = “1” is set. The PENIRQN is determined by the pen-touch (touched/untouched) when command with A2= “1” and PD0= “1” is sent. V. The period from SCL7↓ to SCL21↓ on the write operation The AD input will sample the hold and the conversion will be done during this period. PENIRQN is always low. VI. The period after SCL21↓ on the read operation The level transition of the PENIRQN pin is determined by PD0 bit of the present command. When the present command PD0= “0” is sent the pen-interrupt function will be enabled. The PENIRQN pin is low when the panel is touched. The PENIRQN pin is “H” when the panel is untouched. When the present command PD0= “1” are sent the PENIRQN pin is low regardless of pen-touch. It is recommended that the processor will mask the pseudo interrupt while the control command is issued or AD data is sent to processor. PENIRQN VCC To uP PEN Interrupt VCC Ri = 10kΩ VCC EN2 Driver OFF XP EN1 YN Driver ON Figure 76 Pen interrupt function block MS0670-E-00 2007/09 - 78 - [AK4673] B) Audio Control (1)-1. WRITE Operations Figure 77 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 66). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CADA (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CADA pin) sets these device address bits (Figure 78). If the slave address matches that of the AK4673, the AK4673 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 68). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4673. The format is MSB first, and those most significant 2-bits are fixed to zeros (Figure 79). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 80). The AK4673 generates an acknowledge after each byte is received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 66). The AK4673 can perform more than one byte write operation per sequence. After receiving of the third byte the AK4673 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 24H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. STOP Data(n+1) Data(n+x) P MASTER ACK Data(n) MASTER ACK Sub Address(n) MASTER ACK Slave Address MASTER ACK S AK4673 ACK SDA MASTER ACK START R/W="0" The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only be changed when the clock signal on the SCL line is LOW (Figure 67) except for the START and STOP conditions. Figure 77. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 1 CADA R/W A2 A1 A0 D2 D1 D0 ( CADA should match with CADA pins) Figure 78. The First Byte 0 0 A5 A4 A3 Figure 79. The Second Byte D7 D6 D5 D4 D3 Figure 80. Byte Structure after the second byte MS0670-E-00 2007/09 - 79 - [AK4673] (1)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4673. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after receiving of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 24H prior to generating a stop condition, the address counter will “roll over” to 00H and the data of 00H will be read out. The AK4673 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. STOP Data(n+2) Data(n+x) P MASTER NACK Data(n+1) MASTER ACK Data(n) MASTER ACK Slave Address MASTER ACK S AK4673 ACK SDA MASTER ACK START R/W="1" (1)-2-1. CURRENT ADDRESS READ The AK4673 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address n+1. After receiving of the slave address with R/W bit set to “1”, the AK4673 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4673 ceases transmission. Figure 81. CURRENT ADDRESS READ Data(n+1) Data(n+x) P MASTER NACK Data(n) MASTER ACK Slave Address MASTER ACK S MASTER ACK Sub Address(n) STOP R/W="1" START Slave Address AK4673 ACK S AK4673 ACK SDA AK4673 ACK START R/W="0" (1)-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4673 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4673 ceases transmission. Figure 82. RANDOM ADDRESS READ MS0670-E-00 2007/09 - 80 - [AK4673] ■ Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 Rch Input Volume Control Rch Digital Volume Control Mode Control 3 Mode Control 4 Power Management 3 Digital Filter Select FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Power Management 4 Mode Control 5 Lineout Mixing Select HP Mixing Select Reserved D7 0 HPZ 0 LOVL PLL3 PS1 DVTM 0 REF7 D6 PMVCM HPMTN 0 LOPS PLL2 PS0 WTM2 0 REF6 D5 PMMIN PMHPL 0 MGAIN1 PLL1 FS3 ZTM1 ALC REF5 D4 0 PMHPR DACL 0 PLL0 MSBS ZTM0 ZELMN REF4 D3 PMLO M/S 0 0 BCKO BCKP WTM1 LMAT1 REF3 D2 PMDAC 0 PMMP MINL 0 FS2 WTM0 LMAT0 REF2 D1 0 MCKO 0 0 DIF1 FS1 RFST1 RGAIN0 REF1 D0 PMADL PMPLL MGAIN0 0 DIF0 FS0 RFST0 LMTH0 REF0 IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 DVL7 RGAIN1 IVR7 DVR7 0 0 INR1 GN1 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 DVL6 LMTH1 IVR6 DVR6 LOOP 0 INL1 GN0 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 DVL5 0 IVR5 DVR5 SMUTE 0 HPG 0 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 DVL4 0 IVR4 DVR4 DVOLC 0 MDIF2 FIL1 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 DVL3 0 IVR3 DVR3 BST1 IVOLC MDIF1 EQ F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 DVL2 0 IVR2 DVR2 BST0 HPM INR0 FIL3 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 DVL1 VBAT IVR1 DVR1 DEM1 MINH INL0 0 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 PMAINR4 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL 0 LOM 0 0 0 LOM3 HPM3 0 MICR3 RINR4 RINH4 0 MICL3 LINL4 LINH4 0 L4DIF RINR3 RINH3 0 MIX LINL3 LINH3 0 AIN3 RINR2 RINH2 0 LODIF LINL2 LINH2 0 Note 42. PDN pin = “L” resets the registers to their default values. Note 43. Unused bits must contain a “0” value. MS0670-E-00 2007/09 - 81 - [AK4673] ■ Register Definitions Addr 00H Register Name Power Management 1 Default D7 0 0 D6 PMVCM 0 D5 PMMIN 0 D4 0 0 D3 PMLO 0 D2 PMDAC 0 D1 0 0 D0 PMADL 0 PMADL: MIC-Amp Lch and ADC Lch Power Management 0: Power-down (default) 1: Power-up When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms @44.1kHz) starts. After initializing, digital data of the ADC is output. PMDAC: DAC Power Management 0: Power-down (default) 1: Power-up PMLO: Stereo Line Out Power Management 0: Power-down (default) 1: Power-up PMMIN: MIN Input Power Management 0: Power-down (default) 1: Power-up PMMIN or PMAINL3 bit should be set to “1” for playback. PMVCM: VCOM Power Management 0: Power-down (default) 1: Power-up When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only when all power management bits of 00H, 01H, 02H, 10H, 20H and MCKO bits are “0”. Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all blocks are powered-down regardless of setting of this address. In this case, register is initialized to the default value. When all power management bits are “0” in the 00H, 01H, 02H, 10H and 20H addresses and MCKO bit is “0”, all blocks are powered-down. The register values remain unchanged. Power supply current is 20μA(typ) in this case. For fully shut down (typ. 1μA), the PDN pin should be “L”. When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks must always be present. MS0670-E-00 2007/09 - 82 - [AK4673] Addr 01H Register Name Power Management 2 Default D7 HPZ 0 D6 HPMTN 0 D5 PMHPL 0 D4 PMHPR 0 D3 M/S 0 D2 0 0 D1 MCKO 0 D4 DACL 0 D3 0 0 D2 PMMP 0 D1 0 0 D0 PMPLL 0 PMPLL: PLL Power Management 0: EXT Mode and Power-Down (default) 1: PLL Mode and Power-up MCKO: Master Clock Output Enable 0: Disable: MCKO pin = “L” (default) 1: Enable: Output frequency is selected by PS1-0 bits. M/S: Master / Slave Mode Select 0: Slave Mode (default) 1: Master Mode PMHPR: Headphone-Amp Rch Power Management 0: Power-down (default) 1: Power-up PMHPL: Headphone-Amp Lch Power Management 0: Power-down (default) 1: Power-up HPMTN: Headphone-Amp Mute Control 0: Mute (default) 1: Normal operation HPZ: Headphone-Amp Pull-down Control 0: Shorted to GND (default) 1: Pulled-down by 200kΩ (typ) Addr 02H Register Name Signal Select 1 Default D7 0 0 D6 0 0 D5 0 0 D0 MGAIN0 1 MGAIN1-0: MIC-Amp Gain Control (Table 23) MGAIN1 bit is D5 bit of 03H. PMMP: MPWR pin Power Management 0: Power-down: Hi-Z (default) 1: Power-up DACL: Switch Control from DAC to Line Output 0: OFF (default) 1: ON When PMLO bit is “1”, DACL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to VSS1. MS0670-E-00 2007/09 - 83 - [AK4673] Addr 03H Register Name Signal Select 2 Default D7 LOVL 0 D6 LOPS 0 D5 D4 0 0 MGAIN1 0 D3 0 0 D2 MINL 0 D1 0 0 D0 0 0 MINL: Switch Control from MIN pin to Stereo Line Output 0: OFF (default) 1: ON When PMLO bit is “1”, MINL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to VSS1. MGAIN1: MIC-Amp Gain Control (Table 23) LOPS: Stereo Line Output Power-Save Mode 0: Normal Operation (default) 1: Power-Save Mode LOVL: Stereo Line Output Gain Select (Table 51, Table 52) 0: 0dB/+6dB (default) 1: +2dB/+8dB Addr 04H Register Name Mode Control 1 Default D7 PLL3 0 D6 PLL2 0 D5 PLL1 0 D4 PLL0 0 D3 BCKO 0 D2 0 0 D1 DIF1 1 D0 DIF0 0 D4 MSBS 0 D3 BCKP 0 D2 FS2 0 D1 FS1 0 D0 FS0 0 DIF1-0: Audio Interface Format (Table 17) Default: “10” (Left justified) BCKO: BICK Output Frequency Select at Master Mode (Table 11) PLL3-0: PLL Reference Clock Select (Table 5) Default: “0000”(LRCK pin) Addr 05H Register Name Mode Control 2 Default D7 PS1 0 D6 PS0 0 D5 FS3 0 FS3-0: Sampling Frequency Select (Table 6 and Table 7.) and MCKI Frequency Select (Table 12.) FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode. BCKP: BICK Polarity at DSP Mode (Table 18) “0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (default) “1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”). MSBS: LRCK Polarity at DSP Mode (Table 18) “0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (default) “1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change. PS1-0: MCKO Output Frequency Select (Table 10) Default: “00”(256fs) MS0670-E-00 2007/09 - 84 - [AK4673] Addr 06H Register Name Timer Select Default D7 DVTM 0 D6 WTM2 0 D5 ZTM1 0 D4 ZTM0 0 D3 WTM1 0 D2 WTM0 0 D1 RFST1 0 D0 RFST0 0 D2 LMAT0 0 D1 RGAIN0 0 D0 LMTH0 0 D2 REF2 0 D1 REF1 0 D0 REF0 1 RFST1-0: ALC First recovery Speed (Table 34) Default: “00”(4times) WTM2-0: ALC Recovery Waiting Period (Table 31.) Default: “000” (128/fs) ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 30.) Default: “00” (128/fs) DVTM: Digital Volume Transition Time Setting (Table 40.) 0: 1061/fs (default) 1: 256/fs This is the transition time between DVL/R7-0 bits = 00H and FFH. Addr 07H Register Name ALC Mode Control 1 Default D7 0 0 D6 0 0 D5 ALC 0 D4 ZELMN 0 D3 LMAT1 0 LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 28.) Default: “00” LMTH1 bit is D6 bit of 0BH. RGAIN1-0: ALC Recovery GAIN Step (Table 32.) Default: “00” RGAIN1 bit is D7 bit of 0BH. LMAT1-0: ALC Limiter ATT Step (Table 29.) Default: “00” ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (default) 1: Disable ALC: ALC Enable 0: ALC Disable (default) 1: ALC Enable Addr 08H Register Name ALC Mode Control 2 Default D7 REF7 1 D6 REF6 1 D5 REF5 1 D4 REF4 0 D3 REF3 0 REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (Table 33.) Default: “E1H” (+30.0dB) MS0670-E-00 2007/09 - 85 - [AK4673] Addr 09H 0CH Register Name Lch Input Volume Control Rch Input Volume Control Default D7 IVL7 IVR7 1 D6 IVL6 IVR6 1 D5 IVL5 IVR5 1 D4 IVL4 IVR4 0 D3 IVL3 IVR3 0 D2 IVL2 IVR2 0 D1 IVL1 IVR1 0 D0 IVL0 IVR0 1 IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 36.) Default: “E1H” (+30.0dB) Addr 0AH 0DH Register Name Lch Digital Volume Control Rch Digital Volume Control Default D7 DVL7 DVR7 0 D6 DVL6 DVR6 0 D5 DVL5 DVR5 0 D4 DVL4 DVR4 1 D3 DVL3 DVR3 1 D2 DVL2 DVR2 0 D1 DVL1 DVR1 0 D0 DVL0 DVR0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 VBAT 0 D0 0 0 D2 BST0 0 D1 DEM1 0 D0 DEM0 1 DVL7-0, DVR7-0: Output Digital Volume (Table 39.) Default: “18H” (0dB) Addr 0BH Register Name ALC Mode Control 3 Default D7 RGAIN1 0 D6 LMTH1 0 VBAT: HP-Amp Common Voltage (Table 56.) 0: 0.5 x HVDD (default) 1: 0.64 x AVDD LMTH1: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 28.) RGAIN1: ALC Recovery GAIN Step (Table 32.) Addr 0EH Register Name Mode Control 3 Default D7 0 0 D6 LOOP 0 D5 SMUTE 0 D4 DVOLC 1 D3 BST1 0 DEM1-0: De-emphasis Frequency Select (Table 37) Default: “01” (OFF) BST1-0: Bass Boost Function Select (Table 38) Default: “00” (OFF) DVOLC: Output Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When DVOLC bit = “1”, DVL7-0 bits control both Lch and Rch volume level, while register values of DVL7-0 bits are not written to DVR7-0 bits. When DVOLC bit = “0”, DVL7-0 bits control Lch level and DVR7-0 bits control Rch level, respectively. SMUTE: Soft Mute Control 0: Normal Operation (default) 1: DAC outputs soft-muted LOOP: Digital Loopback Mode 0: SDTI → DAC (default) 1: SDTO → DAC MS0670-E-00 2007/09 - 86 - [AK4673] Addr 0FH Register Name Mode Control 4 Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 IVOLC 1 D2 HPM 0 D1 MINH 0 D0 DACH 0 DACH: Switch Control from DAC to Headphone-Amp 0: OFF (default) 1: ON MINH: Switch Control from MIN pin to Headphone-Amp 0: OFF (default) 1: ON HPM: Headphone-Amp Mono Output Select 0: Stereo (default) 1: Mono When the HPM bit = “1”, DAC output signal is output to Lch and Rch of the Headphone-Amp as (L+R)/2. IVOLC: Input Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0 bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits control Rch level, respectively. Addr 10H Register Name Power Management 3 Default D7 INR1 0 D6 INL1 0 D5 HPG 0 D4 MDIF2 0 D3 MDIF1 0 D2 INR0 0 D1 INL0 0 D0 PMADR 0 PMADR: MIC-Amp Lch and ADC Rch Power Management 0: Power-down (default) 1: Power-up INL1-0: ADC Lch Input Source Select (Table 20) Default: 00 (LIN1 pin) INR1-0: ADC Rch Input Source Select (Table 20) Default: 00 (RIN1 pin) MDIF1: Single-ended / Full-differential Input Select 1 0: Single-ended input (LIN1/RIN1 pins: Default) 1: Full-differential input (IN1+/IN1− pins) MDIF1 bit selects the input type of pins #32 and #31. MDIF2: Single-ended / Full-differential Input Select 2 0: Single-ended input (LIN2/RIN2 pins: Default) 1: Full-differential input (IN2+/IN2− pins) MDIF2 bit selects the input type of pins #30 and #29. HPG: Headphone-Amp Gain Select (Table 54.) 0: 0dB (default) 1: +3.6dB MS0670-E-00 2007/09 - 87 - [AK4673] Addr 11H Register Name Digital Filter Select Default D7 GN1 0 D6 GN0 0 D5 0 0 D4 FIL1 0 D3 EQ 0 D2 FIL3 0 D1 0 0 D0 0 0 GN1-0: Gain Select at GAIN block (Table 26.) Default: “00” FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are enabled. When FIL3 bit is “0”, FIL3 block is OFF (MUTE). EQ: EQ (Gain Compensation Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ bit is “1”, the settings of EQA15-0, EQB13-0 and EQC15-0 bits are enabled. When EQ bit is “0”, EQ block is through (0dB). FIL1: FIL1 (Wind-noise Reduction Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL1 bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When FIL1 bit is “0”, FIL1 block is through (0dB). Addr 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Default D7 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 0 D6 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 0 D5 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 0 D4 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 0 D3 F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 0 D2 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 0 D1 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 0 D0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 0 F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2) Default: “0000H” F3AS: FIL3 (Stereo Separation Emphasis Filter) Select 0: HPF (default) 1: LPF EQA15-0, EQB13-0, EQC15-C0: EQ (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1) Default: “0000H” F1A13-0, F1B13-B0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2) Default: “0000H” F1AS: FIL1 (Wind-noise Reduction Filter) Select 0: HPF (default) 1: LPF MS0670-E-00 2007/09 - 88 - [AK4673] Addr 20H Register Name Power Management 4 Default D7 D6 D5 D4 D3 D2 D1 D0 PMAINR4 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL 0 0 0 0 0 0 0 0 PMMICL: MIC-Amp Lch Power Management 0: Power down (default) 1: Power up PMMICR: MIC-Amp Rch Power Management 0: Power down (default) 1: Power up PMAINL2: LIN2 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINR2: RIN2 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINL3: LIN3 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINR3: RIN3 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINL4: LIN4 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINR4: RIN4 Mixing Circuit Power Management 0: Power down (default) 1: Power up MS0670-E-00 2007/09 - 89 - [AK4673] Addr 21H Register Name Mode Control 5 Default D7 0 0 D6 0 0 D5 MICR3 0 D4 MICL3 0 D3 L4DIF 0 D2 MIX 0 D1 AIN3 0 D0 LODIF 0 LODIF: Lineout Select 0: Single-ended Stereo Line Output (LOUT/ROUT pins) (default) 1: Full-differential Mono Line Output (LOP/LON pins) AIN3: Analog Mixing Select 0: Mono Input (MIN pin) (default) 1: Stereo Input (LIN3/RIN3 pins): PLL is not available. MIX: Mono Recording 0: Stereo (default) 1: Mono: (L+R)/2 L4DIF: Line Input Type Select 0: Stereo Single-ended Input: LIN4/RIN4 pins (default) 1: Mono Full-differential Input: IN4+/− pins MICL3: Switch Control from MIC-Amp Lch to Analog Output 0: LIN3 input signal is selected. (default) 1: MIC-Amp Lch output signal is selected. MICR3: Switch Control from MIC-Amp Rch to Analog Output 0: RIN3 input signal is selected. (default) 1: MIC-Amp Rch output signal is selected. MS0670-E-00 2007/09 - 90 - [AK4673] Addr 22H Register Name Lineout Mixing Select Default D7 LOM 0 D6 LOM3 0 D5 RINR4 0 D4 LINL4 0 D3 RINR3 0 D2 LINL3 0 D1 RINR2 0 D0 LINL2 0 LINL2: Switch Control from LIN2 pin to Stereo Line Output (without MIC-Amp) 0: OFF (default) 1: ON RINR2: Switch Control from RIN2 pin to Stereo Line Output (without MIC-Amp) 0: OFF (default) 1: ON LINL3: Switch Control from LIN3 pin (or MIC-Amp Lch) to Stereo Line Output 0: OFF (default) 1: ON RINR3: Switch Control from RIN3 pin (or MIC-Amp Lch) to Stereo Line Output 0: OFF (default) 1: ON LINL4: Switch Control from LIN4 pin to Stereo Line Output (without MIC-Amp) 0: OFF (default) 1: ON RINR4: Switch Control from RIN4 pin to Stereo Line Output (without MIC-Amp) 0: OFF (default) 1: ON LOM3: Mono Mixing from MIC-Amp (or LIN3/RIN3) to Stereo Line Output 0: Stereo Mixing (default) 1: Mono Mixing LOM: Mono Mixing from DAC to Stereo Line Output 0: Stereo Mixing (default) 1: Mono Mixing MS0670-E-00 2007/09 - 91 - [AK4673] Addr 23H Register Name HP Mixing Select Default D7 0 0 D6 HPM3 0 D5 RINH4 0 D4 LINH4 0 D3 RINH3 0 D2 LINH3 0 D1 RINH2 0 D0 LINH2 0 LINH2: Switch Control from LIN2 pin to Headphone Output (without MIC-Amp) 0: OFF (default) 1: ON RINH2: Switch Control from RIN2 pin to Headphone Output (without MIC-Amp) 0: OFF (default) 1: ON LINH3: Switch Control from LIN3 pin (or MIC-Amp Lch) to Headphone Output 0: OFF (default) 1: ON RINH3: Switch Control from RIN3 pin (or MIC-Amp Lch) to Headphone Output 0: OFF (default) 1: ON LINH4: Switch Control from LIN4 pin to Headphone Output (without MIC-Amp) 0: OFF (default) 1: ON RINH4: Switch Control from RIN4 pin to Headphone Output (without MIC-Amp) 0: OFF (default) 1: ON HPM3: Mono Mixing from MIC-Amp (or LIN3/RIN3) to Headphone Output 0: Stereo Mixing (default) 1: Mono Mixing MS0670-E-00 2007/09 - 92 - [AK4673] SYSTEM DESIGN Figure 83 and Figure 84 shows the system connection diagram for the AK4673. The evaluation board [AKD4673] is demonstrates the optimum layout, power supply arrangements and measurement results. Power Supply 1.6 ~ 3.6V 0.22u 10u 10 0.22u 47u 10 6.8 Power Supply 2.6 ~ 3.6V 47u 10u 6.8 Headphone Power Supply 2.6 ~ 5.25V 0.1u μP 1u MUTET HPL HVDD SCLT CADT NC MCKI NC RIN4 NC HPR VSS2 SDAT PENIRQN NC MCKO NC ROUT LIN4 NC TVDD1 0.1u LOUT MIN TVDD2 DVDD 0.1u NC RIN2 NC VSS3 TSVDD LIN2 LRCK BICK LIN1 NC NC SDTI SDTO VCOM RIN1 MPWR I2CA VCOC NC PDN SCLA SDAA NC VSS1 AVDD XP YP XN YN CADA NC 10 NC Line In 1u Line Out External SPK-Amp 1u Mono In External MIC AK4673EG 0.1u DSP 2.2K 2.2K 2.2K 2.2K Internal MIC μP 2.2u 0.1u Touch Screen Cp Rp Power Supply 2.5 ~ 3.6V Analog Ground 10u Digital Ground Notes: - VSS1, VSS2 and VSS3 pins of the AK4673 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK4673 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of the VCOC/RIN3 pin is not needed. - When the AK4673 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of the VCOC/RIN3 pin should be connected as shown in Table 5. - When the AK4673 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4673. - 0.1μF ceramic capacitor should be attached to each supply pins. The type of other capacitors is not critical. - When DVDD is supplied from AVDD via 10Ω series resistor, the capacitor larger than 0.1μF should not be connected between DVDD and the ground. Figure 83. Typical Connection Diagram (AIN3 bit = “0”, MIC Input) MS0670-E-00 2007/09 - 93 - [AK4673] Power Supply 1.6 ∼ 3.6V 10u 0.22u 10 0.22u 47u 10 6.8 Power Supply 2.6 ∼ 3.6V 47u 10u 6.8 Headphone Power Supply 2.6 ∼ 5.25V 0.1u μP 20K 1u MUTET HPL HVDD SCLT CADT NC MCKI NC RIN4 NC HPR VSS2 SDAT PENIRQN NC MCKO NC ROUT LIN4 NC TVDD1 0.1u LOUT LIN3 TVDD2 DVDD 0.1u NC RIN2 NC VSS3 TSVDD LIN2 LRCK BICK LIN1 NC NC SDTI SDTO VCOM RIN1 MPWR I2CA RIN3 NC PDN SCLA SDAA NC VSS1 AVDD XP YP XN YN CADA NC 10 20K NC Line In 1u Line Out 200 200 1u AK4673EG 0.1u DSP Line In μP 2.2u 0.1u Touch Screen Power Supply 2.5 ∼ 3.6V Analog Ground 10u Digital Ground Notes: - VSS1, VSS2 and VSS3 pins of the AK4673 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When AIN3 bit = “1”, PLL is not available. - When the AK4673 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4673. - 0.1μF ceramic capacitor should be attached to each supply pins. The type of other capacitors is not critical. - When DVDD is supplied from AVDD via 10Ω series resistor, a capacitor larger than 0.1μF should not be connected between DVDD and the ground. Figure 84. Typical Connection Diagram (AIN3 bit = “1”: PLL is not available, Line Input) MS0670-E-00 2007/09 - 94 - [AK4673] 1. Grounding and Power Supply Decoupling The AK4673 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, TVDD1, TVDD2, HVDD and TSVDD are usually supplied from the system’s analog supply. If AVDD, DVDD, TVDD1, TVDD2, HVDD and TSVDD are supplied separately, the power-up sequence is not critical. The PDN pin should be held to “L” upon power-up. The PDN pin should be set to “H” after all power supplies are powered-up. In case that the pop noise should be avoided at line output and headphone output, the AK4673 should be operated by the following recommended power-up/down sequence. 1) Power-up - The PDN pin should be held to “L” upon power-up. The AK4673 should be reset by bringing the PDN pin “L” for 150ns or more. - In case that the power supplies are separated in two or more groups, the power supply including TVDD1 and TVDD2 should be powered ON at first. Regarding the relationship between DVDD and HVDD, the power supply including DVDD should be powered ON prior to the power supply including HVDD. 2) Power-down - Each power supplies should be powered OFF after the PDN pin is set to “L”. - In case that the power supplies are separated in two or more groups, the power supply including TVDD1 and TVDD2 should be powered OFF at last. Regarding the relationship between DVDD and HVDD, the power supply including HVDD should be powered OFF prior to the power supply including DVDD. VSS1, VSS2 and VSS3 of the AK4673 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4673 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4673. 3. Analog Inputs The Mic, Line and MIN inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp(typ) @MGAIN1-0 bits = “01”, 0.03 x AVDD Vpp(typ) @MGAIN1-0 bits = “10”, 0.015 x AVDD Vpp(typ) @MGAIN1-0 bits = “11” or 0.6 x AVDD Vpp(typ) @MGAIN1-0 bits = “00” for the Mic/Line input and 0.6 x AVDD Vpp (typ) for the MIN input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = 1/ (2πRC). The AK4673 can accept input voltages from VSS1 to AVDD. 4. Analog Outputs The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). The ideal output is VCOM voltage for 0000H(@16bit). Stereo Line Output is centered at 0.45 x AVDD. The Headphone-Amp output is centered at HVDD/2. MS0670-E-00 2007/09 - 95 - [AK4673] CONTROL SEQUENCE ■ Clock Set up When ADC or DAC is powered-up, the clocks must be supplied. 1. PLL Master Mode. Example: Power Supply Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 8kHz (1) PDN pin (2) (3) PMVCM bit (Addr:00H, D6) (4) (1) Power Supply & PDN pin = “L” Æ “H” MCKO bit (Addr:01H, D1) PMPLL bit (2)Addr:01H, Data:08H Addr:04H, Data:4AH Addr:05H, Data:00H (Addr:01H, D0) (5) MCKI pin Input M/S bit (3)Addr:00H, Data:40H (Addr:01H, D3) 40msec(max) (6) BICK pin LRCK pin Output (4)Addr:01H, Data:0BH Output MCKO, BICK and LRCK output 40msec(max) (8) MCKO pin (7) Figure 85. Clock Set Up Sequence (1) <Example> (1) After Power Up, the PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4673. The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid the pop noise at line output and headphone output. (2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period. (3) Power UpVCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered-up before the other block operates. (4) In case of using MCKO output: MCKO bit = “1” In case of not using MCKO output: MCKO bit = “0” (5) PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source. (6) The AK4673 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation starts. (7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”. (8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”. MS0670-E-00 2007/09 - 96 - [AK4673] 2. PLL Slave Mode (LRCK or BICK pin) Example: Power Supply Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz (1) PDN pin (2) 4fs (1)ofPower Supply & PDN pin = “L” Æ “H” (3) PMVCM bit (Addr:00H, D6) PMPLL bit (2) Addr:04H, Data:32H Addr:05H, Data:00H (Addr:01H, D0) LRCK pin BICK pin Input (3) Addr:00H, Data:40H (4) Internal Clock (5) (4) Addr:01H, Data:01H Figure 86. Clock Set Up Sequence (2) <Example> (1) After Power Up: The PDN pin “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4673. The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output. (2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is supplied. PLL lock time is 160ms(max) when LRCK is a PLL reference clock. And PLL lock time is 2ms(max) when BICK is a PLL reference clock. (5) Normal operation stats after that the PLL is locked. MS0670-E-00 2007/09 - 97 - [AK4673] 3. PLL Slave Mode (MCKI pin) Example: Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 8kHz Power Supply (1) Power Supply & PDN pin = “L” Æ “H” (1) PDN pin (2) (3) (2)Addr:04H, Data:4AH Addr:05H, Data:00H PMVCM bit (Addr:00H, D6) (4) MCKO bit (Addr:01H, D1) (3)Addr:00H, Data:40H PMPLL bit (Addr:01H, D0) (5) MCKI pin (4)Addr:01H, Data:03H Input 40msec(max) (6) MCKO pin MCKO output start Output (7) (8) BICK pin LRCK pin Input BICK and LRCK input start Figure 87. Clock Set Up Sequence (3) <Example> (1) After Power Up: The PDN pin “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4673. The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output. (2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) Enable MCKO output: MCKO bit = “1” (5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied. PLL lock time is 40ms(max). (6) The invalid frequency is output from MCKO during this period. (7) The normal clock is output from MCKO after PLL is locked. (8) BICK and LRCK clocks should be synchronized with MCKO clock. MS0670-E-00 2007/09 - 98 - [AK4673] 4. EXT Slave Mode Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable Power Supply (1) Power Supply & PDN pin = “L” Æ “H” (1) PDN pin (2) (2) Addr:04H, Data:02H Addr:05H, Data:00H (3) PMVCM bit (Addr:00H, D6) (4) MCKI pin Input (3) Addr:00H, Data:40H (4) LRCK pin BICK pin Input MCKI, BICK and LRCK input Figure 88. Clock Set Up Sequence (4) <Example> (1) After Power Up: The PDN pin “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4673. The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output. (2) DIF1-0 and FS1-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) Normal operation starts after the MCKI, LRCK and BICK are supplied. MS0670-E-00 2007/09 - 99 - [AK4673] 5. EXT Master Mode Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable (1) Power Supply & PDN pin = “L” Æ “H” Power Supply (1) PDN pin (2) MCKI input (4) PMVCM bit (Addr:00H, D6) (3) Addr:04H, Data:02H Addr:05H, Data:00H Addr:01H, Data:08H (2) MCKI pin Input (3) M/S bit BICK and LRCK output (Addr:01H, D3) LRCK pin BICK pin Output (4) Addr:00H, Data:40H Figure 89. Clock Set Up Sequence (5) <Example> (1) After Power Up: The PDN pin “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4673. The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output. (2) MCKI should be input. (3) After DIF1-0 and FS1-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output. (4) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. MS0670-E-00 2007/09 - 100 - [AK4673] ■ MIC Input Recording (Stereo) Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 PLL Master Mode Audio I/F Format:MSB justified (ADC & DAC) Sampling Frequency:44.1kHz Pre MIC AMP:+20dB MIC Power On ALC setting:Refer to Table 34 ALC bit=“1” 1,111 (1) MIC Control (Addr:02H, D2-0) ALC Control 1 (Addr:06H) ALC Control 2 (Addr:08H) (1) Addr:05H, Data:27H 001 101 (2) Addr:02H, Data:05H (2) 00H 3CH (3) Addr:06H, Data:3CH E1H (4) Addr:08H, Data:E1H (3) E1H (4) (5) Addr:0BH, Data:00H ALC Control 3 (Addr:0BH) 00H 00H (6) Addr:07H, Data:21H (5) ALC Control 4 (Addr:07H) 07H 21H 01H (6) ALC State (9) ALC Disable ALC Enable ALC Disable (7) Addr:00H, Data:41H Addr:10H, Data:01H Recording PMADL/R bits (Addr:00H&10H, D0) 1059 / fs (8) (7) ADC Internal State Power Down (8) Addr:00H, Data:40H Addr:10H, Data:00H Initialize Normal State Power Down (9) Addr:07H, Data:01H Figure 90. MIC Input Recording Sequence <Example> This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to “Figure 35. Registers set-up sequence at ALC operation” At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bit). When the AK4673 is PLL mode, MIC and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up MIC input (Addr: 02H) (3) Set up Timer Select for ALC (Addr: 06H) (4) Set up REF value for ALC (Addr: 08H) (5) Set up LMTH1 and RGAIN1 bits (Addr: 0BH) (6) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H) (7) Power Up MIC and ADC: PMADL = PMADR bits = “0” → “1” The initialization cycle time of ADC is 1059/fs=24ms@fs=44.1kHz. After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL default value (+30dB). The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog input pin going to the common voltage and the time constant of the offset cancel digital HPF. This time can be shorter by using the following sequence: At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to power-up the ADC should be longer than 4 times of the time constant that is determined by the AC coupling capacitor at analog input pin and the internal input resistance 60k(typ). (8) Power Down MIC and ADC: PMADL = PMADR bits = “1” → “0” When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed when the sampling frequency is changed, it should be done after the AK4673 goes to the manual mode (ALC bit = “0”) or MIC&ADC block is powered-down (PMADL=PMADR bits = “0”). IVOL gain is not reset when PMADL=PMADR bits = “0”, and then IVOL operation starts from the setting value when PMADL or PMADR bit is changed to “1”. (9) ALC Disable: ALC bit = “1” → “0” MS0670-E-00 2007/09 - 101 - [AK4673] ■ Headphone-amp Output E x a m p le : FS3-0 bits (Addr:05H, D5&D2-0) 0,000 P L L M a s te r M o d e S a m p lin g F r e q u e n c y : 4 4 . 1 k H z D V O L C b it = “ 1 ” ( d e fa u lt ) D ig it a l V o lu m e L e v e l: − 8 d B B a s s B o o s t L e v e l: M id d le D e -e m p h a s e s re s p o n s e : O F F S o f t M u t e T im e : 2 5 6 /f s 1,111 (1) ( 1 ) A d d r : 0 5 H , D a ta : 2 7 H DACH bit (2) (Addr:0FH, D0) (13) ( 2 ) A d d r : 0 F H , D a ta 0 9 H BST1-0 bits (Addr:0EH, D3-2) IVL/R7-0 bits (Addr:09H&0CH, D7-0) 00 10 00 (3) E1H (4 ) A d d r:0 9 H & 0 C H , D a ta 9 1 H 91H (4) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (3 ) A d d r:0 E H , D a ta 1 9 H (12) ( 5 ) A d d r : 0 A H & 0 D H , D a ta 2 8 H 18H 28H ( 6 ) A d d r : 0 0 H , D a ta 6 4 H (5) PMDAC bit ( 7 ) A d d r : 0 1 H , D a ta 3 9 H (Addr:00H, D2) (6) (11) PMMIN bit ( 8 ) A d d r : 0 1 H , D a ta 7 9 H P la y b a c k (Addr:00H, D5) ( 9 ) A d d r : 0 1 H , D a ta 3 9 H PMHPL/R bits (7) (10) (Addr:01H, D5-4) HPMTN bit ( 1 0 ) A d d r :0 1 H , D a t a 0 9 H (8) (9) (Addr:01H, D6) ( 1 1 ) A d d r :0 0 H , D a t a 4 0 H ( 1 2 ) A d d r :0 E H , D a t a 0 0 H HPL/R pins Normal Output ( 1 3 ) A d d r :0 F H , D a t a 0 8 H Figure 91. Headphone-Amp Output Sequence <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4673 is PLL mode, DAC and Headphone-Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1” (3) Set up the low frequency boost level (BST1-0 bits) (4) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB). (5) Set up the output digital volume (Addr: 0AH and 0DH) When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (6) Power up DAC and MIN-Amp: PMDAC = PMMIN bits = “0” → “1” The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by IVL/R7-0 bits) during an initialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits. (7) Power up headphone-amp: PMHPL = PMHPR bits = “0” → “1” Output voltage of headphone-amp is still VSS2. (8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1” The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V and the capacitor value is 1.0μF, the time constant is τr = 100ms(typ), 250ms(max). (9) Fall down the common voltage of headphone-amp: HPMTN bit = “1” → “0” The fall time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V and the capacitor value is 1.0μF, the time constant is τ f = 100ms(typ), 250ms(max). If the power supply is powered-off or headphone-Amp is powered-down before the common voltage goes to GND, the pop noise occurs. It takes twice of τf that the common voltage goes to GND. (10) Power down headphone-amp: PMHPL = PMHPR bits = “1” → “0” (11) Power down DAC and MIN-Amp: PMDAC = PMMIN bits = “1” → “0” (12) Off the bass boost: BST1-0 bits = “00” (13) Disable the path of “DAC → HP-Amp”: DACH bit = “1” → “0” MS0670-E-00 2007/09 - 102 - [AK4673] ■ Stereo Line Output Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 PLL, Master Mode Audio I/F Format :MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: −8dB LOVL=MINL bits = “0” 1,111 (1) (1) Addr:05H, Data:27H (10) DACL bit (2) (2) Addr:02H, Data:10H (Addr:02H, D4) IVL/R7-0 bits (Addr:09H&0CH, D7-0) E1H (3) Addr:09H&0CH, Data:91H 91H (3) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (4) Addr:0AH&0DH, Data:28H 18H 28H (5) Addr:03H, Data:40H (4) LOPS bit (6) Addr:00H, Data:6CH (Addr:03H, D6) (5) (7) (8) (11) PMDAC bit (Addr:00H, D2) Playback PMMIN bit (8) Addr:03H, Data:40H (Addr:00H, D5) (6) (9) (9) Addr:00H, Data:40H PMLO bit (Addr:00H, D3) (7) Addr:03H, Data:00H >300 ms (10) Addr:02H, Data:00H LOUT pin ROUT pin >300 ms Normal Output (11) Addr:03H, Data:00H Figure 92. Stereo Lineout Sequence <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up the sampling frequency (FS3-0 bits). When the AK4673 is PLL mode, DAC and Stereo Line-Amp should be powered-up in consideration of PLL lock time after the sampling frequency is changed. (2) Set up the path of “DAC Æ Stereo Line Amp”: DACL bit = “0” Æ “1” (3) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB). (4) Set up the output digital volume (Addr: 0AH and 0DH) When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (5) Enter power-save mode of Stereo Line Amp: LOPS bit = “0” Æ “1” (6) Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “0” → “1” The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by IVL/R7-0 bits) during an initialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits. LOUT and ROUT pins rise up to VCOM voltage after PMLO bit is changed to “1”. Rise time is 300ms(max) at C=1μF and AVDD=3.3V. (7) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0” LOPS bit should be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation by setting LOPS bit to “0”. (8) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0” Æ “1” (9) Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “1” → “0” LOUT and ROUT pins fall down to VSS1. Fall time is 300ms(max) at C=1μF and AVDD=3.3V. (10) Disable the path of “DAC Æ Stereo Line-Amp”: DACL bit = “1” Æ “0” (11) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0” LOPS bit should be set to “0” after LOUT and ROUT pins fall down. MS0670-E-00 2007/09 - 103 - [AK4673] ■ Stop of Clock Master clock can be stopped when ADC and DAC are not used. 1. PLL Master Mode Example: Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz Sampling Frequency: 8kHz (1) PMPLL bit (Addr:01H, D0) (2) MCKO bit "1" or "0" (1) (2) Addr:01H, Data:08H (Addr:01H, D1) (3) External MCKI Input (3) Stop an external MCKI Figure 93. Clock Stopping Sequence (1) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop MCKO clock: MCKO bit = “1” → “0” (3) Stop an external master clock. 2. PLL Slave Mode (LRCK or BICK pin) Example Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz (1) PMPLL bit (Addr:01H, D0) (2) External BICK Input (1) Addr:01H, Data:00H (2) External LRCK Input (2) Stop the external clocks Figure 94. Clock Stopping Sequence (2) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop the external BICK and LRCK clocks 3. PLL Slave (MCKI pin) Example (1) Audio I/F Format: MSB justified (ADC & DAC) PLL Reference clock: MCKI BICK frequency: 64fs Sampling Frequency: 8kHz PMPLL bit (Addr:01H, D0) (1) MCKO bit (1) Addr:01H, Data:00H (Addr:01H, D1) (2) External MCKI Input (2) Stop the external clocks Figure 95. Clock Stopping Sequence (3) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop MCKO output: MCKO bit = “1” → “0” (3) Stop the external master clock. MS0670-E-00 2007/09 - 104 - [AK4673] 4. EXT Slave Mode (1) External MCKI Input Example (1) External BICK Input External LRCK Input Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz (1) (1) Stop the external clocks Figure 96. Clock Stopping Sequence (4) <Example> (1) Stop the external MCKI, BICK and LRCK clocks. 5. EXT Master Mode (1) External MCKI Input Example BICK Output "H" or "L" LRCK Output "H" or "L" Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz (1) Stop the external MCKI Figure 97. Clock Stopping Sequence (5) <Example> (1) Stop MCKI clock. BICK and LRCK are fixed to “H” or “L”. ■ Power down Power supply current can be shut down (typ. 20μA) by stopping clocks and setting PMVCM bit = “0” after all blocks except for VCOM are powered-down. Power supply current can be also shut down (typ. 1μA) by stopping clocks and setting the PDN pin = “L”. When the PDN pin = “L”, the registers are initialized. MS0670-E-00 2007/09 - 105 - [AK4673] PACKAGE 57pin BGA (Unit: mm) 5.0 ± 0.1 φ 0.05 A 57 - φ 0.3 ± 0.05 M S AB 9 8 7 65 4 3 2 1 4.0 5.0 ± 0.1 A B C D E B F G H J 0.5 0.5 S 1.0MAX 0.25 ± 0.05 0.08 S ■ Material & Lead finish Package molding compound: Interposer material: Solder ball material: Epoxy BT resin SnAgCu MS0670-E-00 2007/09 - 106 - [AK4673] MARKING 4673 XXXX XXXX: Date code (4 digit) Pin #A1 indication REVISION HISTORY Date (YY/MM/DD) 07/09/28 Revision 00 Reason First Edition Page Contents IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0670-E-00 2007/09 - 107 -