AKM AKD4634

[AK4634]
= Preliminary =
AK4634
16-Bit Mono CODEC with ALC & MIC/SPK-AMP
GENERAL DESCRIPTION
The AK4634 is a 16-bit mono CODEC with Microphone-Amplifier and Speaker-Amplifier. Input circuits
include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a
Speaker-Amplifier and Mono Line Output. The AK4634 is suitable for a moving picture of Digital Still
Camera and etc. This speaker-Amplifier supports a Piezo Speaker. The AK4634 is housed in a
space-saving 32-pin QFN 5mm x 5mm package.
1.
2.
3.
4.
5.
6.
7.
8.
9.
FEATURE
16-Bit Delta-Sigma Mono CODEC
Recording Function
• 1ch Mono Input
• MIC Amplifier: (0dB/+3dB/+6dB/+10dB/ +17dB/+20dB/+23dB/+26dB/+29dB/+32dB)
• Digital ALC (Automatic Level Control)
(+36dB ∼ -54dB, 0.375dB Step, Mute)
• ADC Performance (MIC-Amp=+20dB)
- S/(N+D): 84dB
- DR, S/N: 86dB
• Wind-noise Reduction Emphasis
• 5 band notch Filter
Playback Function
• Digital ALC (Automatic Level Control)
(+36dB ∼ -54dB, 0.375dB Step, Mute)
• Mono Line Output: S/(N+D) : 85dB, S/N : 93dB
• Mono Class-D Speaker-Amp
- BTL Output
- Output Power: 400mW @ 8Ω (SVDD=3.3V)
- S/(N+D): 55dB (150mW@8Ω)
• Beep Generator
Power Management
PLL Mode:
• Frequencies:
12MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)
1fs (FCK pin)
16fs, 32fs or 64fs (BICK pin)
EXT Mode:
• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)
Sampling Rate:
• PLL Slave Mode (FCK pin): 7.35kHz ~ 48kHz
• PLL Slave Mode (BICK pin): 7.35kHz ~ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Slave Mode / EXT Master Mode:
7.35kHz ~ 48kHz (256fs), 7.35kHz ~ 26kHz (512fs), 7.35kHz ~ 13kHz (1024fs)
Output Master Clock Frequency: 256fs
Serial μP Interface: 3-wire, I2C Bus (Ver 1.0, 400kHz High Speed Mode)
Rev. 0.5
2007/10
-1-
[AK4634]
10. Master / Slave Mode
11. Audio Interface Format: MSB First, 2’s compliment
• ADC: DSP Mode, 16bit MSB justified, I2S
• DAC: DSP Mode, 16bit MSB justified, 16bit LSB justified, I2S
12. Ta = - 30 ∼ 85°C
13. Power Supply
• Analog Supply (AVDD): 2.2 ∼ 3.6V
• Digital Supply (DVDD): 1.6 ∼ 3.6V
• Speaker Supply (SVDD): 2.2 ∼ 4.0V
14. Package: 29pin CSP, 2.5mm x 3.0mm, 0.5mm pitch
■ Block Diagram
AVDD
VSS1
VCOM
DVDD
VSS2
PMMP
MPI
PDN
MIC Power
Supply
I2C
MIC/MICP
PMADC
Mic
A/D
LIN/MICN
HPF
MIC-Amp
0dB /+3dB/+6dB/+10dB/+17dB/+20dB
+23dB+26dB / +29dB / +32dB
PMPFIL
BICK
HPF
Audio
I/F
LPF
PMAO
Line Out
AOUT
SDTO
PMDAC
&
PMAO
5 Band
EQ
D/A
VOL
(ALC)
SVDD
SDTI
PMDAC
VSS3
SMUTE
DATT
MCKO
PMPLL
MCKI
PMSPK
PLL
SPP
Speaker
SPN
FCK
Class-D
VCOC
PMSPK
SPK-AMP
BEEP
Generator
CSN/SDA
Control
Register
CCLK/SCL
CDTIO
TET1
TET2
TET3
Figure 1. AK4634 Block Diagram
Rev. 0.5
2007/10
-2-
[AK4634]
■ Ordering Guide
−30 ∼ +85°C
29 pin CSP (0.5mm pitch)
Evaluation board for AK4634
AK4634
AKD4634
■ Pin Layout
6
5
4
Top View
3
2
1
A
B
C
D
E
6
I2C
DVDD
VSS2
VSS3
NC
5
SDTO
MCKO
SPN
SVDD
SPP
4
BICK
SDTI
MCKI
AOUT
3
FCK
CCLK/SCL
CDTIO
MPI
2
PDN
CSN/SDA
TST2
VCOM
VCOC
1
TST1
VSS1
AVDD
TST3
C
D
E
A
B
LIN/
MICN
MIC/
MICP
Top View
Rev. 0.5
2007/10
-3-
[AK4634]
■ Compatibility with AK4633
1. Function
Function
MIC-Amp
AK4633
0dB/+6dB/+10dB/+14dB
+17dB/+20dB/+26dB/+32dB
Single End of Analog Input
LPF
Notch Filter ( Equalizer)
SPK-Amp
ALC Recovery Waiting Period
1ch (MIC pin)
Not Available
2 band
Class-AB
4 steps
(128fs ~ 1024fs)
11.2896MHz, 12MHz,
12.288MHz, 13.5MHz
24MHz, 27MHz
Analog Input
3-wire
24pin QFN: 4.0mm x 4.0mm
Master Clock Mode
PLL Mode Frequency
BEEP Output
Control Interface
Package
Rev. 0.5
AK4634
0dB/+3dB/+6dB/+10dB/+17dB/
+20dB/+23dB/+26dB/+29dB/
+32dB
2ch (MIC pin / LIN pin)
Available
5 band
Class-D
8 steps
(128fs ~ 16384fs)
12MHz, 13.5MHz, 24MHz,
27MHz
Generator circuit Included
3-wire, I2C
29 pin CSP:2.5mm x 3.0mm
2007/10
-4-
[AK4634]
PIN/FUNCTION
No.
1
Pin Name
NC
I/O
-
Function
No Connection. No internal bonding. This pin should be connected to the ground.
TEST3 pin
This pin should be open.
2
TST3
-
3
4
AVDD
VSS1
-
5
TST2
-
6
TST1
-
7
NC
CSN
I
SDA
I/O
9
PDN
I
10
CDTIO
I/O
CCLK
I
Control Data Clock Pin (I2C pin = “L”)
SCL
FCK
MCKI
BICK
SDTI
SDTO
I2C
MCKO
DVDD
VSS2
NC
SPN
VSS3
NC
SPP
SVDD
AOUT
LIN
I
I/O
I
I/O
I
O
I
O
O
O
O
I
Control Data Clock Pin (I2C pin = “H”)
MICN
I
Microphone Negative Input Pin for Differential Input
MIC
I
Microphone Input Pin for Single Ended Input
MICP
I
Microphone Positive Input Pin for Differential Input
30
MPI
I
MIC Power Supply Pin for Microphone
31
VCOM
O
32
VCOC
O
8
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Analog Power Supply Pin 2.2 ~ 3.6V
Ground Pin.
TEST2 pin
This pin should be open.
TEST1 pin
This pin should be open.
No Connection. No internal bonding. This pin should be connected to the ground.
Chip Select Pin (I2C pin = “L”)
Control Data Input/Output Pin (I2C pin = “H”)
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initialize the control register.
AK4634 should always be reset upon power-up.
Control Data Input/Output Pin (I2C pin = “L”)
This pin should be connected to the ground. (I2C pin = “H”)
Frame Clock Pin
External Master Clock Input Pin
Audio Serial Data Clock Pin
Audio Serial Data Input Pin
Audio Serial Data Output Pin
Control Mode Select Pin “H”: I2C Bus, “L”: 3-wire Serial
Master Clock Output Pin
Digital Power Supply Pin 1.6 ~ 3.6V
Ground Pin.
No Connection. No internal bonding. This pin should be connected to the ground.
Speaker Amp Negative Output Pin
Ground Pin.
No Connection. No internal bonding. This pin should be connected to the ground.
Speaker Amp Negative Output Pin
Speaker Amp Power Supply Pin 2.2 ~4.0V
Mono Line Output Pin
Line Input Pin for Single Ended Input
(MDIF bit = “0”)
(MDIF bit = “1”)
(MDIF bit = “0”)
(MDIF bit = “1”)
Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of ADC inputs and DAC outputs.
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to VSS1 with one resistor and capacitor in series.
Note : All input pins except analog input pins (MIC/MICP, LIN/MICN pins) must not be left floating
Rev. 0.5
2007/10
-5-
[AK4634]
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
MIC/MICP, LIN/MICN, MPI, AOUT,
SPP, SPN, VCOC
MCKI, SDTI
Setting
These pins should be open
These pins should be connected to VSS2
When I2C pin = “H”, These pins should be
connected to VSS2.
These pins should be open.
CDTIO
MCKO, SDTO
ABSOLUTE MAXIMUM RATINGS
(VSS1-3 =0V; Note 1)
Parameter
Symbol
min
−0.3
AVDD
Analog
Power Supplies:
−0.3
DVDD
Digital
−0.3
SVDD
Speaker-Amp
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage (Note 2)
VINA
−0.3
Digital Input Voltage (Note 3)
VIND
−0.3
Ambient Temperature (powered applied)
Ta
−40
Storage Temperature
Tstg
−65
Maximum Power Dissipation (Note 4)
Pd
-
max
4.6
4.6
4.6
±10
AVDD+0.3
DVDD+0.3
85
150
400
Units
V
V
V
mA
V
V
°C
°C
mW
Note 1. All voltages with respect to ground. VSS21, VSS2 and VSS3 must be connected to the same analog ground plane.
Note 2. LIN/MICN, MIC/MICP pins
Note 3. PDN, I2C, CSN/SDA, CCLK/SCL, CDTIO, SDTI, FCK, BICK, MCKI pins
Pull-up resistors at SDA and SCL pins should be connected to (DVDD+0.3)V or less voltage.
Note 4.When PCB wiring density is 100%. This power is the AK4634 internal dissipation that does not include power of
externally connected speaker.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1-3=0V; Note 1)
Parameter
Symbol
Min
typ
3.3
2.2
AVDD
Power Supplies Analog
3.3
1.6
DVDD
Digital
(Note 5)
3.3
2.2
SVDD
Speaker-Amp
max
3.6
3.6
4.0
Units
V
V
V
Note 1. All voltages with respect to ground.
Note 5. The power up sequence between AVDD, DVDD and SVDD is not critical.
Do not power DVDD off when AVDD or SVDD is powered up.
When only AVDD or SVDD is powered OFF, the AK4634 must be reset by bringing the PDN pin “L” after
theses power supplies are powered ON again. The power supply current of DVDD at power-down mode may be
increased. DVDD should not be powered OFF while AVDD or SVDD is powered ON.
* AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
Rev. 0.5
2007/10
-6-
[AK4634]
ANALOG CHRACTERISTICS
(Ta=25°C; AVDD = DVDD = SVDD=3.3V; VSS1-3 =0V; fs=8kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data;
Measurement frequency=20Hz ∼ 3.4kHz; EXT Slave Mode; unless otherwise specified)
Parameter
min
typ
max
Units
MIC Amplifier: MIC, LIN pins ; MDIF bit = “0”; (Single-ended input)
Input Resistance
20
30
40
kΩ
Gain
0
dB
(MGAIN3-0 bits = “0000”)
20
dB
(MGAIN3-0 bits = “0001”)
26
dB
(MGAIN3-0 bits = “0010”)
32
dB
(MGAIN3-0 bits = “0011”)
10
dB
(MGAIN3-0 bits = “0100”)
17
dB
(MGAIN3-0 bits = “0101”)
23
dB
(MGAIN3-0 bits = “0110”)
29
dB
(MGAIN3-0 bits = “0111”)
3
dB
(MGAIN3-0 bits = “1000”)
6
dB
(MGAIN3-0 bits = “1001”)
MIC Amplifier: MICP, MICN pins ; MDIF bit = “1”; (Full-differential input)
Input Voltage
0.228
Vpp
(MGAIN3-0 bits = “0001”)
(Note 6)
0.114
Vpp
(MGAIN3-0 bits = “0010”)
0.057
Vpp
(MGAIN3-0 bits = “0011”)
0.720
Vpp
(MGAIN3-0 bits = “0100”)
0.322
Vpp
(MGAIN3-0 bits = “0101”)
0.161
Vpp
(MGAIN3-0 bits = “0110”)
0.080
Vpp
(MGAIN3-0 bits = “0111”)
1.14
Vpp
(MGAIN3-0 bits = “1001”)
MIC Power Supply: MPI pin
Output Voltage
(Note 7)
TBD
2.64
TBD
V
Load Resistance
2
kΩ
Load Capacitance
30
pF
ADC Analog Input Characteristics: MIC/LIN Æ ADC, MIC Gain=20dB, IVOL=0dB, ALC1bit = “0”
Resolution
16
Bits
Input Voltage (MIC Gain=20dB, Note 8)
TBD
0.198
TBD
Vpp
TBD
84
dB
S/(N+D)
(−1dBFS) (Note 9)
TBD
86
dB
D-Range
(−60dBFS)
S/N
TBD
86
dB
DAC Characteristics:
Resolution
16
Bits
Mono Line Output Characteristics: AOUT pin, DAC → AOUT, RL=10kΩ
TBD
1.98
TBD
Vpp
Output Voltage (Note 10) LOVL bit = “0”
TBD
2.50
TBD
Vpp
LOVL bit = “1”
85
TBD
dB
S/(N+D)
(0dBFS) (Note 9)
93
TBD
dB
D-Range
(-60dBFS)
93
TBD
dB
S/N
10
Load Resistance
kΩ
30
pF
Load Capacitance
Speaker-Amp Characteristics: SDTI Æ SPP/SPN pins, ALC2 bit = “0”, SPKG bit = “0”, RL=8Ω + 10μH,
BTL = SVDD=3.3V
Output Power (0dBFS)
(Note 11)
400
mW
S/(N+D)
400mW output
20
dB
150mW output
55
dB
TBD
-80
dBV
Output Noise Level
Load Resistance
8
Ω
30
pF
Load Capacitance
Rev. 0.5
2007/10
-7-
[AK4634]
Parameter
Min
Typ
max
Units
Speaker-Amp Characteristics: SDTI → SPP/SPN pins, ALC2 bit = “0”, SPKG bit = “0”, CL=3μF, Rseries=10Ω x 2,
BTL, SVDD=3.8V
Output Voltage (0dBFS)
(Note 11)
2.5
Vrms
S/(N+D) (Note 12)
20
dB
-68
dBV
Output Noise Level (Note 12)
Load Impedance (Note 13)
50
Ω
3
Load Capacitance
μF
Power Supplies
Power Up (PDN pin = “H”)
All Circuit Power-up: (Note 17)
AVDD+DVDD
fs=8kHz
9
mA
fs=48kHz
12
TBD
mA
SVDD: Speaker-Amp Normal Operation (No Output)
SVDD=3.3V
1.5
TBD
mA
Power Down (PDN pin = “L”) (Note 18)
1
TBD
AVDD+DVDD+SVDD
μA
Note 6. The voltage difference between MICP and MICN pins. AC coupling capacitor should be connected in series at
each input pin. Full-differential mic input is not available at MGAIN3-0 bits = “1000” or “0000”. Maximum input
voltage of MICP and MICN pins are proportional to AVDD voltage, respectively.
Vin = |(MICP) − (MICN)| = 0.069 x AVDD(max)@MGAIN3-0 bits = “0001”,
0.035 x AVDD(max)@MGAIN3-0 bits = “0010”, 0.017 x AVDD(max)@MGAIN3-0 bits = “0011”,
0.218x AVDD(max)@MGAIN3-0 bits = “0100”, 0.097x AVDD(max)@MGAIN3-0 bits = “0101”,
0.048x AVDD(max)@MGAIN3-0 bits = “0110”, 0.024x AVDD(max)@MGAIN3-0 bits = “0111”,
0.345x AVDD(max)@MGAIN3-0 bits = “1001”
When the signal larger than above value is input to MICP or MICN pin, ADC does not operate normally.
Note 7. Output voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ)
Note 8. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)
Note 9. When a PLL reference clock is the FCK pin in PLL Slave Mode, S/ (N+D) of MICÆADC is 75dB (typ), S/
(N+D) of DACÆAOUT is 75dB (typ).
Note 10. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)@LOVL bit = “0”.
Note 11. The value after passing LPF (LPF : Passband is 20kHz or less, Stopband Attenuation@250kHz is –50dB or less)
Note 12. In case of measuring at between the SPP pin and SPN pin directly.
Note 13. Load impedance is total impedance of series resistance (Rseries) and piezo speaker impedance at 1kHz in
Figure 44. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series
resistors should be connected at both SPP and SPN pins, respectively.
Note 14. Maximum input voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD
x Rin/20kΩ (typ).
Note 15. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).
Note 16. Input Voltage does not depend on AVDD voltage.
Note 17. PLL Master Mode (MCKI = 12MHz) and PMMP = PMADC = PMDAC = PMPFIL = PMSPK = PMVCM =
PMPLL = MCKO = PMAO = M/S = “1”. And output current from the MPI pin is 0mA.
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD+DVDD = (typ) TBDmA@fs=8kHz,
(typ)TBDmA @fs=48kHz
Note 18. All digital inputs pins are fixed to DVDD or VSS2.
Rev. 0.5
2007/10
-8-
[AK4634]
FILTER CHRACTERISTICS
(Ta = −30 ∼ 85°C; AVDD = 2.2 ∼ 3.6V; DVDD = 1.6 ∼ 3.6V, SVDD = 2.2 ∼ 4.0V; fs=8kHz)
Parameter
Symbol
min
typ
max
ADC Digital Filter (Decimation LPF):
Passband
(Note 19) ±0.16dB
PB
0
3.0
−0.66dB
3.5
−1.1dB
3.6
−6.9dB
4.0
Stopband
(Note 19)
SB
4.7
Passband Ripple
PR
±0.1
Stopband Attenuation
SA
73
Group Delay
(Note 20)
GD
16
Group Delay Distortion
ΔGD
0
DAC Digital Filter (Decimation LPF):
Passband
(Note 19)
±0.16dB
PB
0
3.0
−0.54dB
3.5
−1.0dB
3.6
−6.7dB
4.0
Stopband
(Note 19)
SB
4.7
Passband Ripple
PR
±0.1
Stopband Attenuation
SA
73
Group Delay
(Note 20)
GD
16
Group Delay Distortion
ΔGD
0
DAC Digital Filter + Analog Filter:
Frequency Response: 0 ∼ 3.4kHz
FR
±1.0
-
Units
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
dB
kHz
dB
dB
1/fs
μs
dB
Note 19. The passband and stopband frequencies are proportional to fs (system sampling rate).
For example, ADC of PB = 3.6kHz is 0.45*fs (@ −1.0dB). A reference of frequency response is 1kHz.
Note 20. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16-bit data of a channel from the input register to the output register of the ADC. For the DAC, this time is from
setting the 16-bit data of a channel from the input register to the output of analog signal. When there is not a
phase change with the IIR filter, the group delay of the programmable filter (primary HPF + primary LPF +
5-band Equalizer + ALC) increases for 2/fs than a value of an above mention.
DC CHRACTERISTICS
(Ta = −30 ~ 85°C; AVDD = 2.2 ∼ 3.6V, DVDD = 1.6 ∼ 3.6V, SVDD = 2.2 ∼ 4.0V)
Parameter
Symbol
min
70%DVDD
VIH
High-Level Input Voltage
(DVDD ≥ 2.2V)
80%DVDD
(DVDD < 2.2V)
VIL
Low-Level Input Voltage
(DVDD ≥ 2.2V)
(DVDD < 2.2V)
DVDD−0.2
VOH
High-Level Output Voltage
(Iout = −80μA)
Low-Level Output Voltage
(Except SDA pin: Iout = 80μA) VOL1
(SDA pin, 2.0V ≤ DVDD ≤ 3.6V: Iout = 3mA) VOL2
(SDA pin, 1.6V ≤ DVDD < 2.0V: Iout = 3mA) VOL2
Input Leakage Current
Iin
-
Rev. 0.5
typ
-
max
30%DVDD
20%DVDD
-
-
0.2
0.4
20%DVDD
±10
Units
V
V
V
V
V
V
V
μA
2007/10
-9-
[AK4634]
SWITING CHARACTERISTICS
(Ta = −30 ~ 85°C; AVDD = 2.2 ∼ 3.6V, DVDD = 1.6 ∼ 3.6V, SVDD = 2.2 ∼ 4.0V; CL = 20pF)
Parameter
Symbol
min
typ
max
PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 2)
MCKI Input: Frequency
fCLK
11.2896
27.0
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output:
256 x fFCK
fMCK
Frequency
60
50
40
dMCK
Duty Cycle except fs=29.4kHz, 32kHz
33
dMCK
fs =29.4kHz, 32kHz (Note 21)
48
8
fFCK
FCK Output: Frequency
Pulse width High
tBCK
tFCKH
(DIF1-0 bits = “00” and FCKO bit = “1”)
Duty Cycle
50
dFCK
(DIF1-0 bits = “00” or FCKO bit = “0”)
1/16fFCK
tBCK
BICK: Period (BCKO1-0 = “00”)
1/32fFCK
tBCK
(BCKO1-0 = “01”)
1/64fFCK
tBCK
(BCKO1-0 = “10”)
50
dBCK
Duty Cycle
Audio Interface Timing
DSP Mode: (Figure 3, Figure 4)
0.5 x tBCK + 40
0.5 x tBCK −40 0.5 x tBCK
tDBF
FCK “↑” to BICK “↑” (Note 22)
0.5 x tBCK +40
0.5 x tBCK −40 0.5 x tBCK
tDBF
FCK “↑” to BICK “↓” (Note 23)
70
-70
tBSD
BICK “↑” to SDTO (BCKP = “0”)
70
-70
tBSD
BICK “↓” to SDTO (BCKP = “1”)
50
tSDH
SDTI Hold Time
50
tSDS
SDTI Setup Time
Except DSP Mode: (Figure 5)
40
−40
tBFCK
BICK “↓” to FCK Edge
70
−70
tFSD
FCK to SDTO (MSB)
(Except I2S mode)
70
−70
tBSD
BICK “↓” to SDTO
50
tSDH
SDTI Hold Time
50
tSDS
SDTI Setup Time
Rev. 0.5
Units
MHz
ns
ns
kHz
%
%
kHz
ns
%
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2007/10
- 10 -
[AK4634]
Parameter
Symbol
min
PLL Slave Mode (PLL Reference Clock: FCK pin) (Figure 6, Figure 7)
FCK: Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK: Period
Pulse Width Low
Pulse Width High
fFCK
tFCKH
duty
tBCK
tBCKL
tBCKH
7.35
tBCK−60
45
1/64fFCK
0.4 x tBCK
0.4 x tBCK
typ
max
Units
8
-
48
1/fFCK−tBCK
55
1/16fFCK
-
kHz
ns
%
ns
ns
ns
8
1/16fFCK
1/32fFCK
1/64fFCK
-
48
1/fFCK−tBCK
55
-
kHz
ns
%
ns
ns
ns
ns
ns
PLL Slave Mode (PLL Reference Clock: BICK pin) (Figure 6, Figure 7)
FCK: Frequency
DSP Mode: Pulse width High
Except DSP Mode: Duty Cycle
BICK: Period (PLL3-0 bit = “0001”)
(PLL3-0 bit = “0010”)
(PLL3-0 bit = “0011”)
Pulse Width Low
Pulse Width High
fFCK
tFCKH
duty
tBCK
tBCK
tBCK
tBCKL
tBCKH
7.35
tBCK−60
45
0.4 x tBCK
0.4 x tBCK
PLL Slave Mode (PLL Reference Clock: MCKI pin) (Figure 8)
MCKI Input: Frequency
Pulse Width Low
Pulse Width High
MCKO Output:
Frequency
Duty Cycle except fs=29.4kHz, 32kHz
fs=29.4kHz, 32kHz (Note 21)
FCK: Frequency
DSP Mode: Pulse width High
Except DSP Mode: Duty Cycle
BICK: Period
Pulse Width Low
Pulse Width High
Audio Interface Timing
DSP Mode: (Figure 9, Figure 10)
FCK “↑” to BICK “↑” (Note 22)
FCK “↑” to BICK “↓” (Note 23)
BICK “↑” to FCK “↑” (Note 22)
BICK “↓” to FCK “↑” (Note 23)
BICK “↑” to SDTO (BCKP bit= “0”)
BICK “↓” to SDTO (BCKP bit= “1”)
SDTI Hold Time
SDTI Setup Time
Except DSP Mode: (Figure 12)
FCK Edge to BICK “↑” (Note 24)
BICK “↑” to FCK Edge (Note 24)
FCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
fCLK
fCLKL
fCLKH
11.2896
0.4/fCLK
0.4/fCLK
-
27.0
-
MHz
ns
ns
fMCK
dMCK
dMCK
fFCK
tFCKH
duty
tBCK
tBCKL
tBCKH
40
8
tBCK−60
45
1/64fFCK
0.4 x tBCK
0.4 x tBCK
256 x fFCK
50
33
-
60
48
1/fFCK−tBCK
55
1/16fFCK
-
kHz
%
%
kHz
ns
%
ns
ns
ns
tFCKB
tFCKB
tBFCK
tBFCK
tBSD
tBSD
tSDH
tSDS
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
50
50
-
80
80
-
ns
ns
ns
ns
ns
ns
ns
ns
tFCKB
tBFCK
tFSD
tBSD
tSDH
tSDS
50
50
50
50
-
80
80
-
ns
ns
ns
ns
ns
ns
Rev. 0.5
2007/10
- 11 -
[AK4634]
Parameter
EXT Slave Mode (Figure 11)
Symbol
min
typ
max
Units
MCKI Frequency: 256fs
512fs
1024fs
Pulse Width Low
Pulse Width High
FCK Frequency (MCKI = 256fs)
(MCKI = 512fs)
(MCKI = 1024fs)
Duty Cycle
BICK Period
BICK Pulse Width Low
Pulse Width High
fCLK
fCLK
fCLK
tCLKL
tCLKH
fFCK
fFCK
fFCK
duty
tBCK
tBCKL
tBCKH
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
7.35
7.35
7.35
45
312.5
130
130
2.048
4.096
8.192
8
8
8
-
12.288
13.312
13.312
48
26
13
55
-
MHz
MHz
MHz
ns
ns
Audio Interface Timing (Figure 12)
FCK Edge to BICK “↑” (Note 24)
BICK “↑” to FCK Edge (Note 24)
FCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tFCKB
tBFCK
tFSD
tBSD
tSDH
tSDS
50
50
50
50
-
80
80
-
ns
ns
ns
ns
ns
ns
Rev. 0.5
kHz
kHz
%
ns
ns
ns
2007/10
- 12 -
[AK4634]
Parameter
EXT Master Mode (Figure 2)
Symbol
min
typ
max
Units
MCKI Frequency: 256fs
512fs
1024fs
Pulse Width Low
Pulse Width High
FCK Frequency (MCKI = 256fs)
(MCKI = 512fs)
(MCKI = 1024fs)
Duty Cycle
BICK: Period (BCKO1-0 bit = “00”)
(BCKO1-0 bit = “01”)
(BCKO1-0 bit = “10”)
Duty Cycle
fCLK
fCLK
fCLK
tCLKL
tCLKH
fFCK
fFCK
fFCK
dFCK
tBCK
tBCK
tBCK
dBCK
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
7.35
7.35
7.35
-
2.048
4.096
8.192
8
8
8
50
1/16fFCK
1/32fFCK
1/64fFCK
50
12.288
13.312
13.312
48
26
13
-
MHz
MHz
MHz
ns
ns
kHz
kHz
kHz
%
ns
ns
ns
%
tDBF
tDBF
tBSD
tBSD
tSDH
tSDS
0.5 x tBCK−40
0.5 x tBCK−40
−70
−70
50
50
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK +40
70
70
-
ns
ns
ns
ns
ns
ns
tBFCK
tFSD
−40
−70
-
40
70
ns
ns
tBSD
tSDH
tSDS
−70
50
50
-
70
-
ns
ns
ns
Audio Interface Timing
DSP Mode: (Figure 3, Figure 4)
FCK “↑” to BICK “↑” (Note 22)
FCK “↑” to BICK “↓” (Note 23)
BICK “↑” to SDTO (BCKP bit = “0”)
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
SDTI Setup Time
Except DSP Mode: (Figure 5)
BICK “↓” to FCK Edge
FCK to SDTO (MSB)
(Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Note 21. Duty Cycle = (the width of “L”)/(the period of clock)*100
Note 22. MSBS, BCKP bits = “00” or “11”
Note 23. MSBS, BCKP bits = “01” or “10”
Note 24. BICK rising edge must not occur at the same time as FCK edge.
Rev. 0.5
2007/10
- 13 -
[AK4634]
Parameter
Control Interface Timing (3-wire Serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CCLK “↓” to CDTI (at Read Command)
CSN “↑” to CDTI (Hi-Z) (at Read Command)
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 26)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Reset Timing
PDN Pulse Width
(Note 25, Note 26, Note 27)
PMADC “↑” to SDTO valid
(Note 28)
ADRST bit = “0”
ADRST bit = “1”
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
40
40
150
50
50
-
-
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
150
-
-
ns
tPDV
tPDV
-
1059
291
-
1/fs
1/fs
Note 25. I2C is a registered trademark of Philips Semiconductors.
Note 26. RL = 1kΩ/10% change ( Pull-up to DVDD)
Note 27. The AK4634 can be reset by the PDN pin = “L”
Note 28. This is the count of FCK “↑” from the PMADC = “1”.
Rev. 0.5
2007/10
- 14 -
[AK4634]
■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fFCK
50%DVDD
FCK
dFCK
dFCK
1/fMCK
50%DVDD
MCKO
tMCKOH
tMCKOL
dMCK = tMCKOL x fMCK x 100%
Figure 2. Clock Timing (PLL/EXT Master mode) (MCKO is not available at EXT Master Mode)
FCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "0")
50%DVDD
BICK
(BCKP = "1")
50%DVDD
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH
SDTI
MSB
VIL
Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”)
Rev. 0.5
2007/10
- 15 -
[AK4634]
FCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "1")
50%DVDD
BICK
(BCKP = "0")
50%DVDD
tBSD
SDTO
50%DVDD
MSB
tSDS
SDTI
tSDH
VIH
MSB
VIL
Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”)
50%DVDD
FCK
tBFCK
dBCK
BICK
50%DVDD
tFSD
tBSD
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 5. Audio Interface Timing (PLL/EXT Master mode & Except DSP mode)
Rev. 0.5
2007/10
- 16 -
[AK4634]
1/fFCK
VIH
FCK
VIL
tFCKH
tBFCK
tBCK
VIH
BICK
(BCKP = "0")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "1")
VIL
Figure 6. Clock Timing (PLL Slave mode; PLL Reference clock = FCK or BICK pin & DSP mode; MSBS = “0”)
1/fFCK
VIH
FCK
VIL
tFCKH
tBFCK
tBCK
VIH
BICK
(BCKP = "1")
VIL
tBCKH
tBCKL
VIH
BICK
(BCKP = "0")
VIL
Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = “1”)
Rev. 0.5
2007/10
- 17 -
[AK4634]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fFCK
VIH
FCK
VIL
tFCKH
tFCKL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
1/fMCK
50%DVDD
MCKO
tMCKOH
tMCKOL
dMCK = tMCKOL x fMCK x 100%
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode)
Rev. 0.5
2007/10
- 18 -
[AK4634]
tFCKH
VIH
FCK
VIL
tFCKB
VIH
BICK
VIL
(BCKP = "0")
VIH
BICK
(BCKP = "1")
VIL
tBSD
SDTO
50%DVDD
MSB
tSDS
tSDH
VIH
SDTI
MSB
VIL
Figure 9. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = “0”)
tFCKH
VIH
FCK
VIL
tFCKB
VIH
BICK
VIL
(BCKP = "1")
VIH
BICK
(BCKP = "0")
VIL
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH
SDTI
MSB
VIL
Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = “1”)
Rev. 0.5
2007/10
- 19 -
[AK4634]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fFCK
VIH
FCK
VIL
tFCKH
tFCKL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 11. Clock Timing (EXT Slave mode)
VIH
FCK
VIL
tBFCK
tFCKB
VIH
BICK
VIL
tFSD
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH
SDTI
VIL
Figure 12. Audio Interface Timing (PLL, EXT Slave mode & Except DSP mode)
Rev. 0.5
2007/10
- 20 -
[AK4634]
VIH
CSN
VIL
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTI
C1
C0
R/W
VIL
Figure 13. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
Figure 14. WRITE Data Input Timing
Rev. 0.5
2007/10
- 21 -
[AK4634]
VIH
CSN
VIL
VIH
CCLK
VIL
tCCZ
tDCD
D3
CDTI
D2
D1
50%
DVDD
D0
Figure 15. Read Data Output Timing
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 16. I2C Bus Mode Timing
PMADC
bit
tPDV
SDTO
50%DVDD
Figure 17. Power Down & Reset Timing 1
tPD
PDN
VIL
Figure 18. Power Down & Reset Timing 2
Rev. 0.5
2007/10
- 22 -
[AK4634]
OPERATION OVERVIEW
■ System Clock
There are the following five clock modes to interface with external devices. (Table 1 and Table 2)
Mode
PMPLL bit M/S bit
PLL3-0 bit
PLL Master Mode
1
1
Table 4
PLL Slave Mode 1
Table 4
1
0
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
Table 4
1
0
(PLL Reference Clock: FCK or BICK pin)
EXT Slave Mode
0
0
x
EXT Master Mode
0
1
x
Table 1. Clock Mode Setting (x: Don’t care)
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: FCK or BICK pin)
MCKO bit
MCKO pin
0
“L” Output
1
256fs Output
0
“L” Output
1
0
Figure
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
MCKI pin
BICK pin
FCK pin
Master Clock
Input for PLL
(Note 29)
16fs/32fs/64fs
Output
1fs
Output
256fs Output
Master Clock
Input for PLL
(Note 29)
≥ 16fs
Input
1fs
Input
“L” Output
GND
16fs/32fs/64fs
Input
1fs
Input
≥ 32fs
Input
1fs
Input
32fs/64fs
Output
1fs
Output
EXT Slave Mode
0
“L” Output
EXT Master Mode
0
“L” Output
256fs/
512fs/
1024fs
Input
256fs/
512fs/
1024fs
Input
Note 29. 12MHz/13.5MHz/24MHz/27MHz
Table 2. Clock pins state in Clock Mode
Rev. 0.5
2007/10
- 23 -
[AK4634]
■ Master Mode/Slave Mode
The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4634 is in power-down mode (PDN pin = “L”) and exits reset state, the AK4634 is slave mode. After exiting reset
state, the AK4634 changes to master mode by bringing M/S bit = “1”.
When the AK4634 is in master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. The FCK and
BICK pins of the AK4634 should be pulled-down or pulled-up by about 100kΩ resistor externally to avoid the floating
state.
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 3. Select Master/Salve Mod
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4. Ether when the AK4634 is supplied to a stable clocks
after PLL is powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency changes, the PLL lock time is the
same.
1) Setting of PLL Mode
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
0
1
2
3
6
7
12
13
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
PLL Reference
Clock Input Pin
Input
Frequency
R and C of
VCOC pin
(Note 30)
R[Ω] C[F]
6.8k
220n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
PLL Lock
Time
(max)
FCK pin
1fs
160ms
BICK pin
16fs
2ms
BICK pin
32fs
2ms
BICK pin
64fs
2ms
MCKI pin
12MHz
20ms
MCKI pin
24MHz
20ms
MCKI pin
13.5MHz
20ms
MCKI pin
27MHz
20ms
Others
Others
N/A
Note 30. the tolerance of R is ±5%, the tolerance of C is ±30%
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
(default)
2) Setting of sampling frequency in PLL Mode.
When PLL2 bit is “1” (PLL reference clock input is the MCKI pin), the sampling frequency is selected by FS2-0 bits as
defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (N/A: Not available)
Rev. 0.5
2007/10
- 24 -
[AK4634]
When PLL2 bit is “0” (PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3-2
bits. (Table 6)
Mode
0
1
2
Others
FS3 bit
FS2 bit
Sampling Frequency
Range
0
0
x
x
(default)
7.35kHz ≤ fs ≤ 12kHz
0
1
x
x
12kHz < fs ≤ 24kHz
1
0
x
x
24kHz < fs ≤ 48kHz
Others
N/A
(x: Don’t care, N/A: Not available)
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”
FS1 bit
FS0 bit
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, irregular frequency clocks are output from FCK, BICK and MCKO pins after PMPLL bit = “0” Æ “1” or
sampling frequency is changed. After that PLL is unlocked, the BICK and FCK pins output “L” for a moment, and invalid
frequency clock is output from the MCKO pin at MCKO bit = “1”. If the MCKO bit is “0”, MCKO pin is output to “L”.
(Table 7)
When sampling frequency is changed, BICK and FCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
BICK pin
FCK pin
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
“L” Output
“L” Output
PLL Unlock
“L” Output
Invalid
Invalid
Invalid
PLL Lock
“L” Output
256fs Output
See Table 9
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin after PMPLL bit = “0” Æ “1” or sampling frequency is
changed. After that, 256fs is output from the MCKO pin when PLL is locked. ADC and DAC output invalid data when
the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACA and DACS bits in Addr=02H.
MCKO pin
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
PLL Unlock
“L” Output
Invalid
PLL Lock
“L” Output
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
PLL State
Rev. 0.5
2007/10
- 25 -
[AK4634]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (12MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, the MCKO, BICK and FCK
clocks are generated by an internal PLL circuit. The MCKO output frequency is fixed to 256fs, the output is enabled by
MCKO bit. The BICK is selected among 16fs, 32fs or 64fs, by BCKO1-0 bits. (Table 9)
In DSP mode, FCK output can select Duty 50% or High-output only during 1 BICK cycle (Table 10). Except DSP mode,
FCKO bit should be set “0”.
When BICK output frequency is 16fs, the audio interface format supports Mode 0 only (DSP Mode).
12MHz, 13.5MHz,
24MHz, 27MHz
DSP or μP
AK4634
MCKI
MCKO
BICK
FCK
256fs
16fs, 32fs, 64fs
1fs
MCLK
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 19. PLL Master Mode
BICK Output
Frequency
0
0
0
16fs
(default)
1
0
1
32fs
2
1
0
64fs
3
1
1
N/A
Table 9. BICK Output Frequency at Master Mode (N/A: Not available)
Mode
BCKO1
BCKO0
Mode
FCKO
FCK Output
0
0
Duty = 50%
1
1
High Width = 1/fBCK
Note 31. fBCK is BICK Output Frequency.
(default)
Table 10. FCK Output at PLL Master Mode and DSP Mode
Rev. 0.5
2007/10
- 26 -
[AK4634]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the MCKI, BICK or FCK pin. The required clock to the
AK4634 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. When BICK input frequency
is 16fs, the audio interface format supports Mode 0 only (DSP Mode).
a) PLL reference clock: MCKI pin
BICK and FCK inputs should be synchronized with MCKO output. The phase between MCKO and FCK is not important.
The MCKO pin outputs the frequency selected by FS3-0 bits (Table 5)
12MHz, 13.5MHz,
24MHz, 27MHz
AK4634
DSP or μP
MCKI
MCKO
BICK
FCK
256fs
16fs, 32fs, 64fs
1fs
MCLK
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
Rev. 0.5
2007/10
- 27 -
[AK4634]
b) PLL reference clock: BICK or LRCK pin
Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits. (Table 6)
AK4634
DSP or μP
MCKO
MCKI
BICK
FCK
16fs, 32fs, 64fs
1fs
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 21 PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4634
DSP or μP
MCKO
MCKI
BICK
FCK
≥16fs
1fs
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 22. PLL Slave Mode 2 (PLL Reference Clock: FCK pin)
The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC or SPK or
Programmable Filter is in operation (PMADC bit = “1”, PMDAC bit = “1”, PMSPK bit = “1”, PMPFIL bit = “1”). If these
clocks are not provided, the AK4634 may draw excess current and it is not possible to operate properly because utilizes
dynamic refreshed logic internally. If the external clocks are not present, the ADC, DAC, SPK and Programmable Filter
should be in the power-down mode.(PMADC = PMDAC = PMSPK = PMPFIL bits = “0”).
Rev. 0.5
2007/10
- 28 -
[AK4634]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4634 becomes EXT Slave mode. Master clock is input from the MCKI pin, the internal
PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate
are MCKI (256fs, 512fs or 1024fs), FCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with
FCK. The phase between these clocks is not important. The input frequency of MCKI is selected by FS1-0 bits. (Table 11)
Mode
0
1
2
3
FS3-2 bits
FS1 bit
FS0 bit
MCKI Input
Sampling Frequency
Frequency
Range
x
0
256fs
0
7.35kHz ≤ fs ≤ 48kHz (default)
x
1
1024fs
0
7.35kHz ≤ fs ≤ 13kHz
x
0
512fs
1
7.35kHz ≤ fs ≤ 26kHz
x
1
256fs
1
7.35kHz ≤ fs ≤ 48kHz
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) (x: Don’t care)
External Slave Mode does not support Mode 0 (DSP Mode) of Audio Interface Format.
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. (Table 12, Table 13)
S/N (fs=8kHz, 20kHzLPF + A-weighted)
DAC →AOUT
256fs
84dB
512fs
92dB
1024fs
92dB
Table 12. Relationship between MCKI and S/N of AOUT and SPK-Amp
MCKI
Output Noise Level
(SVDD=3.3V,fs=8kHz, 20kHzLPF + A-weighted)
MCKI
SDTI → SPK-Amp
256fs
-73dBV
512fs
-86dBV
1024fs
-88dBV
Table 13. Relationship between MCKI and Output Noise Level of SPK-Amp
The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC or SPK or
Programmable Filter is in operation (PMADC = PMDAC = PMSPK bit = PMPFIL bits = “1”). If these clocks are not
provided, the AK4634 may draw excess current and it is not possible to operate properly because utilizes dynamic
refreshed logic internally. If the external clocks are not present, the ADC, DAC, SPK and Programmable Filter should be
in the power-down mode (PMADC = PMDAC = PMSPK bit = PMPFIL bits = “0”).
AK4634
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
FCK
MCLK
≥ 32fs
1fs
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 23. EXT Slave Mode
Rev. 0.5
2007/10
- 29 -
[AK4634]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4634 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The
input frequency of MCKI is selected by FS1-0 bits (Table 14). The BICK is selected among 32fs or 64fs, by BCKO1-0
bits (Table 15). FCK bit should be set to “0”.
Mode
FS3-2 bits
FS1 bit
FS0 bit
MCKI Input
Sampling Frequency
Frequency
Range
x
0
256fs
0
0
7.35kHz ≤ fs ≤ 48kHz (default)
x
1
1024fs
1
0
7.35kHz ≤ fs ≤ 13kHz
x
0
512fs
2
1
7.35kHz ≤ fs ≤ 26kHz
x
1
256fs
3
1
7.35kHz ≤ fs ≤ 48kHz
Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (x: Don’t care)
External Master Mode does not support Mode 0 (DSP Mode) of Audio Interface Format.
MCKI should always be present whenever the ADC, DAC, SPK or Programmable Filter is in operation (PMADC =
PMDAC = PMSPK bit = PMPFIL bits = “1”). If MCKI is not provided, the AK4634 may draw excess current and it is not
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC, DAC,
SPK and Programmable Filter should be in the power-down mode (PMADC = PMDAC = PMSPK = PMPFIL bits = “0”).
AK4634
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
FCK
MCLK
32fs, 64fs
1fs
BCLK
FCK
SDTO
SDTI
SDTI
SDTO
Figure 24. EXT Master Mode
BICK Output
Frequency
0
0
0
N/A
(default)
1
0
1
32fs
2
1
0
64fs
3
1
1
N/A
Table 15. BICK Output Frequency at Master Mode (N/A: Not available)
Mode
BCKO1
BCKO0
Rev. 0.5
2007/10
- 30 -
[AK4634]
■ Audio Interface Format
Four types of data formats are available and are selected by setting the DIF1-0 bits. (Table 16) In all modes, the serial data
is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. FCK and
BICK are output from the AK4634 in master mode, but must be input to the AK4634 in slave mode.
In Mode 1-3, the SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO (ADC)
SDTI (DAC)
BICK
DSP Mode
DSP Mode
≥ 16fs
MSB justified
MSB justified
≥ 32fs
MSB justified
MSB justified
≥ 32fs
I2S compatible I2S compatible
≥ 32fs
Table 16. Audio Interface Format
Figure
See Table 17
Figure 25
Figure 26
Figure 27
(default)
In Mode0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit is “0”, SDTO data is output by rising edge of BICK, SDTI data is latched by falling edge of BICK.
When BCKP bit is “1”, SDTO data is output by falling edge of BICK, SDTI data is latched by rising edge of BICK.
MSB data position of SDTO and SDTI can be shifted by MSBS bit. The shifted period is a half of BICK.
MSBS bit BCKP bit
Audio Interface Format
0
0
Figure 28
0
1
Figure 29
1
0
Figure 30
1
1
Figure 31
Table 17. Audio Interface Format in Mode 0
(default)
If 16-bit data, the output of ADC, is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
FCK
0
1
2
8
3
9
10
11
12
13
14
15
0
1
2
3
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
15 14 13
SDTI(i)
15 14 13
0
1
2
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
3
14
15
16
17
18
31
15
15
Don’t Care
0
1
2
3
14
15
16
17
18
31
0
1
BICK(64fs)
SDTO(o)
15 14 13
SDTI(i)
Don’t Care
15:MSB, 0:LSB
2
1
0
15
15 14
1
0
Don’t Care
Data
1/fs
Figure 25. Mode 1 Timing
Rev. 0.5
2007/10
- 31 -
[AK4634]
FCK
0
1
2
8
9
10
11
12
13
14
15
0
1
2
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
15 14
8
7
6
5
4
3
2
1
0
SDTI(I)
15 14
8
7
6
5
4
3
2
1
0
0
1
2
3
14
15
16
17
18
31
15
15
Don’t Care
0
1
2
3
14
14
15
16
17
18
31
0
1
BICK(64fs)
SDTO(o)
15 14 13
13 2
1
0
SDTI(i)
15 14 13
13 2
1
0
15
Don’t Care
Don’t Care
15
15:MSB, 0:LSB
Data
1/fs
Figure 26. Mode 2 Timing
FCK
0
1
2
3
4
9
10
11
12
13
14
15
0
1
2
3
1
2
3
4
9
10
11
12
13
14
15
16
17
18
14
15
0
1
31
0
1
BICK(32fs)
SDTO(o)
15 14 13
SDTI(i)
15 14 13
0
1
2
3
4
7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
14
15
16
17
18
31
0
4
BICK(64fs)
SDTO(o)
15 14 13
2
1
0
SDTI(i)
15 14 13
2
1
0
15:MSB, 0:LSB
Don’t Care
Don’t Care
Data
1/fs
Figure 27. Mode 3 Timing
Rev. 0.5
2007/10
- 32 -
[AK4634]
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
15
0
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
15
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
2
8
9
10
11
12
13
30
31
0
15
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
1/fs
Don’t Care
1/fs
15:MSB, 0:LSB
Figure 28. Mode 0 Timing (BCKP = “0”, MSBS = “0”)
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
15
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
2
8
9
10
11
12
13
30
31
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
1/fs
Don’t Care
1/fs
15:MSB, 0:LSB
Figure 29. Mode 0 Timing (BCKP = “1”, MSBS = “0”)
Rev. 0.5
2007/10
- 33 -
[AK4634]
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
15
0
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
15
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
2
8
9
10
11
12
13
30
31
0
15
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
1/fs
Don’t Care
1/fs
15:MSB, 0:LSB
Figure 30. Mode 0 Timing (BCKP = “0”, MSBS = “1”)
FCK
15
0
1
8
2
8
9
10
11
12
13
14
15
0
1
8
2
8
9
10
11
12
13
14
BICK(16fs)
SDTO(o)
0
15 14
SDTI(i)
0
15 14
15
0
1
8
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
2
14
15
16
17
18
29
30
31
0
1
8
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
2
8
9
10
11
12
13
30
31
0
BICK(32fs)
SDTO(o)
15 14
SDTI(i)
15 14
8
2
1
0
2
1
0
Don’t Care
15 14
8
2
1
0
15 14
8
2
1
0
1/fs
Don’t Care
1/fs
15:MSB, 0:LSB
Figure 31. Mode 0 Timing (BCKP = “1”, MSBS = “1”)
Rev. 0.5
2007/10
- 34 -
[AK4634]
■ System Reset
When power-up, the PDN pin should be “L” and change to “H” after all power are supplied. “L” time of 150ns or more
is needed to reset in the AK4634.
The ADC enters an initialization cycle when the PMADC bit is changed from “0” to “1”. The initialization cycle time is
1059/fs, or 133ms@fs = 8kHz. During the initialization cycle, the ADC digital data outputs of both channels are forced to
a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete. The DAC
does not require an initialization cycle.
(Note) Off-set occurs in the initial data depending on the conditions of a microphone and cut-off frequency of HPF.
When Off-set becomes a problem, lengthen initialization time of ADC as ADRST bit = “0” or do not use initial
output data of ADC.
ADRST bit
0
1
Init Cycle
Cycle
fs = 8kHz
fs = 16kHz
1059/fs
132.4ms
66.2ms
291/fs
36.4ms
18.2ms
Table 18 Initialization cycle of ADC
fs = 48kHz
22.1ms
6.1ms
■ Thermal Shut Down
When the internal device temperature rises up irregularly (e.g. output pins of speaker amplifier are shortened), the
AK4634 is powered down automatically and then THDET bit becomes “1”. The powered-down speaker amplifier do not
return to normal operation unless SPK-Amp blocks of the AK4634 are reset by the PDN pin “L”. The device status can be
monitored by THDET bit.
■ MIC/LINE Input Selector
The AK4634 has an input selector. When MDIF bit is “0”, LIN bit selects the MIC pin or the LIN pin. When MDIF bit is
“1”, full-differential input is available.
MDIF bit
0
0
1
LIN bit
Input circuit
Input pin
0
Single-End
MIC pin
1
Single-End
LIN pin
x
Differential
MICP/MICN pin
Table 19. Input Select (x: Don’t care)
(default)
AK4634
MIC/MICP pin
LIN bit
ADC
LIN/MICN pin
MDIF bit
Figure 32 Input Selector
Rev. 0.5
2007/10
- 35 -
[AK4634]
AK4634
MIC-Power
MPI pin
1k
MICP pin
Audio
MICNpin
A/D
HPF
I/F
MIC-Amp
BICK pin
FCK pin
STDO pin
1k
Figure 33. MIC Differential Input Circuit
■ MIC Gain Amplifier
The AK4634 has a Gain Amplifier for Microphone input. These gains are selected by the MGAIN3-0 bit. The typical
input impedance is 30kΩ.
MGAIN3 bit
0
0
0
0
0
0
0
0
1
1
MGAIN2 bit
MGAIN1 bit
MGAIN0 bit
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
Others
Table 20. Input Gain
Input Gain
0dB
+20dB
+26dB
+32dB
+10dB
+17dB
+23dB
+29dB
+3dB
+6dB
N/A
(default)
■ MIC Power
The MPI pin supplies power for the Microphone. This output voltage is proportional to 0.8 x AVDD typically and the
load resistance is minimum 2kΩ. Any capacitor must not be connected to the MPI pin, directly. (Figure 34)
AK4634
MPI pin
MIC-Power
≥ 2k
Audio
MIC pin
A/D
HPF
I/F
BICK pin
FCK pin
STDO pin
MIC-Amp
Figure 34. MIC Block Circuit
Rev. 0.5
2007/10
- 36 -
[AK4634]
■ Digital Block
The digital block consists of block diagram as shown in Figure 35. The AK4634 can choose various signal processing on
a recording path or a playback path by setting ADCPF bit, PFDAC bit and PFSDO bit. (Figure 35 - Figure 38, Table 21)
PMADC bit
SDTI
ADC
1st Order
HPFAD bit
HPF
“1”
“0”
ADCPF bit
PMPFIL bit
HPF bit
1st Order
HPF
1st Order
LPF bit
LPF
5 Band
EQ5-1 bits
EQ
ALC
(Volume)
“0”
“1”
“1”
PFSDO bit
“0”
PFDAC bit
PMDAC bit
DATT
SDTO
SMUTE
DAC
(1) ADC: Include the Digital Filter (LPF) for ADC as shown in “FILTER CHRACTERISTICS”.
(2) DAC: Include the Digital Filter (LPF) for DAC as shown in “FILTER CHRACTERISTICS”.
(3) HPF: High Pass Filter. Applicable to use as Wind-Noise Reduction Filter. (See “Digital Programmable Filter
Circuit”.)
(4) LPF: Low Pass Filter (See “Digital Programmable Filter Circuit”.)
(5) 5-Band EQ: Applicable to use as Equalizer or Notch Filter. (See “Digital Programmable Filter Circuit”.)
(6) ALC: Input Digital Volume with ALC function. (See “Input Digital Volume” and “ALC Operation”.)
(7) DATT: 4-step Digital Volume for recording path. (See “Output Digital Volume 2”)
(8) SMUTE: Soft mute. (See “SOFT MUTE”.)
Figure 35. Digital Block Path Select
Rev. 0.5
2007/10
- 37 -
[AK4634]
Mode
Recording Mode
Reproduction Mode
Loop Back Mode
ADCPF bit
PFDAC bit
PFSDO bit
1
0
1
0
1
0
1
1
1
Table 21 Recording Reproduction Mode
ADC
DAC
2nd Order
1st Order
5 Band
HPF
LPF
EQ
SMUTE
Figure
Figure 36
Figure 37
Figure 38
ALC
(Volume)
DATT
Figure 36. Path at Recording Mode (default)
1st Order
ADC
DAC
HPF
SMUTE
ADC
DAC
DATT
ALC
5 Band
EQ
Figure 37. Path at Playback Mode
(Volume)
2nd Order
1st Order
5 Band
HPF
LPF
EQ
SMUTE
1st Order
1st Order
LPF
HPF
ALC
(Volume)
DATT
Figure 38. Path at Recording & Playback Mode
Rev. 0.5
2007/10
- 38 -
[AK4634]
■ Digital Programmable Filter Circuit
The AK4634 has 2 steps of 1st order HPF, 1st order LPF and 5-band Equalizer built-in in a recording path and a playback
path.
(1)
High Pass Filter (HPF)
Normally, this HPF is used as a Wind-Noise Reduction Filter. This is composed with 2 steps of 1st order HPF. The
coefficient of both HPF is the same and set by F1A13-0 bits and F1B13-0 bits. HPFAD bit controls ON/OFF of the 1st
step HPF and HPF bit controls ON/OFF of the 2nd step HPF. When the HPF is OFF, the audio data passes this block by
0dB gain. The coefficient should be set when HPFAD = HPF bits = “0” or PMADC = PMPFIL bits = “0”.
fs : Sampling frequency
fc : Cut-off frequency
Register setting (Note 32)
HPF: F1A[13:0] bits = A, F1B[13:0] bits = B
(MSB = F1A13, F1B13; LSB = F1A0, F1B0)
1
1− tan (πfc/fs)
A=
,
B=
1 + tan (πfc/fs)
1 + tan (πfc/fs)
The cut-off frequency should be set as below.
fc/fs ≥ 0.0001 (fc min = 1.6Hz at 16kHz)
(2) Low Pass Filter(LPF)
This is composed with 1st order LPF. F2A13-0 bits and F2B13-0 bits set the coefficient of LPF. LPF bit controls ON/OFF
of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient should be set when LPF
bit = “0” or PMPFIL bits = “0”.
fs : Sampling frequency
fc : Cut-off frequency
Register setting (Note 32)
LPF: F2A[13:0] bits =A, F2B[13:0] bits =B
(MSB=F2A13, F1B13; LSB=F2A0, F2B0)
1 − 1 / tan (πfc/fs)
1
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
The cut-off frequency should be set as below.
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
Rev. 0.5
2007/10
- 39 -
[AK4634]
(3) 5-band Equalizer
This block can be used as Equalizer or Notch Filter. ON/OFF 5-band Equalizer (EQ1, EQ2, EQ3, EQ4 and EQ5) can be
controlled independently by EQ1, EQ2, EQ3, EQ4 and EQ5 bits. When Equalizer is OFF, the audio data passes this block
by 0dB gain. E1A15-0, E1B15-0 and E1C15-0 bits set the coefficient of EQ1. E2A15-0, E2B15-0 and E2C15-0 bits set
the coefficient of EQ2. E3A15-0, E3B15-0 and E3C15-0 bits set the coefficient of EQ3. E4A15-0, E4B15-0 and E4C15-0
bits set the coefficient of EQ4. E5A15-0, E5B15-0 and E5C15-0 bits set the coefficient of EQ5. Each EQx coefficient
setting must be made when EQx bit (corresponding bit to EQx) is “0” or PMPFIL bit is “0”.
fs : The Sampling frequency
fo1 ~ fo5 : The Center frequency
fb1 ~ fb5 : The Band width where the gain is 3dB different from center frequency
K1 ~ K5 : The Gain ( -1 ≤ Kn < 3 )
Register setting (Note 32)
EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1
EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2
EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3
EQ4: E4A[15:0] bits =A4, E4B[15:0] bits =B4, E4C[15:0] bits =C4
EQ5: E5A[15:0] bits =A5, E5B[15:0] bits =B5, E5C[15:0] bits =C5
(MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15, E4A15, E4B15, E4C15,
E5A15, E5B15, E5C15 ; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0, E4A0, E4B0,
E4C0, E5A0, E5B0, E5C0)
An = Kn x
tan (πfbn/fs)
1 + tan (πfbn/fs)
2
, Bn = cos(2π fon/fs) x
1 + tan (πfbn/fs)
,
Cn =
1 − tan (πfbn/fs)
1 + tan (πfbn/fs)
(n = 1, 2, 3, 4, 5)
The center frequency should be set as below
fon / fs < 0.497
When gain of K is set to “−1”, the equalizer becomes notch filter. When it is used as notch filter, central frequency of a
real notch filter deviates from the above-mentioned calculation, if its central frequency of each band is near. The control
soft that is attached to the evaluation board has a function that revises a gap of frequency, and calculates the coefficient.
When its central frequency of each band is near, revise the central frequency and confirm the frequency response.
Note 32.
[Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)]
X = (Real number of filter coefficient calculated by the equations above) x 213
X should be rounded to integer, and then should be translated to binary code (2’s complement).
MSB of each filter coefficient setting register is sine bit.
Rev. 0.5
2007/10
- 40 -
[AK4634]
■ Input Digital Volume (Manual Mode)
When ADCPF bit = “1” and ALC1 bit = “0”, ALC block becomes an input digital volume (manual mode). The digital
volume’s gain is set by IVOL7-0 bits as shown in Table 22. The IVOL value is changed at zero cross or zero cross time
out. The zero crossing timeout period is set by ZTM1-0 bits.
IVOL7-0bits
F1H
F0H
EFH
:
92H
91H
90H
:
2H
1H
0H
GAIN(0dB)
Step
+36.0
+35.625
+35.25
:
0.375dB
+0.375
0.0
-0.375
:
-53.625
-54.0
MUTE
Table 22. Input Digital Volume Setting
(default)
When writing to the IVOL7-0 bits continually, the control register should be written in an interval more than zero
crossing timeout. If not, zero crossing counter could be reset at each time and volume is not be changed. However, it could
be ignored when writing the same register value as the last time. At this time, zero crossing counter is not reset, so it can
be written in an interval less than zero crossing timeout.
Rev. 0.5
2007/10
- 41 -
[AK4634]
■ Output Digital volume (Manual mode)
When ADCPF bit = “0” and ALC2 bit = “0”, ALC block become an output digital volume (manual mode). The digital
volume’s gain is set by OVOL7-0 bits as shown in Table 23. The OVOL7-0 bits value are reflected to this output volume
at zero cross or zero cross time out. The zero crossing timeout period is set by ZTM1-0 bits.
OVOL7-0bits
F1H
F0H
EFH
:
92H
91H
90H
:
2H
1H
0H
GAIN(0dB)
Step
+36.0
+35.625
+35.25
:
0.375dB
+0.375
0.0
-0.375
:
-53.625
-54.0
MUTE
Table 23 Output Digital Volume Setting
(default)
When writing to the OVOL7-0 bits continually, the control register should be written by an interval more than zero
crossing timeout. If not, zero crossing counter could be reset at each time and volume is not be changed. However, It
could be ignored when writing a same register value as the last time. At this time, zero crossing counter is not reset, so it
can be written by an interval less than zero crossing timeout.
■ Output Digital Volume2
The AK4634 has 4 steps output volume in addition to the volume setting by OVOL7-0 bits. This volume is set by
DATT1-0 bits as shown in Table 24.
DATT1-0bits
0H
1H
2H
3H
GAIN(0dB)
Step
0.0
(default)
6.0dB
-6.0
-12.0
-18.1
Table 24. Output Digital Volume2 Setting
Rev. 0.5
2007/10
- 42 -
[AK4634]
■ ALC Operation
ALC Operation works in ALC block. When ADCPF bit = “1”, ALC operation is enable for recording path. When ADCPF
bit = “0”, ALC operation is enable for playback path. The ON/OFF of ALC operation for recording is controlled by ALC1
bit and the ON/OFF of ALC operation for playback is controlled by ALC2 bit.
1.
ALC Limiter Operation
When the ALC limiter is enabled, and output exceeds the ALC limiter detection level (Table 25), the volume value is
attenuated by the amount defined in LMAT1-0 bits (Table 26) automatically.
When the ZELMN bit = “0” (zero crossing detection valid), the VOL value is changed by ALC limiter operation at the
zero crossing point or zero crossing timeout. Zero crossing timeout period is set by ZTM1-0 bit that in common with ALC
recovery zero crossing timeout period’s setting (Table 27).At LFST bit = “1”, VOL value is attenuated 1step immediately
(period: 1/fs) when output Level is over FS(Digital Full Scale).
When the ZELMN bit = “1” (zero crossing detection invalid), VOL value is changed immediately (period: 1/fs) by ALC
limiter operation. The attenuation for limiter operation is fixed to 1 step and not controlled by setting LMAT1-0 bits.
After finishing the attenuate operation, if ALC bit does not change to “0”, the operation repeats when the output signal
level exceeds the ALC limiter detection level.
LMTH1
0
0
1
1
LMTH0 ALC Limiter Detection Level ALC Recovery Waiting Counter Reset Level
0
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
1
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
0
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
1
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 25. ALC Limiter Detection Level / Recovery Waiting Counter Reset Level
(default)
ALC1 Limiter ATT Step
LMAT1
LMAT0
0
0
1
1
0
1
0
1
ZTM1
ZTM0
0
0
1
1
0
1
0
1
ALC1 Output ALC1 Output
≥ LMTH
≥ FS
ALC1 Output
≥ FS + 6dB
ALC1 Output
≥ FS + 12dB
1
1
1
2
2
2
2
4
4
1
2
4
Table 26. ALC Limiter ATT Step Setting
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 27. ALC Zero Crossing Timeout Period Setting
Rev. 0.5
1
2
8
8
(default)
(default)
2007/10
- 43 -
[AK4634]
2.
ALC Recovery Operation
The ALC recovery operation waits for the WTM2-0 bits (Table 28) to be set after completing the ALC limiter operation.
If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 25) during the wait time, the ALC
recovery operation is executed. The VOL value is automatically incremented by RGAIN1-0 bits (Table 29) up to the set
reference level (Table 30, Table 31) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 27).
The ALC recovery operation is executed in a period set by WTM2-0 bits.
For example, when the current VOL value is 30H and RGAIN1-0 bits are set to “01”(2 steps), VOL is changed to 32H by
the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the VOL value
exceeds the reference level (IREF7-0 or OREF5-0), the VOL values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation
becomes faster than a normal recovery operation. When large noise is input to microphone instantaneously, the quality of
small level in the large noise can be improved by this fast recovery operation. The speed of first recovery operation is set
by RFST1-0 bits (Table 32).
WTM2
WTM1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
ALC Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
0
128/fs
16ms
8ms
2.9ms
1
256/fs
32ms
16ms
5.8ms
0
512/fs
64ms
32ms
11.6ms
1
1024/fs
128ms
64ms
23.2ms
0
2048/fs
256ms
128ms
46.4ms
1
4096/fs
512ms
256ms
92.9ms
0
8192/fs
1024ms
512ms
185.8ms
1
16384/fs
2048ms
1024ms
371.5ms
Table 28. ALC Recovery Operation Waiting Period
WTM0
RGAIN1
0
0
1
1
RGAIN0
GAIN STEP
0
1
0.375dB
1
2
0.750dB
0
3
1.125dB
1
4
1.500dB
Table 29. ALC Recovery GAIN Step
Rev. 0.5
(default)
(default)
2007/10
- 44 -
[AK4634]
IREF7-0bits
GAIN(0dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
C5H
+19.5
(default)
0.375dB
:
:
92H
+0.375
91H
0.0
90H
-0.375
:
:
2H
-53.625
1H
-54.0
0H
MUTE
Table 30. Reference Level at ALC Recovery operation for recoding
OREF5-0bits
GAIN(0dB)
Step
3CH
+36.0
3BH
+34.5
3AH
+33.0
:
:
28H
+6.0
(default)
1.5dB
:
:
25H
+1.5
24H
0.0
23H
-1.5
:
:
2H
-51.0
1H
-52.5
0H
-54.0
Table 31. Reference Level at ALC Recovery operation for playback
RFST1 bit
RFST0 bit
Recovery Speed
0
0
4 times
(default)
0
1
8 times
1
0
16times
1
1
N/A
Table 32. First Recovery Speed Setting (N/A: Not available)
Rev. 0.5
2007/10
- 45 -
[AK4634]
3.
The Volume at the ALC Operation
The current volume value at the ALC operation is reflected by VOL7-0 bits. It is enable to check the current volume value
by reading the register value of VOL7-0 bits.
This function is available only at the time of 3-wire mode. The volume value at the ALC operation can
not be read in I2C mode.
VOL7-0bits
GAIN(0dB)
F1H
F0H
EFH
:
C5H
:
92H
91H
90H
:
2H
1H
0H
+36.0
+35.625
+35.25
:
+19.5
:
+0.375
0.0
−0.375
:
−53.625
−54.0
MUTE
Table 33. Value of VOL7-0 bits
4.
Example of the ALC Operation for Recording Operation
Table 34 shows the examples of the ALC setting for mic recording.
fs=8kHz
Operation
−4.1dBFS
Enable
16ms
Register Name
Comment
LMTH1-0
ZELM
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be more than or
000
16ms
equal to ZTM1-0 bits
Maximum gain at recovery operation
C5H
19.5dB
Gain of IVOL
C5H
19.5dB
Limiter ATT step
00
1step
Fast Limiter Operation
1
ON
Recovery GAIN step
00
1 step
ALC enable
1
Enable
Speed of Fast Recovery
00
4 times
Table 34. Example of the ALC Setting (Recording)
WTM2-0
IREF7-0
IVOL7-0
LMAT1-0
LFST
RGAIN1-0
ALC1
FRSL1-0
Data
01
0
00
Rev. 0.5
Data
01
0
01
fs=16kHz
Operation
−4.1dBFS
Enable
16ms
001
16ms
C5H
C5H
00
1
00
1
00
19.5dB
19.5dB
1step
ON
1 step
Enable
4times
2007/10
- 46 -
[AK4634]
5. Example of ALC for Playback Operation
Table 35 shows the example of the ALC setting for playback.
fs=8kHz
Operation
−4.1dBFS
Enable
16ms
Register Name
Comment
LMTH1-0
ZELM
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be more than or
000
16ms
equal to ZTM1-0 bits
Maximum gain at recovery operation
28
+6dB
Gain of IVOL
91
0dB
Fast Limiter Operation
1
ON
Limiter ATT step
00
1step
Recovery GAIN step
00
1 step
ALC enable
1
Enable
Speed of Fast Recovery
00
4 times
Table 35. Examples of the ALC Setting (Play back)
WTM2-0
OREF5-0
OVOL7-0
LFST
LMAT1-0
RGAIN1-0
ALC2
FRSL1-0
Data
01
0
00
Rev. 0.5
Data
01
0
01
fs=16kHz
Operation
−4.1dBFS
Enable
16ms
001
16ms
28
91
1
00
00
1
00
+6dB
0dB
ON
1step
1 step
Enable
4 times
2007/10
- 47 -
[AK4634]
The following registers must not be changed during the ALC operation. These bits should be changed, after the ALC
operation is finished by ALC1 bit = ALC2 bit = “0” or PMPFIL bit = “0”. After ALC1 bit and ALC2 bit set to “0” or
PMPFIL bit sets to “0”, when ALC is restarted, the waiting time of zero crossing timeout is not needed.
LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, IREF7-0/OREF7-0, ZELM, RFST1-0, LFST
Example:
Limiter = Zero crossing Enable
Manual Mode
Recovery Cycle = 16ms@8kHz
Limiter and Recovery Step = 1
WR (ZTM1-0, WTM2-0)
LFST = 1
Maximum Gain = +19.5dB
Limiter Detection Level = −4.1dBFS
WR (IREF7-0/OREF5-0)
ALC1 bit = “1”
WR (IVOL7-0/OVOL7-0)
*1
(1) Addr=06H, Data=00H
WR (RGAIN1, LMTH1,RFST1-0)
(2) Addr=08H, Data=C5H
WR (LFST,LMAT1-0, RGAIN0, ZELMN, LMTH0)
WR (ALC1= “1”)
(3) Addr=09H, Data=C5H
*2
ALC Operation
(4) Addr=0BH, Data=28H
(5) Addr=07H, Data=A1H
Note : WR : Write
*1: The value of volume at starting should be the same or smaller than REF’s.
*2: When setting ALC1 bit or ALC2 bit to “0”, the operation is shifted to manual mode after passing the zero crossing
time set by ZTM1-0 bits.
Figure 39. Registers set-up sequence at the ALC operation
Rev. 0.5
2007/10
- 48 -
[AK4634]
■ SOFTMUTE
Soft mute operation is performed in the digital input domain. When the SMUTE bit changes to “1”, the input signal is
attenuated by −∞ (“0”) during the cycle of 245/fs (31msec@fs=8kHz). When the SMUTE bit is returned to “0”, the mute
is cancelled and the input attenuation gradually changes to 0dB during the cycle of 245/fs (31msec@fs=8kHz). If the soft
mute is cancelled within the cycle of 245/fs (31msec@fs=8kHz), the attenuation is discontinued and returned to 0dB. The
soft mute for Playback operation is effective for changing the signal source without stopping the signal transmission.
S M U T E bit
245/fs
0dB
245/fs
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 40. Soft Mute Function
(1) The input signal is attenuated by −∞ (“0”) during the cycle of 245/fs (31msec@fs=8kHz).
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within the cycle of 245/fs (31msec@fs=8kHz), the attenuation is discounted and returned
to 0dB within the same cycle.
Rev. 0.5
2007/10
- 49 -
[AK4634]
■ MONO LINE OUTPUT (AOUT pin)
A signal of DAC is output from the AOUT pin. When the DACA bit is “0”, this output is OFF. When the LOVL bit is “1”,
this gain changes to +2dB. The load resistance is 10kΩ(min). When PMAO bit is “0” and AOPSN bit is “0”, the mono
line output enters power-down and is pulled down by 100Ω(typ). If PMAO bit is controlled at AOPS bit = “1”, POP noise
will be reduced at power-up and down. Then, this line should be pulled down by 20kΩ of resister after C-coupling shown
in Figure 41. This rising and falling time is max 300 ms at C = 1.0μF . When PMAO bit is “1” and AOPS bit is “0”, the
mono line output enters power-up state.
LOVL bits
Gain
0
0dB
(default)
1
+2dB
Table 36. Mono line output volume setting
1μF
AOUT
220Ω
20kΩ
Figure 41. AOUT external circuit when using POP Reduction function
AOUT Control Sequence in case of using POP Reduction Circuit
(2 )
(5 )
P M A O b it
(1 )
(3 )
(4 )
(6 )
A O P S b it
A O U T p in
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 42. Mono Line Output Control Sequence when using POP Reduction function
(1) Set AOPS bit = “1”. Mono line output enters the power-save mode.
(2) Set PMAO bit = “1”. Mono line output exits the power-down mode.
AOUT pin rises up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF.
(3) Set AOPS bit = “0” after AOUT pin rises up. Mono line output exits the power-save mode.
Mono line output is enabled.
(4) Set AOPS bit = “1”. Mono line output enters power-save mode.
(5) Set PMAO bit = “1”. Mono line output enters power-down mode.
AOUT pin falls down to VSS1. Fall time is 200ms (max 300ms) at C=1μF.
(6) Set AOPS bit = “0” after AOUT pin falls down. Mono line output exits the power-save mode.
Rev. 0.5
2007/10
- 50 -
[AK4634]
■ Speaker Output
AK4634 has a Mono Class-D Speaker-Amp. Power supply for Speaker-Amp(SVDD) can be set from 2.2V up to 4.0V.
The Speaker is mono and BTL output, and can drive dynamic speaker and piezo speaker without LPF (filter-less). This
speaker can output 400W@8Ω at SVDD = 3.3V, SPKG bit = “0”. This gain is set by SPKG bit (Table 37). The output
level of speaker amp is depended on voltage of SVDD and SPKG bit.
SPKG bit
Gain
0
0dB
1
+2dB (Note 33)
Note 33. The signals more than -2dBFS clip.
Table 37. SPK- Amp Gain
The power up/down speaker amp is controlled by PMSPK bit. When PMSPK bit is “0”, the SPP and SPN pins output
VSS3 level. Also ON/OFF of speaker amp is controlled by SPOUTE bit. When SPOUTE bit is “0”, the SPP and SPN pins
are in VSS3-state forcibly. When the outputting from DAC to speaker, PMDAC bit should be set to “1”.
Follow the following sequence.
P M S P K b it
S P O U T E b it
S P P p in
N o r m a l O u tp u t
S P N p in
N o r m a l O u tp u t
Figure 43. Power-up/Power-down Timing for Speaker-Amp
Rev. 0.5
2007/10
- 51 -
[AK4634]
<Caution for using Piezo Speaker>
When a piezo speaker is used, resistances more than 10Ω should be connected between the SPP/SPN pins and speaker in
series, respectively, as shown in Figure 44. Zener diodes should be connected between speaker and GND as shown in
Figure 44, in order to protect SPK-Amp of the AK4634 from the power that is the piezo speaker output when the speaker
is pressured. Zener diodes of the following Zener voltage should be used.
92% of SVDD ≤ Zener voltage of Zener diodo (ZD of Figure 44) ≤ SVDD+0.3V
Ex) In case of SVDD = 3.8V :3.5V ≤ ZD ≤ 4.1V
For example, Zener diode which Zener voltage is 3.9V(Min 3.7V, Max 4.1V) can be used.
ZD
SPK-Amp
SPP
≥10Ω
SPN
≥10Ω
ZD
Figure 44. Circuit of Speaker Output (using a piezo speaker)
Rev. 0.5
2007/10
- 52 -
[AK4634]
■ BEEP Generate
The AK4634 generates and output square wave from speaker amp. After outputting the signal during the time set by
BPON6-0 bits, the AK4634 stops the output signal during the time set by BPOFF6-0 bits (Figure 46). The repeat count is
set by BPTM6-0 bit, and the output level is set by BPLVL2-0 bits. When BPCNT bit is “0”, if BPOUT bit is written “1”,
the AK4634 outputs the beep for the times of repeat count. When the output finish, BPOUT bit is set to “0” automatically.
When BPCNT bit is set to “1”, it outputs the beep in succession regardless of repeat count, on-time and off-time.
< Setting parameter >
1) Output Frequency ( Table 38 ~ Table 40)
2) ON Time (Table 41)
3) OFF Time (Table 42)
4) Repeat Count (Table 43)
5) Output Level (Table 44)
BPFR1-0, BPON7-0, BPOFF7-0, BPTM6-0 and BPLVL3-0 bits should be set when BPOUT =BPCNT
= “0”.
BPCNT bit is given priority in BPOUT bit. When BPOUT bit be set to “1”, if BPCNT bit is set to “0”,
BPOUT bit is set to “0” forcibly.
DATT2
SMUTE
DAC
Line Out Amp
Class-D SPK-Amp
BEEP
Generator
LPF
Figure 45. BEEP signal output path
BEEP Output
ON Time
OFF Time
Repeat Count
Figure 46. Beep output
Rev. 0.5
2007/10
- 53 -
[AK4634]
Output frequency of BEEP Generator [Hz]
fs = 44.1kHz system
fs = 48kHz system
(Note 35)
(Note 34)
00
4000
4009
(default)
01
2000
2005
10
1000
1002
11
N/A
Note 34. Sampling frequency is 8kHz, 16kHz, 32kHz or 48kHz.
Note 35. Sampling frequency is 11.025kHz, 22.05kHz or 44.1kHz.
Table 38. Beep signal frequency (PLL Master/Slave Mode: reference clock: MCKI) (N/A: Not available)
BPFR1-0 bit
Output frequency of BEEP Generator [Hz]
BPFR1-0 bit
FS3-2 bits = “00”
FS3-2 bits = “01”
FS3-2 bits = “10”
00
fs/2.75
fs/5.5
fs/11
(default)
01
fs/5.5
fs/11
fs/22
10
fs/11
fs/22
fs/44
11
N/A
Table 39. Beep signal frequency ( PLL Slave Mode: reference clock : FCK/BICK) (N/A: Not available)
BPFR1-0 bit
00
01
10
11
Output frequency of BEEP Generator [Hz]
FS1-0 bits = “01”
FS1-0 bits = “10”
FS1-0 bits = “11”
fs/2.75
fs/55
fs/11
fs/5.5
fs/11
fs/22
fs/11
fs/22
fs/44
N/A
Table 40. Beep signal frequency (EXT Slave/Master Mode) (N/A: Not available)
FS1-0 bits = “00”
fs/11
fs/22
fs/44
(default)
ON Time of BEEP Generator [msec]
Step [msec]
fs = 48kHz
fs = 44.1kHz
fs = 48kHz
fs = 44.1kHz
system
system
system
system
(Note 34)
(Note 35)
(Note 34)
(Note 35)
0H
8.0
7.98
8.0
7.98
(default)
1H
16.0
15.86
2H
24.0
23.95
3H
32.0
31.93
4H
40.0
39.9
:
:
:
FDH
2032
2027.3
FEH
2040
2035.3
FFH
2048
2043.4
Note 34. Sampling frequency is 8kHz, 16kHz, 32kHz or 48kHz.
Note 35. Sampling frequency is 11.025kHz, 22.05kHz or 44.1kHz.
Table 41. Beep output ON-time (PLL Master/Slave Mode reference clock: MCKI)
BPON7-0 bit
Rev. 0.5
2007/10
- 54 -
[AK4634]
OFF Time of BEEP Generator [msec]
Step [msec]
fs = 48kHz
fs = 44.1kHz
fs = 48kHz
fs = 44.1kHz
system
system
system
system
(Note 34)
(Note 35)
(Note 34)
(Note 35)
0H
8.0
7.98
8.0
7.98
(default)
1H
16.0
15.86
2H
24.0
23.95
3H
32.0
31.93
4H
40.0
39.9
:
:
:
FDH
2032
2027.3
FEH
2040
2035.3
FFH
2048
2043.4
Note 34. Sampling frequency is 8kHz, 16kHz, 32kHz or 48kHz.
Note 35. Sampling frequency is 11.025kHz, 22.05kHz or 44.1kHz.
Table 42. Beep output OFF-time (PLL Master/Slave Mode reference clock: MCKI)
BPOFF7-0 bit
BPTM6-0 bit
Repeat Count
0H
1
(default)
1H
2
2H
3
3H
:
:
125
7DH
126
7EH
127
7FH
128
Table 43. Beep output Repeat Count
BPLVL3-0 bit
Beep Output Level
STEP
0H
0dB
(default)
1H
−3dB
3dB
2H
−6dB
3H
−9dB
4H
−12dB
5H
−18dB
6dB
6H
−24dB
7H
−30dB
Note 36. Power supply is 3.3V
Note 37. Beep output amplitude as 0dB setting is 4.4Vpp@ load resistance = 8Ω + 10µH, SVDD=3.3V
Table 44. Beep output level
Rev. 0.5
2007/10
- 55 -
[AK4634]
■ Serial Control Interface
(1) 3-wire Serial Control Mode (I2C pin = “L”)
Internal registers may be written and read by using the 3-wire µP interface pins (CSN, CCLK and CDTIO). The data on
this interface consists of Read/Write, Register address (MSB first, 7bits) and Control data (MSB first, 8bits). Address and
data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. Data writing is valid on the
rising edge of the 16th CCLK after the falling edge of CSN. CSN should be set to “H” every after a data writing for each
address. In reading operation, the CDTIO pin changes to output mode at the falling edge of 8th CCLK and outputs
D7-D0. The output finishes on the rising edge of CSN. However this reading function is available only at READ bit = “1”.
When READ bit = “0”, the CDTIO pin stays as Hi-Z even after the falling edge of 8th CCLK. The CDTIO pin is placed
in a Hi-Z state except outputting data at read operation mode. The clock speed of CCLK is 5MHz (max). The value of
internal registers is initialized at the PDN pin = “L”.
Note 38. It is available for reading the address 00H ~ 11H, 20H ~ 24H and 30H. When reading the address 12H ~ 1FH,
25H ~ 2F and 31H ~ 4FH, the register values are invalid.
CSN
0
CCLK
Clock, “H” or “L”
CDTIO
“H” or “L”
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Clock, “H” or “L”
A6 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
R/W:
A6-A0:
D7-D0:
“H” or “L”
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Control data
Figure 47. Serial Control I/F Timing
Rev. 0.5
2007/10
- 56 -
[AK4634]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4634 supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected
to (DVDD+0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 48 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 54). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant seven bits of the slave address are fixed as “0010010” (Figure 49). If the slave address
matches that of the AK4634, the AK4634 generates an acknowledge and the operation is executed. The master must
generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
(Figure 55). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write
operation is to be executed.
The second byte consists of the control register address of the AK4634. The format is MSB first, and those most
significant 1-bits are fixed to zeros (Figure 50). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 51). The AK4634 generates an acknowledge after each byte is received. A data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition (Figure 54).
The AK4634 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4634
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 4FH prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 56) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 48. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
1
0
R/W
A2
A1
A0
D2
D1
D0
Figure 49. The First Byte
0
A6
A5
A4
A3
Figure 50. The Second Byte
D7
D6
D5
D4
D3
Figure 51. Byte Structure after the second byte
Rev. 0.5
2007/10
- 57 -
[AK4634]
(2)-2. READ Operations
Set the R/W bit = “1” for READ operation of the AK4634. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 4FH prior to generating a stop condition, the address
counter will “roll over” to 00H and the data of 00H will be read out.
Note 38. It is available for reading the address 00H ~ 11H, 20H ~ 24H and 30H. When reading the address 12H ~ 1FH,
25H ~ 2F and 31H ~ 4FH, the register values are invalid.
The AK4634 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4634 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit “1”, the AK4634 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but instead generates a stop condition, the AK4634
ceases the transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
A
C
K
P
MN
AA
SC
T
EK
R
MA
AC
SK
T
E
R
Figure 52. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4634 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but instead generates a stop condition, the AK4634 ceases the transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 53. RANDOM ADDRESS READ
Rev. 0.5
2007/10
- 58 -
[AK4634]
SDA
SCL
S
P
start condition
stop condition
Figure 54. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 55. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 56. Bit Transfer on the I2C-Bus
Rev. 0.5
2007/10
- 59 -
[AK4634]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Digital Volume Control
Digital Volume Control
ALC Mode Control 3
Reserved
ALC LEVEL
Signal Select 3
Thermal Shutdown
Signal Select 4
Digital Filter Select 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HPF Co-efficient 0
HPF Co-efficient 1
HPF Co-efficient 2
HPF Co-efficient 3
BEEP Frequency
BEEP ON Time
BEEP OFF Time
BEEP Repeat Count
BEEP VOL/Control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
D7
PMPFIL
0
SPOUTE
PFSDO
PLL3
ADRST
0
LFST
IREF7
IVOL7
OVOL7
RGAIN1
0
VOL7
DATT1
THDET
0
0
0
0
0
0
0
0
0
0
0
0
F1A7
0
F1B7
0
BPCNT
BPON7
BPOFF7
0
BPOUT
0
0
0
0
0
0
0
F2A7
0
F2B7
0
D6
PMVCM
0
0
AOPS
PLL2
FCKO
WTM2
ALC2
IREF6
IVOL6
OVOL6
LMTH1
0
VOL6
DATT0
0
LOVL
0
0
0
0
0
0
0
0
0
0
0
F1A6
0
F1B6
0
0
BPON6
BPOFF6
BPTM6
0
0
0
0
0
0
0
0
F2A6
0
F2B6
0
D5
0
0
DACS
MGAIN1
PLL1
FS3
ZTM1
ALC1
IREF5
IVOL5
OVOL5
OREF5
0
VOL5
SMUTE
0
0
LPF
0
0
0
0
0
0
0
0
0
0
F1A5
F1A13
F1B5
F1B13
0
BPON5
BPOFF5
BPTM5
0
0
0
0
0
0
0
0
F2A5
F2A13
F2B5
F2B13
Rev. 0.5
D4
PMSPK
0
DACA
0
PLL0
MSBS
ZTM0
ZELMN
IREF4
IVOL4
OVOL4
OREF4
0
VOL4
MDIF
0
0
HPF
0
0
0
0
0
0
0
0
0
0
F1A4
F1A12
F1B4
F1B12
0
BPON4
BPOFF4
BPTM4
0
0
0
0
0
0
0
0
F2A4
F2A12
F2B4
F2B12
D3
PMAO
M/S
MGAIN3
SPKG
BCKO1
BCKP
WTM1
LMAT1
IREF3
IVOL3
OVOL3
OREF3
0
VOL3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
F1A3
F1A11
F1B3
F1B11
0
BPON3
BPOFF3
BPTM3
0
0
0
0
0
0
0
0
F2A3
F2A11
F2B3
F2B11
D2
PMDAC
0
PMMP
0
BCKO0
FS2
WTM0
LMAT0
IREF2
IVOL2
OVOL2
OREF2
0
VOL2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F1A2
F1A10
F1B2
F1B10
0
BPON2
BPOFF2
BPTM2
BPLVL2
0
0
0
0
0
0
0
F2A2
F2A10
F2B2
F2B10
D1
0
MCKO
D0
PMADC
PMPLL
MGAIN2
MGAIN0
PFDAC
DIF1
FS1
RFST1
RGAIN0
IREF1
IVOL1
OVOL1
OREF1
1
VOL1
1
0
LIN
0
0
0
0
0
0
0
0
0
0
0
F1A1
F1A9
F1B1
F1B9
BPFR1
BPON1
BPOFF1
BPTM1
BPLVL1
0
0
0
0
0
0
0
F2A1
F2A9
F2B1
F2B9
ADCPF
DIF0
FS0
RFST0
LMTH0
IREF0
IVOL0
OVOL0
OREF0
0
VOL0
READ
0
0
HPFAD
0
0
0
0
0
0
0
0
0
0
F1A0
F1A8
F1B0
F1B8
BPFR0
BPON0
BPOFF0
BPTM0
BPLVL0
0
0
0
0
0
0
0
F2A0
F2A8
F2B0
F2B8
2007/10
- 60 -
[AK4634]
Addr
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
Digital Filter Select 2
Reserved
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
D7
0
0
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
D6
0
0
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
D5
0
0
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
D4
EQ5
0
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
D3
EQ4
0
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
D2
EQ3
0
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
D1
EQ2
0
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
D0
EQ1
0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
The PDN pin = “L” resets the registers to their default values.
Note 39. “0” bits must contain “0” and the “1” bits must contain “1” value.
Note 40. Reading of address 12H ~ 1FH, 25H ~ 2FH and 31H ~ 4FH are not possible.
Note 41. 0FH and 0DH are for address read only. However, 0DH address cannot be read at I2C –bus control mode.
Writing access to 0DH and 0FH does not effect the operation.
Rev. 0.5
2007/10
- 61 -
[AK4634]
■ Register Definitions
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
PMPFIL
R/W
0
D6
PMVCM
R/W
0
D5
0
R
0
D4
PMSPK
R/W
0
D3
PMAO
R/W
0
D2
PMDAC
R/W
0
D1
0
R
0
D0
PMADC
R/W
0
PMADC: ADC Block Power Control
0: Power down (default)
1: Power up
When the PMADC bit changes from “0” to “1”, the initialization cycle (1059/fs=133ms@8kHz) starts. After
initializing, digital data of the ADC is output.
PMDAC: DAC Block Power Control
0: Power down (default)
1: Power up
PMAO: Mono Line Out Power Control
0: Power down (default)
1: Power up
PMSPK: Speaker Block Power Control
0: Power down (default)
1: Power up
PMVCM: VCOM Block Power Control
0: Power down (default)
1: Power up
PMPFIL: Programmable Filter Block (HPF/ LPF/ 5-Band EQ/ ALC) Power Control
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” to each bit. When the PDN pin is “L”, all blocks are
powered-down.
When PMPLL and MCKO bits and all bits in 00H address are “0”, all blocks are powered-down.
When any of the blocks are powered-up, the PMVCM bit must be set to “1”. When PMPLL and MCKO bits and all
bits in 00H address are “0”, PMVCM bit can be “0”.
When any block of ADC, DAC, SPK, or Programmable digital filter is powered-up (PMADC bit = “1”or PMDAC bit
= “1” or PMSPK bit = “1” PMPFIL bit = “1”), the clocks must always be present.
Rev. 0.5
2007/10
- 62 -
[AK4634]
Addr
01H
Register Name
Power Management 2
R/W
Default
D7
0
R/W
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
M/S
R/W
0
D2
0
R
0
D1
MCKO
R/W
0
D0
PMPLL
R/W
0
D4
DACA
R/W
0
D3
MGAIN3
R/W
0
D2
PMMP
R/W
0
D1
MGAIN2
R/W
0
D0
MGAIN0
R/W
1
PMPLL: PLL Block Power Control Select
0: PLL is Power down and External is selected. (default)
1: PLL is Power up and PLL Mode is selected.
MCKO: Master Clock Output Enable
0: “L” Output (default)
1: 256fs Output
M/S: Select Master/ Slave Mode
0: Slave Mode (default)
1: Master Mode
Addr
02H
Register Name
Signal Select 1
R/W
Default
D7
SPOUTE
R/W
0
D6
0
R
0
D5
DACS
R/W
0
MGAIN3-2: MIC-amp Gain control (Table 20)
MGAIN1 bit is located at D5 bit of 03H. Default: “0001” (+20.0dB)
PMMP: MPI pin Power Control
0: Power down (default)
1: Power up
When PMADC bit is “1”, PMMP bit is enabled.
DACA: Switch Control from DAC to mono line amp
0: OFF (default)
1: ON
When PMAO bit is “1”, DACA bit is enabled. When PMAO bit is “0”, the AOUT pin goes VSS1.
DACS: Switch Control from DAC to Speaker-Amp
0: OFF (default)
1: ON
When DACS bit is “1”, DAC output signal is input to Speaker-Amp.
SPOUTE: Speaker output signal Enable
0: Disable (default)
1: Enable
When SPOUTE bit is “0”, the SPP and SPN pins output VSS3.
When SPOUTE bit is “1”, the SPP and SPN pins output signal.
Rev. 0.5
2007/10
- 63 -
[AK4634]
Addr
03H
Register Name
Signal Select 2
R/W
Default
D7
PFSDO
R/W
1
D6
AOPS
R/W
0
D5
MGAIN1
R/W
0
D4
0
R
0
D3
SPKG
R/W
0
D2
0
R
0
D1
PFDAC
R/W
0
D0
ADCPF
R/W
1
ADCPF: Select of Input signal to Programmable Filter/ALC.
0: SDTI
1: Output of ADC (default)
PFDAC: Select of Input signal to DAC.
0: SDTI (default)
1: Output of Programmable Filter/ALC
SPKG: Select Speaker-Amp Output Gain
0: 0dB (default)
1: +2dB
MGAIN1: Mic-Amplifier Gain Control (Table 20)
MGAIN3-2 and MGAIN0 bits are D3, D2 and D0 of 02H. Default: “0001” (+20.0dB)
AOPS: Mono Line Output Power-Save Mode
0: Normal Operation (default)
1: Power-Save Mode
Power-save mode is enable at AOPS bit = “1”. POP noise at power-up/down can be reduced by changing at
PMAO bit = “1”. (Figure 42)
PFSDO: Select of signal from SDTO
0: Output of ADC (1st - HPF)
1: Output of Programmable Filter/ALC (default)
Addr
04H
Register Name
Mode Control 1
R/W
Default
D7
PLL3
R/W
0
D6
PLL2
R/W
0
D5
PLL1
R/W
0
D4
PLL0
R/W
0
D3
BCKO1
R/W
0
D2
BCKO0
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
DIF1-0: Audio Interface Format (Table 16)
Default: “10” (MSB First)
BCKO1-0: Select BICK output frequency at Master Mode (Table 9)
Default: “00” (16fs)
PLL3-0: Select input frequency at PLL mode (Table 4)
Default: “0000” (FCK pin)
Rev. 0.5
2007/10
- 64 -
[AK4634]
Addr
05H
Register Name
Mode Control 2
R/W
Default
D7
ADRST
R/W
0
D6
FCKO
R/W
0
D5
FS3
R/W
0
D4
MSBS
R/W
0
D3
BCKP
R/W
0
D2
FS2
R/W
0
D1
FS1
R/W
0
D0
FS0
R/W
0
FS3-0: Setting of Sampling Frequency (Table 5 and Table 6) and MCKI Frequency (Table 11)
These bits are selected to sampling frequency at PLL mode and MCKI frequency at EXT mode.
Default: “0000”
BCKP, MSBS: “00” (default) (Table 17)
FCKO: Select FCK output frequency at Master Mode (Table 10)
Default: “0”
ADRST: Initialization cycle setting of ADC
0: 1059/fs (default)
1: 291/fs
Addr
06H
Register Name
Timer Select
R/W
Default
D7
0
R
0
D6
WTM2
R/W
0
D5
ZTM1
R/W
0
D4
ZTM0
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
D1
RFST1
R/W
0
D0
RFST0
R/W
0
WTM2-0: ALC1 Recovery Waiting Period (Table 28)
A period of recovery operation when any limiter operation does not occur during the ALC1 operation.
Default is “000”.
ZTM1-0: ALC1, ALC2, IVOL and OVOL Zero crossing timeout Period (Table 27)
The gain is changed by the manual volume controlling (ALC off) or the recovery operation (ALC on) only at
Zero crossing or timeout. The default value is “00”.
RFST1-0 : ALC First recovery Speed (Table 32)
Default: “00” (4times)
Rev. 0.5
2007/10
- 65 -
[AK4634]
Addr
07H
Register Name
ALC Mode Control 1
R/W
Default
D7
LFST
R/W
0
D6
ALC2
R/W
0
D5
ALC1
R/W
0
D4
ZELMN
R/W
0
D3
LMAT1
R/W
0
D2
LMAT0
R/W
0
D1
RGAIN0
R/W
0
D0
LMTH0
R/W
1
D1
IREF1
R/W
0
D0
IREF0
R/W
1
LMTH1-0: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 25)
LMTH1 bit is located at D6 bit of 0BH. Default: “01”
RGAIN1-0: ALC Recovery GAIN Step (Table 29)
RGAIN1 bit is located at D7 bit of 0BH. Default: “00”
LMAT1-0: ALC Limiter ATT Step (Table 26)
Default: “00”
ZELMN: Zero crossing detection enable at ALC Limiter operation
0: Enable (default)
1: Disable
ALC1: ALC of recoding path Enable
0: Disable (default)
1: Enable
ALC2: ALC2 of playback path Enable
0: Disable (default)
1: Enable
LFST: Limiter function of ALC when the output was bigger than Fs.
0: The volume value is changed at zero crossing or timeout. (default)
1: When output of ALC is bigger than FS, VOL value is changed instantly.
Addr
08H
Register Name
ALC Mode Control 2
R/W
Default
D7
IREF7
R/W
1
D6
IREF6
R/W
1
D5
IREF5
R/W
0
D4
IREF4
R/W
0
D3
IREF3
R/W
0
D2
IREF2
R/W
1
IREF7-0: Reference value at ALC Recovery operation for recoding. (0.375dB step, 242 Level) (Table 30)
Default: “C5H” (+19.5dB)
Rev. 0.5
2007/10
- 66 -
[AK4634]
Addr
09H
Register Name
Input Digital Volume Control
R/W
Default
D7
IVOL7
R/W
1
D6
IVOL6
R/W
0
D5
IVOL5
R/W
0
D4
IVOL4
R/W
1
D3
IVOL3
R/W
0
D2
IVOL2
R/W
0
D1
IVOL1
R/W
0
D0
IVOL0
R/W
1
D3
OVOL3
R/W
0
D2
OVOL2
R/W
0
D1
OVOL1
R/W
0
D0
OVOL0
R/W
1
D3
OREF3
R/W
1
D2
OREF2
R/W
0
D1
OREF1
R/W
0
D0
OREF0
R/W
0
IVOL7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 22)
Default: “91H” (0.0dB)
Addr
0AH
Register Name
Digital Volume Control
R/W
Default
D7
OVOL7
R/W
1
D6
OVOL6
R/W
0
D5
OVOL5
R/W
0
D4
OVOL4
R/W
1
OVOL7-0: Output Digital Volume; 0.375dB step, 242 Level (Table 23)
Default: “91H” (0.0dB)
Addr
0BH
Register Name
ALC Mode Control 3
R/W
Default
D7
RGAIN1
R/W
0
D6
LMTH1
R/W
0
D5
OREF5
R/W
1
D4
OREF4
R/W
0
OREF5-0: Reference value at ALC Recovery operation for playback. 1.5dB step, 60 Level (Table 31)
Default: “28H” (+6.0dB)
LMTH1-0: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 25)
Default: “01” (-4.1dBFS > ALC Output ≥ -6.0dBFS)
RGAIN1-0: ALC Recovery GAIN Step (Table 29)
RGAIN1 bit is located at D1 bit of 07H. Default: “00”
Addr
0DH
Register Name
Input Digital Volume Control
R/W
Default
D7
VOL7
R
-
D6
VOL6
R
-
D5
VOL5
R
-
D4
VOL4
R
-
D3
VOL3
R
-
D2
VOL2
R
-
D1
VOL1
R
-
D0
VOL0
R
-
VOL7-0: The current volume of ALC; 0.375dB step, 242 Level, Read only (Table 33)
Rev. 0.5
2007/10
- 67 -
[AK4634]
Addr
0EH
Register Name
Mode Control 3
R/W
Default
D7
DATT1
R/W
0
D6
DATT0
R/W
0
D5
SMUTE
R/W
0
D4
MDIF
R/W
0
D3
1
R
1
D2
0
R
0
D1
1
R
1
D0
READ
R/W
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
0
R
0
D1
LIN
R/W
0
D0
0
R
0
READ: Read function Enable
0: Disable (default)
1: Enable
MDIF: Single-ended / Full-differential Input Select
0: Single-ended input (MIC pin or LIN pin: Default)
1: Full-differential input (MICP and MICN pins)
SMUTE: Soft Mute Control
0: Normal Operation (default)
1: DAC outputs soft-muted
DATT1-0: Output Digital Volume2; 6dB step, 4 Level (Table 24)
Default: “00H” (0.0dB)
Addr
0FH
Register Name
Thermal Shutdown
R/W
Default
D7
THDET
R
0
D6
0
R
0
D5
0
R
0
THDET: Thermal Shutdown Detection
0: Normal Operation (default)
1: Thermal Shutdown
Addr
10H
Register Name
Signal Select 4
R/W
Default
D7
0
R
0
D6
LOVL
R/W
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
LIN: Select Input data of ADC
0: MIC pin (default)
1: LIN pin
LOVL: Lineout Gain Setting
0: 0dB(default)
1: +2dB
Rev. 0.5
2007/10
- 68 -
[AK4634]
Addr
11H
Register Name
Digital Filter Select 1
R/W
Default
D7
0
R
0
D6
0
R
0
D5
LPF
R/W
0
D4
HPF
R/W
1
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
HPFAD
R/W
1
D1
F1A1
F1A9
F1B1
F1B9
W
D0
F1A0
F1A8
F1B0
F1B8
W
D1
BPFR1
R/W
0
D0
BPFR0
R/W
0
HPFAD: HPF Enable in ADC block
0: Disable
When HPFAD bit is “0”, HPFAD block is bypassed (0dB).
1: Enable (default)
When HPFAD bit is “1”, F1A13-0, F1B13-0 bits are enabled.
HPFAD bit should be “1”at PMADC bit = “1”.
HPF: HPF Enable in Filter block.
0: Disable
When HPF bit is “0”, HPF block is bypassed (0dB).
1: Enable (default)
When HPF bit is “1”, F1A13-0, F1B13-0 bits are enabled.
LPF: LPF Coefficient Setting Enable
0: Disable (default)
When LPF bit is “0”, LPF block is bypassed (0dB).
1: Enable
When LPF bit is “1”, F2A13-0, F2B13-0 bits are enabled.
Addr
1CH
1DH
1EH
1FH
Register Name
HPF Co-efficient 0
HPF Co-efficient 1
HPF Co-efficient 2
HPF Co-efficient 3
R/W
Default
D7
F1A7
0
F1B7
0
W
D6
F1A6
0
F1B6
0
W
D5
D4
D3
D2
F1A5
F1A4
F1A3
F1A2
F1A13
F1A12
F1A11
F1A10
F1B5
F1B4
F1B3
F1B2
F1B13
F1B12
F1B11
F1B10
W
W
W
W
F1A13-0 bits = 0x1F16, F1B13-0 bits = 0x1E2B
F1A13-0, F1B13-0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2)
Default: F1A13-0 bits = 0x1F16, F1B13-0 bits = 0x1E2B
fc = 75Hz@fs = 8kHz, 150Hz@fs = 16kHz
Addr
20H
Register Name
BEEP Frequency
R/W
Default
D7
BPCNT
R/W
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
BPFR1-0: BEEP Signal Output Frequency Setting (Table 38 ~ Table 40)
Default: “00”
BPCNT: BEEP Signal Output Mode Setting
0: Once Output Mode (default)
1: Continuous Mode
In continuous mode, the BEEP signal is output while BPCNT bit is “1”.
In output mode, the BEEP signal is output by only the frequency set with BPTM6-0 bits.
Rev. 0.5
2007/10
- 69 -
[AK4634]
Addr
21H
Register Name
BEEP ON Time
R/W
Default
D7
BPON7
R/W
0
D6
BPON6
R/W
0
D5
BPON5
R/W
0
D4
BPON4
R/W
0
D3
BPON3
R/W
0
D2
BPON2
R/W
0
D1
BPON1
R/W
0
D0
BPON0
R/W
0
D4
BPOFF4
R/W
0
D3
BPOFF3
R/W
0
D2
BPOFF2
R/W
0
D1
BPOFF1
R/W
0
D0
BPOFF0
R/W
0
D4
BPTM4
R/W
0
D3
BPTM3
R/W
0
D2
BPTM2
R/W
0
D1
BPTM1
R/W
0
D0
BPTM0
R/W
0
BPON7-0: Setting ON-time of BEEP signal output (Table 41)
Default: “00H”
Addr
22H
Register Name
BEEP OFF Time
R/W
Default
D7
BPOFF7
R/W
0
D6
BPOFF6
R/W
0
D5
BPOFF5
R/W
0
BPOFF7-0: Setting OFF-time of BEEP signal output (Table 42)
Default: “00H”
Addr
23H
Register Name
BEEP Repeat Count
R/W
Default
D7
0
R
0
D6
BPTM6
R/W
0
D5
BPTM5
R/W
0
BPTM6-0: Setting the number of times that BEEP signal repeats (Table 43)
Default: “00H”
Addr
24H
Register Name
BEEP VOL/Control
R/W
Default
D7
BPOUT
R/W
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
BPLVL2
R/W
0
D1
BPLVL1
R/W
0
D0
BPLVL0
R/W
0
BPLVL2-0: Setting Output Level of BEEP signal (Table 44)
Default: “0H” (0dB)
BPOUT: BEEP Signal Control
0: OFF (default)
1: ON
At the time of BPCNT = “0”, when BPOUT bit is “1”, the beep signal starts outputting. The Beep signal stops
after the number of times that was set in BPTM6-0 bit, and BPOUT bit is set to “0” automatically.
Rev. 0.5
2007/10
- 70 -
[AK4634]
Addr
2CH
2DH
2EH
2FH
Register Name
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
R/W
Default
D7
F2A7
0
F2B7
0
W
0
D6
F2A6
0
F2B6
0
W
0
D5
F2A5
F2A13
F2B5
F2B13
W
0
D4
F2A4
F2A12
F2B4
F2B12
W
0
D3
F2A3
F2A11
F2B3
F2B11
W
0
D2
F2A2
F2A10
F2B2
F2B10
W
0
D1
F2A1
F2A9
F2B1
F2B9
W
0
D0
F2A0
F2A8
F2B0
F2B8
W
0
D5
0
R
0
D4
EQ5
R/W
0
D3
EQ4
R/W
0
D2
EQ3
R/W
0
D1
EQ2
R/W
0
D0
EQ1
R/W
0
F2A13-0, F2B13-0: LPF Coefficient (14bit x 2)
Default: “0000H”
Addr
30H
Register Name
Digital Filter Select 2
R/W
Default
D7
0
R
0
D6
0
R
0
EQ1: Equalizer 1 Coefficient Setting Enable
0: Disable (default)
When EQ1 bit is “0”, EQ block is through (0dB).
1: Enable
When EQ1 bit is “1”, E1A15-0, E1B15-0, E1C15-0 bits are enabled.
EQ2: Equalizer 2 Coefficient Setting Enable
0: Disable (default)
When EQ2 bit is “0”, EQ block is through (0dB).
1: Enable
When EQ2 bit is “1”, E2A15-0, E2B15-0, E2C15-0 bits are enabled.
EQ3: Equalizer 3 Coefficient Setting Enable
0: Disable (default)
When EQ3bit is “0”, EQ block is through (0dB).
1: Enable
When EQ3 bit is “1”, E3A15-0, E3B15-0, E3C15-0 bits are enabled.
EQ4: Equalizer 4 Coefficient Setting Enable
0: Disable (default)
When EQ4 bit is “0”, EQ block is through (0dB).
1: Enable
When EQ4 bit is “1”, E4A15-0, E4B15-0, E4C15-0 bits are enabled.
EQ5: Equalizer 5 Coefficient Setting Enable
0: Disable (default)
When EQ5 bit is “0”, EQ block is through (0dB).
1: Enable
When EQ5 bit is “1”, E5A15-0, E5B15-0, E5C15-0 bits are enabled.
Rev. 0.5
2007/10
- 71 -
[AK4634]
Addr
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
R/W
Default
D7
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
W
0
D6
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
W
0
D5
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
W
0
D4
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
W
0
D3
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
W
0
D2
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
W
0
D1
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
W
0
D0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
W
0
E1A15-0, E1B15-0, E1C15-0: Equalizer 1 Coefficient (16bit x3)
Default: “0000H”
E2A15-0, E2B15-0, E2C15-0: Equalizer 2 Coefficient (16bit x3)
Default: “0000H”
E3A15-0, E3B15-0, E3C15-0: Equalizer 3 Coefficient (16bit x3)
Default: “0000H”
E4A15-0, E4B15-0, E4C15-0: Equalizer 4 Coefficient (16bit x3)
Default: “0000H”
E5A15-0, E5B15-0, E5C15-0: Equalizer 5 Coefficient (16bit x3)
Default: “0000H”
Rev. 0.5
2007/10
- 72 -
[AK4634]
SYSTEM DESIGN
Figure 57 and Figure 58 show the system connection diagram. The evaluation board [AKD4634] demonstrates the
optimum layout, power supply arrangements and measurement results.
< MIC Single-end Input >
Dynamic SPK
R1, R2: Short
ZD1, ZD2: Open
Piezo SPK
R1, R2: ≥10Ω
ZD1, ZD2: Required
0.1µ
10
Speaker
R1
0.1µ
R2
I2C
DVDD
VSS2
VSS3
NC
SDTO
MCKO
SPN
SVDD
SPP
BICK
SDTI
MCKI
AOUT
LIN
MPI
MIC
1µ
ZD2
ZD1
220
1µ
DSP
&
20 k
2.2k
Top View
µP
FCK
CCLK
CDTI
1µ
0.1µ
PDN
TST1
CSN
TST2
VCOM
VCOC
VSS1
AVDD
TST3
Rp
+
2.2µ
Cp
0.1µ
Analog Supply
2.2∼3.6V
10µ
+
Figure 57. Typical Connection Diagram
Notes:
- VSS1, VSS2 and VSS3 of the AK4634 should be distributed separately from the ground of external controllers.
- All digital input pins except pull-down pin should not be left floating.
- In EXT mode (PMPLL bit = “0”), Rp and Cp of the VCOC pin can be open.
- In PLL mode (PMPLL bit = “1”), Rp and Cp of the VCOC pin should be connected as shown in Table 45.
- When the AK4634 is used at master mode, FCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, a pull-up resistor with around 100Ω should be connected to LRCK and BICK pins of the AK4634.
-When AVDD, DVDD and SVDD were distributed, DVDD = 1.6 ~ 3.6 V, SVDD = 2.2 ~ 4.0 V.
Rev. 0.5
2007/10
- 73 -
[AK4634]
< MIC differential Input >
Dynamic SPK
R1, R2: Short
ZD1, ZD2: Open
Piezo SPK
R1, R2: ≥10Ω
ZD1, ZD2: Required
0.1µ
10
Speaker
R1
0.1µ
R2
I2C
DVDD
VSS2
VSS3
NC
SDTO
MCKO
SPN
SVDD
SPP
1µ
ZD2
ZD1
220
1µ
DSP
BICK
&
SDTI
MCKI
AOUT
MICN
1k
1k
Top View
µP
FCK
CCLK
CDTI
MPI
MICP
1µ
0.1µ
PDN
CSN
TST1
TST2
VCOM
VCOC
VSS1
AVDD
TST3
20 k
Rp
+
2.2µ
Cp
0.1µ
Analog Supply
2.2∼3.6V
10µ
+
Figure 58. Typical Connection Diagram
Notes:
- VSS1, VSS2 and VSS3 of the AK4634 should be distributed separately from the ground of external controllers.
- All digital input pins except pull-down pin should not be left floating.
- In EXT mode (PMPLL bit = “0”), Rp and Cp of the VCOC pin can be open.
- In PLL mode (PMPLL bit = “1”), Rp and Cp of the VCOC pin should be connected as shown in Table 45.
- When the AK4634 is used at master mode, FCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, a pull-up resistor with around 100Ω should be connected to LRCK and BICK pins of the AK4634.
-When AVDD, DVDD and SVDD were distributed, DVDD = 1.6 ~ 3.6 V, SVDD = 2.2 ~ 4.0 V.
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
0
1
2
3
6
7
12
13
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
Others
PLL Reference
Clock Input Pin
Input Frequency
Rp and Cp of
VCOC pin
Rp[Ω] Cp[F]
6.8k
220n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
PLL Lock
Time (max)
FCK pin
1fs
160ms
BICK pin
16fs
2ms
BICK pin
32fs
2ms
BICK pin
64fs
2ms
MCKI pin
12MHz
30ms
MCKI pin
24MHz
30ms
MCKI pin
13.5MHz
30ms
MCKI pin
27MHz
30ms
Others
N/A
Table 45. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
Rev. 0.5
(default)
2007/10
- 74 -
[AK4634]
1. Grounding and Power Supply Decoupling
The AK4634 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and SVDD are
usually supplied from the system’s analog supply. If AVDD, DVDD and SVDD are supplied separately, the correct
power up sequence should be observeVSS21, VSS2 and VSS3 of the AK4634 should be connected to the analog ground
plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto
the printed circuit board. Decoupling capacitors should be as near to the AK4634 as possible, with the small value
ceramic capacitor being the nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached
to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All
signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the
AK4634.
3. Analog Inputs
The Mic and Line inputs supports single-ended and differential. The input signal range scales with nominally at 0.06 x
AVDD Vpp for the Mic input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage
(approx. 0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC).
The AK4634 can accept input voltages from VSS1 to AVDD.
4. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and
a negative full scale for 8000H(@16bit). Mono Line Output from the AOUT pin is centered at 0.45 x AVDD (typ).
Rev. 0.5
2007/10
- 75 -
[AK4634]
PACKAGE
Top View
Bottom View
2.5 ± 0.1
A
29pin WL-CSP : 2.5mm x 3.0mm
6
6
5
5
B
4634
4
3.0 ± 0.1
4
XXXX
3
3
2
2
1
1
A
B
C
D
0.5
E
E
D
C
B
φ 0.3 ± 0.05
A
φ 0.05
M S AB
0.25
0.85
S
0.08 S
Rev. 0.5
2007/10
- 76 -
[AK4634]
MARKING
4634
XXXX
1
A
XXXX: Date code (4 digits)
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
Rev. 0.5
2007/10
- 77 -