SN74LVC1G17 SCES351S – JULY 2001 – REVISED JUNE 2011 www.ti.com SINGLE SCHMITT-TRIGGER BUFFER Check for Samples: SN74LVC1G17 FEATURES 1 • 2 • • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.6 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection 1 A 2 GND 3 5 4 • DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) DBV PACKAGE (TOP VIEW) N.C. Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) VCC N.C. 1 A 2 GND 3 VCC 5 N.C. – No internal connection See mechanical drawings for dimensions. YZP PACKAGE (TOP VIEW) A2 A B1 B2 GND C1 C2 1 6 VCC A 2 5 N.C. GND 3 4 Y Y DNU – Do not use YZV PACKAGE (TOP VIEW) A2 VCC GND B1 B2 Y GND 3 4 Y Table 2. YZV PACKAGE TERMINAL DSF PACKAGE (TOP VIEW) N.C. A GND 1 6 2 5 3 4 VCC N.C. Y 1 2 DNU VCC B A No ball C GND Y A A1 2 VCC Table 1. YZP PACKAGE TERMINAL ASSIGNMENTS VCC A A 5 Y N.C. A1 1 Y 4 DRY PACKAGE (TOP VIEW) DNU N.C. Table 2. YZV PACKAGE TERMINAL ASSIGNMENTS (continued) ASSIGNMENTS 1 2 A A VCC B GND Y 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2011, Texas Instruments Incorporated SN74LVC1G17 SCES351S – JULY 2001 – REVISED JUNE 2011 www.ti.com DESCRIPTION/ORDERING INFORMATION This single Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G17 contains one buffer and performs the Boolean function Y = A. The device functions as an independent buffer, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) TA (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (3) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) Reel of 3000 SN74LVC1G17YZPR _ _ _C7_ NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZV (Pb-free) Reel of 3000 SN74LVC1G17YZVR ____ C7 QFN – DRY Reel of 5000 µQFN – DSF Reel of 5000 SN74LVC1G17DRYR SN74LVC1G17DRYRG4 SN74LVC1G17DSFR C7 C7 SN74LVC1G17DBV3 Reel of 3000 SOT (SOT-23) – DBV SN74LVC1G17DBVR SN74LVC1G17DBVRE4 SN74LVC1G17DBVRG4 –40°C to 85°C Tube of 250 C17 SN74LVC1G17DBVT SN74LVC1G17DBVTE4 SN74LVC1G17DCK3 Reel of 3000 SOT (SC-70) – DCK (1) (2) (3) 2 SN74LVC1G17DCKRE4 SN74LVC1G17DCKRG4 Tube of 250 SOT (SOT-553) – DRL SN74LVC1G17DCKR Reel of 4000 C7_ SN74LVC1G17DCKT SN74LVC1G17DCKTE4 SN74LVC1G17DRLR SN74LVC1G17DRLRG4 C7_ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). YZV: The actual top-side marking is two lines. Line 1 has four characters to denote year, month, day, and wafer fab/assembly site. Line 2 has two characters which show the family and function code. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Copyright © 2001–2011, Texas Instruments Incorporated SN74LVC1G17 SCES351S – JULY 2001 – REVISED JUNE 2011 www.ti.com Table 3. FUNCTION TABLE INPUT A OUTPUT Y H H L L LOGIC DIAGRAM (POSITIVE LOGIC) (DBV, DCK, DRL, DSF, DRY, and YZP Package) LOGIC DIAGRAM (POSITIVE LOGIC) (YZV Package) Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA (3) Continuous current through VCC or GND θJA Package thermal impedance (4) DBV package 206 DCK package 252 DRL package 142 DRY package 234 DSF package 300 YZP package 132 YZV package Tstg (1) (2) (3) (4) Storage temperature range °C/W 116 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Copyright © 2001–2011, Texas Instruments Incorporated 3 SN74LVC1G17 SCES351S – JULY 2001 – REVISED JUNE 2011 www.ti.com Recommended Operating Conditions (1) VCC Supply voltage VI Input voltage VO Output voltage IOH High-level output current Operating Data retention only MIN MAX 1.65 5.5 1.5 5.5 V 0 VCC V VCC = 1.65 V –4 VCC = 2.3 V –8 –16 VCC = 3 V –32 4 VCC = 2.3 V 8 16 VCC = 3 V (1) 4 Operating free-air temperature mA 24 VCC = 4.5 V TA mA –24 VCC = 1.65 V Low-level output current V 0 VCC = 4.5 V IOL UNIT 32 –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright © 2001–2011, Texas Instruments Incorporated SN74LVC1G17 SCES351S – JULY 2001 – REVISED JUNE 2011 www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ (Positive-going input threshold voltage) VT– (Negative-going input threshold voltage) ΔVT Hysteresis (VT+ – VT–) IOH = –100 μA VOH 1.13 1.08 1.56 3V 1.48 1.92 4.5 V 2.19 2.74 5.5 V 2.65 3.33 1.65 V 0.35 0.59 2.3 V 0.56 0.88 3V 0.89 1.2 4.5 V 1.51 1.97 5.5 V 1.88 2.4 1.65 V 0.36 0.64 2.3 V 0.45 0.78 3V 0.51 0.83 4.5 V 0.58 0.93 5.5 V 0.69 1.04 1.9 4.5 V IOL = 100 μA 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 VI = 5.5 V or GND, VI = 3.6 V or GND, One input at VCC – 0.6 V, Other inputs at VC C or GND CI VI = VCC or GND V 3.8 0.4 3V V 0.55 4.5 V IO = 0 V 2.3 IOH = –32 mA VI or VO = 5.5 V V V 2.4 3V VI = 5.5 V or GND UNIT VCC – 0.1 1.2 ΔICC (1) 0.76 2.3 V 2.3 V IOL = 32 mA ICC 1.65 V 1.65 V IOL = 24 mA Ioff MAX IOH = –8 mA IOL = 16 mA A input MIN MIN TYP (1) MAX IOH = –4 mA IOH = –24 mA II 25 °C 1.65 V to 5.5 V IOH = –16 mA VOL VCC 0.55 0 to 5.5 V ±5 μA 0 ±10 μA 1.65 V to 5.5 V 3 V to 3.6 V 10 0.5 3 V to 5.5 V 3.3 V 1.5 500 4.5 μA μA pF All typical values are at VCC = 3.3 V, TA = 25°C. Copyright © 2001–2011, Texas Instruments Incorporated 5 SN74LVC1G17 SCES351S – JULY 2001 – REVISED JUNE 2011 www.ti.com Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1 ) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2.8 9.9 1.6 5.5 1.5 4.6 0.9 4.4 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2 ) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 3.8 11 2 6.5 1.8 5.5 1.2 5 ns Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 20 21 22 26 UNIT pF Copyright © 2001–2011, Texas Instruments Incorporated SN74LVC1G17 SCES351S – JULY 2001 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MW 1 MW 1 MW 1 MW 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Copyright © 2001–2011, Texas Instruments Incorporated 7 SN74LVC1G17 SCES351S – JULY 2001 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 8 Copyright © 2001–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 12-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp SN74LVC1G17DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DCKJ PREVIEW SC70 DCK 5 10000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17DRYRG4 ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 12-Mar-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74LVC1G17DSFR ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G17YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74LVC1G17YZVR ACTIVE DSBGA YZV 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC1G17 : • Automotive: SN74LVC1G17-Q1 • Enhanced Product: SN74LVC1G17-EP Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 12-Mar-2012 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G17DBVR SOT-23 DBV 5 3000 178.0 9.2 SN74LVC1G17DBVR SOT-23 DBV 5 3000 180.0 SN74LVC1G17DBVR SOT-23 DBV 5 3000 178.0 SN74LVC1G17DBVT SOT-23 DBV 5 250 SN74LVC1G17DBVT SOT-23 DBV 5 W Pin1 (mm) Quadrant 3.3 3.2 1.55 4.0 8.0 Q3 9.2 3.17 3.23 1.37 4.0 8.0 Q3 9.0 3.23 3.17 1.37 4.0 8.0 Q3 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 250 178.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3 SN74LVC1G17DBVT SOT-23 DBV 5 250 180.0 9.2 3.17 3.23 1.37 4.0 8.0 Q3 SN74LVC1G17DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G17DCKR SC70 DCK 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 SN74LVC1G17DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1G17DCKT SC70 DCK 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 SN74LVC1G17DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G17DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1G17DRLR SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SN74LVC1G17DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 SN74LVC1G17DRYR SON DRY 6 5000 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1 SN74LVC1G17DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 SN74LVC1G17YZPR DSBGA YZP 5 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1 SN74LVC1G17YZVR DSBGA YZV 4 3000 180.0 8.4 1.02 1.02 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G17DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G17DBVR SOT-23 DBV 5 3000 205.0 200.0 33.0 SN74LVC1G17DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G17DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G17DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G17DBVT SOT-23 DBV 5 250 205.0 200.0 33.0 SN74LVC1G17DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G17DCKR SC70 DCK 5 3000 205.0 200.0 33.0 SN74LVC1G17DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G17DCKT SC70 DCK 5 250 205.0 200.0 33.0 SN74LVC1G17DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G17DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G17DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74LVC1G17DRYR SON DRY 6 5000 180.0 180.0 30.0 SN74LVC1G17DRYR SON DRY 6 5000 203.0 203.0 35.0 SN74LVC1G17DSFR SON DSF 6 5000 180.0 180.0 30.0 SN74LVC1G17YZPR DSBGA YZP 5 3000 220.0 220.0 34.0 SN74LVC1G17YZVR DSBGA YZV 4 3000 220.0 220.0 34.0 Pack Materials-Page 2 X: Max = 0.93 mm, Min = 0.87 mm Y: Max = 0.93 mm, Min = 0.87 mm X: Max = 0.93 mm, Min = 0.87 mm Y: Max = 0.93 mm, Min = 0.87 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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