DRAM SMJ44400 Austin Semiconductor, Inc. 1M x 4 DRAM PIN ASSIGNMENT (Top View) DYNAMIC RANDOM-ACCESS MEMORY 20-Pin DIP (JD) 20-Pin Flatpack (HR) (400 MIL) AVAILABLE AS MILITARY SPECIFICATIONS • SMD 5962-90847 • MIL-STD-883 DQ1 DQ2 W\ RAS\ A9 A0 A1 A2 A3 Vcc FEATURES • Organized 1,048,576 x 4 • Single +5V ±10% power supply • Enhanced Page-Mode operation for faster memory access P Higher data bandwidth than conventional page-mode parts P Random Single-Bit Access within a row with a column address • CAS\-Before-RAS\ (CBR) Refresh • Long Refresh period: 1024-cycle Refresh in 16ms (Max) • 3-State unlatched Output • Low Power Dissipation • All Inputs/Outputs and Clocks are TTL Compatible • Processing to MIL-STD-883, Class B available OPTIONS Pin Name A0 - A9 CAS\ DQ1 - DQ4 OE\ RAS\ W\ Vcc Vss MARKING • Timing 80ns access 100ns access 120ns access • Package(s) Ceramic DIP (400mils) Ceramic Flatpack 20 19 18 17 16 15 14 13 12 11 Vss DQ4 DQ3 CAS\ OE\ A8 A7 A6 A5 A4 Function Address Inputs Column-Address Strobe Data Inputs/Outputs Output Enable Row-Address Strobe Write Enable 5V Supply Ground The SMJ44400 is offered in a 400-mil, 20-pin ceramic side-brazed dual-in-line package (JD suffix) and a 20-pin ceramic flatpack (HR suffix) that are characterized for operation from -55°C to +125°C. -80 -10 -12 OPERATION JD HR No. 113 No. 308 Enhanced Page Mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS\ low time and the CAS\ page cycle time used. With minimum CAS\ page cycle time, all 1024 columns specified by column addresses A0 through A9 can be accessed without intervening RAS\ cycles. Unlike conventional page-mode DRAMs, the columnaddress buffers in this device are activated on the • Operating Temperature Ranges M Military (-55oC to +125oC) GENERAL DESCRIPTION The SMJ44400 is a series of 4,194,304-bit dynamic random-access memories (DRAMs), organized as 1,048,576 words of four bits each. This series employs state-of-the-art technology for high performance, reliability, and low-power operation. The SMJ44400 features maximum row access times of 80ns, 100ns, and 120ns. Maximum power dissipation is as low as 360mW operating and 22mW standby. All inputs and outputs, including clocks, are compatible with Series 54 TTL. All addressses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. SMJ44400 Rev. 2.0 10/01 1 2 3 4 5 6 7 8 9 10 For more products and information please visit our web site at www.austinsemiconductor.com Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 DRAM Austin Semiconductor, Inc. SMJ44400 (continued) Enhanced Paga Mode (continued) falling edge of RAS\. The buffers act as transparent or flowthrough latches while CAS\ is high. The falling edge of CAS\ latches the column addresses. This feature allows the SMJ44400 to operate at a higher data bandwidth then conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when CAS\ goes low. This performance improvement is referred to as enhanced page mode. Valid column address can be presented immediately after row address hold time has been satisfied, usually well in advance of the maximum (access time from column address) has been satisfied. In the event that column addresses for the next cycle are valid at the time CAS\ goes high, access time for the next cycle is determined by the later occurrence of tCAC or tCPA (access time form rising edge of CAS\). Output Enable (OE\) OE\ controls the impedance of the output buffers. When OE\ is high, the buffers remain in the high-impedance state. Bringing OE\ low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is necessary for both RAS\ and CAS\ to be brought low for the output buffers to go into the low-impedance state. Once in the low-ompedance state, they remain in the low-impedance state until either OE\ or CAS\ is brought high. Refresh A refresh operation must be performed at least once every 16ms to retain data. This can be achieved by strobing each of the 1024 rows (A0-A9). A normal read or write cycle refreshes all bits in each row that is selected. A RAS\-only operation can be used by holding CAS\ at the high (inactive) level, conserving power as the output buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS\-only refresh. Hidden refresh can be performed while maintaining valid data at teh output pin. This is accomplished by holding CAS\ at VIL after a read operation and cycling RAS\ after a specified precharge period, similar to a RAS\-only refresh cycle. The external address is ignored during the hidden refresh cycles. Address (A0-A9) Twenty address bits are required to decode 1 of 1,048,576 storage cell locations. Ten row-address bits are set up on inputs A0 through A9 and latched onto the chip by RAS\. The ten column-address bits are set up on pins A0 through A9 and latched onto the chip by CAS\. All addresses must be stable on or before the falling edges of RAS\ and CAS\. RAS\ is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS\ is used as a chip select, activating the output buffer as well as latching the address bits into the column-address buffer. CAS\-before-RAS\ (CBR) and hidden refresh CBR refresh is utilized by bringing CAS\ low earlier than RAS\ (see parameter tCSR) and holding it low after RAS\ falls (see parameter tCSR). For successive CBR refresh cycles, CAS\ can remain low while cycling RAS\. The external address is ignored and the refresh address is generated internally. During CBR refresh cycles the outputs remain in the high-impedance state. Hidden refresh can be performed while maintaining valid data at the output pins. Thsi is accomplished by holding CAS\ at VIL after a read operation. RAS\ is cycled after the specified read cycle parameters are met. Hidden refresh can also be used in conjuction with an early-write cycle. CAS\ is maintained at VIL while RAS\ is cycled, once all the specified early-write parameters are met. Externally generated addresses must be used to specify the location to be accessed during the initial RAS\ cycle of a hidden refresh operation. Subsequent RAS\ cycles (refresh cycles) use the internallygenerated addresses and the external address is ignored. Write Enable (W\) The read or write mode is selected through W\. A logic high on the W\ input selects the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W\ goes low prior to CAS\ (early write), data out reamins in the high-impedance state for the entire cycle permitting a write operation independent of the state of OE\. This permits early-write operation to be completed with OE\ grounded. Data In/Out (DQ1 - DQ4) The high-impedance output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS\ and OE\ are brought low. In a read cycle the output becomes valid after all access times are satisfied. The output remains valid while CAS\ and OE\ are low. CAS\ or OE\ going high returns it to the high-impedance state. SMJ44400 Rev. 2.0 10/01 Power Up To achieve proper device operation, an initial pause of 200µs followed by a minimum of eight initialization cycles is Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 DRAM SMJ44400 Austin Semiconductor, Inc. cycle is used to enter test mode. In the test mode, data is written into and read from eight sections of the array in parallel. All data is written into the array through DQ1. Data is comparted upon reading and if all bits are equal, all DQ pins go high. If any one bit is different, all the DQ pins go low. Any combination read, write, read-write, or page-mode can be used in the test mode. The test mode function reduces test times by enabling the 1M x 4-bit DRAM to be tested as if it were a 512K DRAM where column address 0 is not used. A RAS\-only or CBR refresh cycle is used to exit the DFT mode. (continued) Power Up (continued) required after full Vcc level is achieved. These eight initialization cycles need to include at least one refresh (RAS\-only or CBR) cycle. Test Mode An industry standard Design For Test (DFT) mode is incorporated in the SMJ44400. A CBR with W\ low (WCBR) LOGIC SYMBOL1 RAM 1024K x 4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS\ 6 7 8 9 11 12 13 14 15 5 4 20D10/21D0 A 0 1 048 575 20D19/21D9 C20[Row] G23/[Refresh Row] 24[Power Down] C21[Column] G24 CAS\ 17 3 W\ 16 OE\ DQ1 1 2 DQ2 18 DQ3 19 DQ4 & 23C22 23,21D G25 24,25EN A, Z26 A, 22D 26 1. This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12. The pinouts illustrated are for the JD package. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 DRAM SMJ44400 Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM RAS\ CAS\ W\ OE\ Timeing and Control A0 A1 8 Column Address Buffers 2 A9 Column Decode Sense Amplifiers 128K Array 128K Array R 128K Array 128K Array O W 16 16 D E C O D E R 16 Row Address Buffers 10 128K Array 16 I/O Buffers 4 of 16 Selection 4 Data In Reg. 4 Data Out Reg. 2 128K Array 10 ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. Voltage on Vcc Supply Relative to Vss...............-1V to +7.0V Voltage Range on Any Pin Relative to Vss.........-1V to +7.0V Short Circuit Output Current (per I/O)….......................50mA Power Dissipation.................................................................1W Storage Temperature Range..........................-65°C to +150°C Operating Temperature Range......................-55°C to +125°C RECOMMENDED OPERATING CONDITIONS SYM DESCRIPTION MIN NOM MAX UNIT 4.5 5 5.5 V 2.4 6.5 V VIL Low-Level Input Voltage -1 0.8 V TA Minimum Operating Temperature -55 TC Maximum Operating Case Temperature VCC Supply Voltage VIH High-Level Input Voltage 1 °C 125 °C 1. The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 DRAM SMJ44400 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC<TA<125oC or -40oC to +85oC; Vcc = 5V +10%) -8 -10 -12 SYM VOH PARAMETER High-level output voltage VOL Low-level output voltage TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT 2.4 2.4 2.4 V IOH = -5mA IOL = 4.2mA VCC = 5.5V, VI = 0V to 6.5V, All 0.4 0.4 0.4 V ±10 ±10 ±10 µA II Input current (leakage) IO Output current (leakage) VCC = 5.5V, VO = 0V to VCC, CAS\ High ±10 ±10 ±10 µA ICC1 Read - or write-cycle current1 VCC = 5.5V, Minimum cycle 85 80 70 mA ICC2 Standby current After 1 memory cycle, RAS\ and CAS\ High, VIH = 2.4V 4 4 4 mA VCC = 5.5V, Minimum cycle, RAS\ cycling, CAS\ High (RAS\ only), RAS\ Low after CAS\ Low (CBR) 85 75 65 mA VCC = 5.5V, tPC = minimum, RAS\ Low, CAS\ cycling 50 40 35 mA ICC3 Average refresh current 1 (RAS\ only, or CBR\) ICC4 Average page current2 other pins = 0V to VCC CAPACITANCE (f = 1MHz)3 SYM MAX UNIT Input capacitance, address inputs 7 pF Ci(RC) Input capacitance, strobe inputs 10 pF Ci(W) Input capacitance, write-enable inputs 10 pF Output capacitance 10 pF Ci(A) CO PARAMETER SWITCHING CHARACTERISTICS (-55oC<TA<125oC or -40oC to +85oC; Vcc = 5V +10%) SYM tAA PARAMETERS Access time from column address -8 MAX 40 -10 MAX 45 -12 MAX 55 UNIT ns tCAC Access time from CAS\ low 20 25 30 ns tCPA Access time from column precharge 45 50 55 ns tRAC Access time from RAS\ low 80 100 120 ns tOEA Access time from OE\ low 20 25 30 ns 20 25 30 ns 20 25 30 ns tOFF tOEZ 4 Output disable time after CAS\ High Output disable tiem after OE\ High 4 NOTES: 1. Measured with a maximum of one address change while RAS\ = VIL. 2. Measured with a maximum of one address change while CAS\ = VIH. 3. VCC = 5V ±0.5V and the bias on the pins under test is 0V. Capacitance is sampled only at initial design and after any major change. 4. tOFF and tOEZ are specified when the output is no longer driven. The outputs are disabled by bringing either OE\ or CAS\ High. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 DRAM SMJ44400 Austin Semiconductor, Inc. TIMING REQUIREMENTS (-55oC<TA<125oC or -40oC to +85oC; Vcc = 5V +10%) SYM tRC tRWC tPC tPRWC PARAMETER MIN 150 1 Cycle time, random read or write Cycle time, read-write Cycle time, page-mode read or write 2 Cycle time, page-mode read-write 3 -8 MAX MIN 180 -10 MAX MIN 210 -12 MAX UNIT ns 205 245 285 ns 50 60 65 ns 100 120 135 ns 80 100000 100 100000 120 100000 ns 80 10000 ns 20 10000 tRASP Pulse duration, page mode, RAS\ low tRAS Pulse duration, nonpage mode, RAS\ low tCAS Pulse duration, CAS\ low tCP Pulse duration, CAS\ High 10 10 15 ns 3 4 100 10000 25 10000 120 10000 30 10000 ns tRP Pulse duration, RAS\ High (precharge) 60 70 80 ns tWP Pulse duration, write 15 20 25 ns tASC Setup time, column address before CAS\ low 0 0 0 ns tASR Setup time, row address before RAS\ low 0 0 0 ns tDS Setup time, data 5 0 0 0 ns tRCS Setup time, read before CAS\ low 0 0 0 ns tCWL Setup time, W\ low before CAS\ high 20 25 30 ns tRWL Setup time, W\ low before RAS\ high 20 25 30 ns tWCS Setup time, W\ low before CAS\ low (early-write operation only) 0 0 0 ns tWSR Setup time, W\ High (CBR refresh only) 10 10 10 ns tCAH Hold time, column address after CAS\ low 15 20 20 ns tDHR Hold time, data after RAS\ low 5 tDH Hold time, data tAR Hold time, column address after CAS\ low tRAH Hold time, row address after RAS\ low tRCH Hold time, read after CAS\ High Hold time, read after RAS\ High Hold time, write after CAS\ low (early-write operation only) tRRH tWCH 4 60 75 90 ns 15 20 25 ns 60 75 90 ns 10 15 15 ns 6 0 0 0 ns 6 0 0 0 ns 15 20 25 ns ns 4 tWCR Hold time, write after RAS\ low 60 75 90 tWHR Hold time, W\ High (CBR refresh only) 10 10 10 ns tOEH Hold time, OE\ command 20 25 30 ns tROH 20 25 30 ns 70 80 90 ns 20 20 25 ns tCRP Hold time, RAS\ referenced to OE\ Delay time, column address to W\ low (read-write operation only) Delay time, RAS\ low to CAS\ High (CBR refresh only) Delay time, CAS\ High to RAS\ low 0 0 0 ns tCSH Delay time, RAS\ low to CAS\ High 80 100 120 ns tCSR Delay time, CAS\ low to RAS\ low (CBR refresh only) 10 10 10 ns tCWD Delay time, CAS\ low to W\ low (read-write operation only) 50 60 70 ns tAWD tCHR NOTES: 1. All cycle times assume tT = 5ns. 2. To assure tPC min, tASC should be > tCP. 3. In a read-write cycle, tRWD and tRWL must be observed. 4. In a read-write cycle, tCWD and tCWL must be observed. 5. Referenced to the later of CAS\ or W\ in write operations. 6. Either tRRH or tRCH must be satisfied for a read cycle. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 DRAM SMJ44400 Austin Semiconductor, Inc. TIMING REQUIREMENTS (continued) SYM PARAMETER 1 MIN 15 -8 MAX 40 MIN 20 -10 MAX 50 MIN 20 -12 MAX 65 UNIT ns tRAD Delay time, RAS\ low to column address tRAL Delay time, column addresss to RAS\ High 40 50 55 ns tCAL Delay time, column addresss to CAS\ High 40 50 55 ns 1 20 60 25 75 25 90 ns tRCD Delay time, RAS\ low to CAS\ low tRPC Delay time, RAS\ High to CAS\ low 0 0 0 ns tRSH Delay time, CAS\ low to RAS\ High 20 25 30 ns tRWD Delay time, RAS\ low to W\ low (read-write operation only) 110 135 160 ns tCLZ CAS\ to output in low Z tOED OE\ to data delay tREF Refresh time interval 2 0 0 0 ns 20 25 30 ns 16 16 16 ms 3 tT Tranistion time NOTES: 1. Maximum value specified only to assure access time. 2. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access times as the outputs are driven when CAS\ and OE\ are low. 3. Transition times (rise and fall) for RAS\ and CAS\ are to be a minimum of 3ns and a maximum of 50ns. PARAMETER MEASUREMENT INFORMATION Figure 1. Load Circuit for Timing Parameters 5V 1.31V R1 = 828Ω RL = 218Ω Output Under Test Output Under Test R2 = 295Ω CL = 100 pF1 CL = 100 pF1 (a) LOAD CIRCUIT (b) ALTERNATE LOAD CIRCUIT NOTES: 1. CL includes probe and fixture capacitance. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 DRAM Austin Semiconductor, Inc. SMJ44400 READ-CYCLE TIMING 1 NOTES: 1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access tiems as the outputs are driven when CAS\ and OE\ are low. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 DRAM Austin Semiconductor, Inc. SMJ44400 EARLY-WRITE-CYCLE TIMING SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 DRAM Austin Semiconductor, Inc. SMJ44400 WRITE-CYCLE TIMING SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 DRAM Austin Semiconductor, Inc. SMJ44400 READ-WRITE CYCLE TIMING (1) NOTES: 1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access tiems as the outputs are driven when CAS\ and OE\ are low. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 DRAM SMJ44400 Austin Semiconductor, Inc. ENHANCED-PAGE-MODE READ-CYCLE TIMING (2) (2) (1) NOTES: 1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access tiems as the outputs are driven when CAS\ and OE\ are low. 2. Access time is tCPA or tAA dependent. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 DRAM Austin Semiconductor, Inc. SMJ44400 ENHANCED-PAGE-MODE WRITE-CYCLE TIMING2 (1) (1) NOTES: 1. Referenced to CAS\ or W\, whichever occurs last. 2. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 DRAM SMJ44400 Austin Semiconductor, Inc. ENHANCED-PAGE-MODE READ-WRITE-CYCLE TIMING2 (1) (1) NOTES: 1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access times as the outputs are driven when CAS\ and OE\ are low. 2. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 DRAM Austin Semiconductor, Inc. SMJ44400 RAS\-ONLY REFRESH TIMING SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 DRAM Austin Semiconductor, Inc. SMJ44400 AUTOMATIC-CBR-REFRESH-CYCLE TIMING SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 DRAM Austin Semiconductor, Inc. SMJ44400 HIDDEN-REFRESH-CYCLE (READ) TIMING (1) NOTES: 1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access times as the outputs are driven when CAS\ and OE\ are low. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 17 DRAM SMJ44400 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #113 (Package Designator JD) SMD 5962-90847, Case Outline U D D1 A Q L E S1 b2 e b Pin 1 eA c SMD Specifications SYMBOL A b b2 c D D1 E eA e Q L S1 MIN --0.015 0.045 0.008 0.980 0.890 0.380 0.385 MAX 0.175 0.021 0.065 0.014 1.030 0.910 0.410 0.420 0.100 BSC 0.015 0.125 --- 0.060 0.200 0.070 NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits. * All measurements are in inches. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 DRAM SMJ44400 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #308 (Package Designator HR) SMD 5962-90847, Case Outline X E L 123456 123456 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 1234 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 e D b S Q c A SYMBOL A b c D E e L Q S SMD Specifications MIN MAX 0.080 0.100 0.015 0.021 0.004 0.010 0.690 0.710 0.483 0.497 0.050 TYP 0.340 0.370 0.025 0.035 0.101 0.133 NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits. * All measurements are in inches. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 19 DRAM SMJ44400 Austin Semiconductor, Inc. ORDERING INFORMATION EXAMPLE: SMJ44400-12JDM Device Number Speed ns Package Type Process SMJ44400 -80 JD /* SMJ44400 -10 JD /* SMJ44400 -12 JD /* EXAMPLE: SMJ44400-80HRM Device Number Speed ns Package Type Process SMJ44400 -80 HR /* SMJ44400 -10 HR /* SMJ44400 -12 HR /* *AVAILABLE PROCESSES M = Extended Temperature Range SMJ44400 Rev. 2.0 10/01 -55oC to +125oC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 20 DRAM Austin Semiconductor, Inc. SMJ44400 ASI TO DSCC PART NUMBER CROSS REFERENCE* ASI Package Designator JD TI Part #** SMJ44400-12/JDM SMJ44400-10/JDM SMJ44400-80/JDM SMD Part # 5962-9084701MUA 5962-9084702MUA 5962-9084703MUA ASI Package Designator HR TI Part #** SMJ44400-12/HRM SMJ44400-10/HRM SMJ44400-80/HRM SMD Part # 5962-9084701MXA 5962-9084702MXA 5962-9084703MXA * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. ** Parts are listed on SMD under the old Texas Instruments part number. ASI purchased this product line in November of 1999. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 21