TI TMS465169

 SMHS566B − JUNE 1997 − REVISED APRIL 1998
D Organization . . . 4 194 304 by 16 Bits
D Single 3.3-V Power Supply (± 0.3 V
DGE PACKAGE
( TOP VIEW )
Tolerance)
D Performance Ranges:
ACCESS ACCESS ACCESS
TIME
TIME
TIME
tRAC
tCAC
tAA
MAX
MAX
MAX
’46x169/P-50
50 ns
13 ns
25 ns
’46x169/P-60
60 ns
15 ns
30 ns
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
VCC
W
RAS
NC
NC
W
NC
A0
A1
A2
A3
A4
A5
VCC
EDO
CYCLE
tHPC
MIN
20 ns
25 ns
D Extended-Data-Out (EDO) Operation
D xCAS-Before-RAS ( xCBR) Refresh
D Long Refresh Period and Self-Refresh
D
D
D
D
Option ( TMS46x169P)
3-State Unlatched Output
Low Power Dissipation
High-Reliability Plastic 50-Lead
400-Mil-Wide Surface-Mount Thin
Small-Outline Package ( TSOP) (DGE Suffix)
Operating Free-Air Temperature Range
0°C to 70°C
AVAILABLE OPTIONS
DEVICE
POWER
SUPPLY
SELFREFRESH,
BATTERY
BACKUP
REFRESH
CYCLES
TMS465169
3.3 V
—
4 096 in 64 ms
TMS465169P
3.3 V
Yes
4 096 in 128 ms
1
50
2
49
3
48
4
47
5
46
6
45
7
44
8
43
9
42
10
41
11
40
12
39
13
38
14
15
37
36
16
35
17
34
18
33
19
32
20
31
21
30
22
29
23
28
24
27
25
26
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
VSS
LCAS
UCAS
OE
NC
NC
A12/NC†
A11
A10
A9
A8
A7
A6
VSS
description
The and TMS465169 is a high-speed,
67 108 864-bit dynamic random-access memory
(DRAM) device organized as 4 194 304 words of
16 bits. The TMS465169P is similar DRAM but
includes a long refresh period and a self-refresh
option. Both employ state-of-the-art technology
for high performance, reliability, and low power at
low cost.
PIN NOMENCLATURE
A0 −A12†
DQ0 −DQ15
LCAS
UCAS
NC
OE
RAS
VCC
VSS
W
Address Inputs
Data In / Data Out
Lower Column-Address Strobe
Upper Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
3.3-V Supply
Ground
Write Enable
† A12 is NC for TMS465169 and TMS465169P.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0 !)) '!!&"&#+
POST OFFICE BOX 1443
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1
SMHS566B − JUNE 1997 − REVISED APRIL 1998
description (continued)
These devices feature maximum RAS access times of 50 and 60 ns. All addresses and data-in lines are latched
on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS465169/ P is offered in a 50-lead plastic surface-mount TSOP (DGE suffix). This package is designed
for operation from 0°C to 70°C.
2
POST OFFICE BOX 1443
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
logic symbol (TMS465169 and TMS465169P)†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RAS
19
20
21
22
23
24
27
28
29
30
31
32
14
LCAS 38
UCAS 37
RAM 1M × 16
20D10/21D0
A
0
4194303
20D19 / 21D9
20D20
20D21
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21
G24
&
23C22
31
C21
G34
&
31
23C32
Z31
W 13
OE 36
DQ0 2
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
3
4
5
7
8
9
10
41
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
42
43
44
46
47
48
49
23,21D
24,25EN27
34,25EN37
25
A,22D
∇26,27
A, Z26
A,32D
∇36,37
A, Z36
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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3
SMHS566B − JUNE 1997 − REVISED APRIL 1998
functional block diagram (TMS465169 and TMS465169P)
RAS UCAS LCAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
Column Address
Buffers
512K Array
512K Array
A9
Row Address
Buffers
A10,
A11
512K Array
R
o
w
12
512K Array
16
I/O
Buffers
64
2
POST OFFICE BOX 1443
DataOut
Reg.
16
16
DQ0 −DQ15
512K Array
12
4
DataIn
Reg.
512K Array
D
e
c
o
d
e
64
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• HOUSTON, TEXAS 77251−1443
SMHS566B − JUNE 1997 − REVISED APRIL 1998
operation
dual xCAS
Two xCAS pins (LCAS and UCAS) are provided to give independent byte control of the 16 data I/O pins
(DQ0−DQ15), with LCAS corresponding to DQ0 −DQ7 and UCAS corresponding to DQ8 −DQ15. Each xCAS
going low enables its corresponding DQx pins.
In write cycles, data-in setup and hold times (tDS and tDH), and write-command setup and hold times (tWCS, tCWL,
and tWCH) must be satisfied for each individual xCAS to ensure writing into the storage cells of the corresponding
DQ pins.
extended data out
Extended data out (EDO) allows for data output rates of up to 50 MHz for 50-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup and hold and address
multiplex is eliminated. The maximum number of columns that can be accessed is determined by tRASP , the
maximum RAS low time.
EDO does not enter the DQs into the high-impedance state with the rising edge of xCAS. The output remains
valid for the system to latch the data. After xCAS goes high, the DRAM decodes the next address. OE and W
can be used to control the output impedance. Descriptions of OE and W further explain the benefit of EDO
operation.
address: A0 −A11 ( TMS465169, TMS465169P)
Twenty-two address bits are required to decode each of the 4 194 304 storage cell locations. For the
TMS465169 and TMS465169P, 12 row-address bits are set up on A0 −A11 and latched on the chip by RAS.
Ten column-address bits are set up on A0 −A9 and latched on the chip by the first xCAS. All addresses must
be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip-enable in that it activates the
sense amplifiers as well as the row decoder. xCAS is used as a chip-select, activating its corresponding output
buffer and latching the address bits into the column-address buffers.
To latch in a new column address, both xCAS pins must be brought high. The column-precharge time (see
parameter tCP) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle.
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. The data input is disabled when the read mode is selected. When W goes low prior to xCAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation
independent of the state of OE. This permits early-write operations to be completed with OE grounded. If W goes
low in an EDO read cycle, the DQ pins go into the high-impedance state as long as xCAS is high.
data in (DQ0 −DQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to an xCAS
falling edge, and data is strobed into the on-chip data latch for the corresponding DQ pins with setup and hold
times referenced to this xCAS signal.
In a delayed-write or read-modify-write cycle, xCAS is already low and data is strobed in by W with setup and
hold times referenced to this signal. In this cycle, OE must be high to bring the output buffers to the
high-impedance state prior to impressing data on the I / O lines (see parameter tOED).
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
data out (DQ0 −DQ15)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE
are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with
the negative transition of xCAS) as long as tRAC and tAA are satisfied. The delay time from xCAS low to valid
data out is measured from each individual xCAS to its corresponding DQx pin.
output enable (OE)
OE controls the impedance of the output buffers. While xCAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance. There are two methods for placing
the DQs into the high-impedance state and keeping them in that state during xCAS high time by using OE. The
first method is to transition OE high before xCAS transitions high and to keep OE high for tCHO past the xCAS
transition (see Figure 7). This disables the DQs and they remain in the high-impedance state, regardless of OE,
until xCAS falls again. The second method is to have OE low as xCAS transitions high. Then OE can pulse high
for a minimum of tOEP anytime during xCAS high time, disabling the DQs regardless of further transitions on
OE until xCAS falls again (see Figure 7).
RAS-only refresh
A refresh operation must be performed at least once every 64 ms (128 ms for TMS465169P) to retain data. This
is achieved by strobing each of the 4096 rows for TMS465169/ P. A normal read or write cycle refreshes all bits
in each row that is selected. A RAS-only operation can be used by holding both xCAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pins. This is accomplished by holding
xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
An xCBR refresh is achieved by bringing at least one xCAS low earlier than RAS (see parameter tCSR) and
holding it low after RAS falls (see parameter tCHR). For successive xCBR refresh cycles, xCAS can remain low
while cycling RAS. The external address is ignored and the refresh address is generated internally.
battery-backup refresh (TMS465169P)
A low-power battery-backup refresh mode that requires less than 250 µA of refresh current is available on the
TMS465169P. Data integrity is maintained using xCBR refresh with a period of 31.25 µs while holding RAS low
for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels
( VIL < 0.2 V, VIH > VCC − 0.2 V).
self-refresh ( TMS465169P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both
held low for a minimum of 100 µs. The chip is then refreshed internally by an on-board oscillator. No external
address is required because the xCBR counter is used to keep track of the address. To exit the self-refresh
mode, both RAS and xCAS are brought high to satisfy tCHS. Upon exiting self-refresh mode, a burst refresh
(refresh of a full set of row addresses) must be executed before continuing with normal operation. The burst
refresh ensures that the DRAM is completely refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs, followed by a minimum of eight initialization
cycles, is required after power up to the full VCC level. These eight initialization cycles must include at least one
refresh (RAS-only or xCBR) cycle.
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Voltage range on any pin (see Note 1): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
’465169/P
VCC
VSS
Supply voltage
VIH
VIL
High-level input voltage
MIN
NOM
MAX
3
3.3
3.6
Supply voltage
0
2
Low-level input voltage (see Note 2)
− 0.3
UNIT
V
V
VCC + 0.3
0.8
V
V
TA
Operating free-air temperature
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
POST OFFICE BOX 1443
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
TMS465169/P
electrical characteristics over recommended ranges of supply voltage and operating free-air
conditions (unless otherwise noted)
PARAMETER
’465169/P - 50
TEST CONDITIONS†
MIN
’465169/P - 60
MAX
MAX
UNIT
High-level output
voltage
IOH = − 2 mA
IOH = − 100 µA
LVTTL
VOH
0.4
0.4
Low-level output voltage
IOL = 2 mA
IOL = 100 µA
LVTTL
VOL
LVCMOS
0.2
0.2
II
Input current (leakage)
VCC = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VCC
± 10
± 10
µA
IO
Output current (leakage)
VCC = 3.6 V,
xCAS high
VO = 0 V to VCC,
± 10
± 10
µA
ICC1‡§
Average read- or write-cycle
current
VCC = 3.6 V,
Minimum cycle
130
110
mA
1.5
1.5
mA
Average standby current
VIH = 2 V (LVTTL),
After one memory cycle,
RAS and xCAS high
VIH = 2 V (LVTTL),
After one memory cycle,
RAS and xCAS high
1
1
mA
’465169
500
500
’465169P
300
300
ICC2
LVCMOS
VIH = VCC − 0.2 V
(LVCMOS),
After one memory cycle,
RAS and xCAS high
2.4
MIN
2.4
VCC −0.2
’465169
’465169P
V
VCC −0.2
V
A
µA
ICC3§
RAS-only refresh, average
refresh current
VCC = 3.6 V,
RAS cycling,
Minimum cycle,
xCAS high
130
110
mA
ICC4‡¶
Average EDO current
VCC = 3.6 V,
RAS low,
tHPC = MIN,
xCAS cycling
120
100
mA
ICC5
Average CBR refresh current
VCC = 3.6 V,
Minimum cycle,
RAS low after CAS low
130
110
mA
ICC6#
Average self-refresh current
xCAS < 0.2 V,
RAS < 0.2 V,
Measured after tRASS min
400
400
µA
ICC10#
Average battery back-up
operating current,
xCBR only
tRC = 31.25 µs, tRAS ≤ 300 ns,
VCC − 0.2 V ≤ VIH ≤ 3.9 V,
0 V ≤ VIL ≤ 0.2 V, W and OE = VIH,
Address and data stable
550
550
µA
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
# For TMS465169P only
8
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capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 −A12†
5
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(RC)
Input capacitance, xCAS and RAS
7
pF
Ci(W)
Input capacitance, W
Output capacitance‡
7
pF
7
pF
CO
† A12 is NC for TMS465169 and TMS465169P.
‡ xCAS and OE = VIH to disable outputs
NOTE 3: VCC = 3.3 V ± 0.3 V, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’465169/P - 50
PARAMETER
MIN
MAX
’465169/P - 60
MIN
MAX
UNIT
tAA
tCAC
Access time from column address (see Note 5)
25
30
ns
Access time from xCAS (see Note 5)
13
15
ns
tCPA
tRAC
Access time from xCAS precharge (see Note 5)
28
35
ns
Access time from RAS (see Note 5)
50
60
ns
tOEA
tCLZ
Access time from OE (see Note 5)
13
15
ns
Delay time, xCAS to output in the low-impedance state
0
tOEZ
tREZ
Output buffer turnoff delay from OE (see Note 6)
3
13
3
15
ns
Output buffer turnoff delay from RAS (see Note 6)
3
13
3
15
ns
tCEZ
tWEZ
Output buffer turnoff delay from xCAS (see Note 6)
3
13
3
15
ns
Output buffer turnoff delay from W (see Note 6)
3
13
3
15
ns
0
ns
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
5. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
6. The MAX specifications of tREZ , tCEZ , tWEZ and tOEZ are specified when the output is no longer driven. Data-in should not be driven
until one of the applicable maximum specifications is satsified.
EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’465169/P - 50
MIN
MAX
’465169/P - 60
MIN
MAX
UNIT
tHPC
tPRWC
Cycle time, EDO page-mode read or write
20
25
ns
Cycle time, EDO read-write
57
68
ns
tCSH
tCHO
Delay time, RAS active to xCAS precharge
40
48
ns
Hold time, OE from xCAS
5
5
ns
tDOH
tCAS
Hold time, output from xCAS active
5
5
ns
Pulse duration, xCAS active (see Note 7)
8
tWPE
tCP
Pulse duration, W (output disable only)
5
5
ns
Pulse duration, xCAS precharge
8
10
ns
tOCH
tOEP
Setup time, OE before xCAS
5
5
ns
Precharge time, OE (output disable only)
5
5
ns
10 000
10
10 000
ns
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
7. In a read-write cycle, tCWD and tCWL must be observed.
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’465169/P -50
MIN
MAX
’465169/P -60
MIN
MAX
UNIT
tRC
tRWC
Cycle time, read
tRASP
tRAS
Pulse duration, RAS active, page mode (see Note 8)
50 100 000
60 100 000
ns
Pulse duration, RAS active, nonpage mode (see Note 8)
50
60
ns
tRP
tWP
Pulse duration, RAS precharge
30
40
ns
Pulse duration, write command
8
10
ns
tASC
tASR
Setup time, column address
0
0
ns
Setup time, row address
0
0
ns
tDS
tRCS
Setup time, data in (see Note 9)
0
0
ns
Setup time, read command
0
0
ns
tCWL
tRWL
Setup time, write command before xCAS precharge
8
10
ns
Setup time, write command before RAS precharge
8
10
ns
Setup time, write command before xCAS active
(early-write only)
0
0
ns
tWRP
tCSR
Setup time, write before RAS active (xCBR refresh only)
5
5
ns
Setup time, xCAS referenced to RAS (xCBR refresh only)
5
5
ns
tCAH
tDH
Hold time, column address
8
10
ns
Hold time, data in (see Note 9)
8
10
ns
tRAH
tRCH
Hold time, row address
8
10
ns
Hold time, read command referenced to xCAS (see Note 10)
0
0
ns
tRRH
Hold time, read command referenced to RAS (see Note 10)
0
0
ns
tWCH
Hold time, write command during xCAS active
(early-write only)
8
10
ns
tWCS
Cycle time, read-write
84
104
ns
111
135
ns
10 000
10 000
tRHCP
tOEH
Hold time, RAS active from xCAS precharge
28
35
ns
Hold time, OE command
13
15
ns
tROH
tWRH
Hold time, RAS referenced to OE
8
10
ns
Hold time, write after RAS active (xCBR refresh only)
8
10
ns
tCHS
Hold time, CAS active after RAS precharge (self-refresh)
− 50
− 50
ns
tAWD
Delay time, column address to write command
(read-write only)
42
49
ns
Delay time, xCAS referenced to RAS (xCBR refresh only)
8
10
ns
Delay time, xCAS precharge to RAS
5
5
ns
Delay time, xCAS to write command
(read-write operation only)
30
34
ns
tCHR
tCRP
tCWD
NOTES: 4.
8.
9.
10.
10
With ac parameters, it is assumed that tT = 2 ns.
In a read-write cycle, tRWD and tRWL must be observed.
Referenced to the later of xCAS or W in write operations
Either tRRH or tRCH must be satisfied for a read cycle.
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timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4) (continued)
’465169/P - 50
MIN
MAX
’465169/P - 60
MIN
MAX
tOED
tRAD
Delay time, OE to data in
13
Delay time, RAS to column address (see Note 11)
10
tRAL
tCAL
Delay time, column address to RAS precharge
25
Delay time, column address to xCAS precharge
15
tRCD
tRPC
Delay time, RAS to xCAS (see Note 11)
12
Delay time, RAS precharge to xCAS
5
5
ns
tRSH
tRWD
Delay time, xCAS active to RAS precharge
8
10
ns
67
79
ns
tCPW
tRASS
Delay time, xCAS precharge to write command (read-write only)
tRPS
Pulse duration, RAS precharge after self refresh
tREF
Refresh time interval
Delay time, RAS active to write command (read-write only)
Pulse duration, RAS active, self-refresh (see Note 12)
’465169
’465169P
15
UNIT
25
12
ns
30
30
ns
18
37
14
ns
ns
45
ns
45
54
ns
100
100
µs
90
110
ns
64
64
ms
128
128
ms
tT
Transition time
1
50
1
50
ns
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
11. The maximum value is specified only to assure access time.
12. During the period of 10 µs ≤ tRASS ≤ 100 µs, the device is in transition state from normal operational mode to self-refresh mode.
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11
SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
1.4 V
3.3 V
500 Ω
1 178 Ω
Output Under Test
Output Under Test
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameters
12
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868 Ω
SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tCSH
tRCD
tRSH
tCRP
tCRP
tCAS
tASR
XCAS
tRAD
tCP
tASC
tRAH
Address
Row
tCAL
tRAL
Don’t Care
Column
tRCS
tRRH
tRCH
tCAH
W
Don’t Care
Don’t Care
tCAC
tCEZ
tREZ
tAA
DQ0 −DQ15
Hi-Z
Valid Data Out
See Note B
tCLZ
tRAC
tWEZ
tOEA
tWPE
tOEZ
tROH
OE
Don’t Care
Don’t Care
NOTES: A. When LCAS corresponds to DQ0 −DQ7 and UCAS corresponds to DQ8 −DQ15, byte-reading can be achieved by holding xCAS
high for the other byte.
B. Data out can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing (see Note A)
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13
SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCSH
tCAS
tASR
xCAS
tCP
tASC
tCAL
tRAL
tRAH
Address
tCAH
Row
Column
Don’t Care
tCWL
tRAD
tRWL
tWCH
W
tWCS
Don’t Care
Don’t Care
tDH
tDS
DQ0 −DQ15
Don’t Care
Valid Data
Don’t Care
OE
NOTE A: When LCAS corresponds to DQ0 −DQ7 and UCAS corresponds to DQ8 −DQ15, byte writing can be achieved by holding xCAS high
for the other byte.
Figure 3. Early-Write-Cycle Timing (see Note A)
14
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCAS
tCSH
tASR
tASC
xCAS
tCP
tRAL
tCAL
tRAH
tCAH
Address
Row
Don’t Care
Column
tCWL
tRAD
W
tDS
tRWL
Don’t Care
Don’t Care
tWP
tCLZ
tDH
Don’t Care
Valid Data In
DQ0 −DQ15
Invalid Data Out
tOED
tOEH
OE
Don’t Care
Don’t Care
NOTE A: When LCAS corresponds to DQ0 −DQ7 and UCAS corresponds to DQ8 −DQ15, byte writing can be achieved by holding xCAS high
for the other byte.
Figure 4. Write-Cycle Timing (see Note A)
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15
SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tCRP
tRCD
tCAS
tASR
xCAS
tCP
tRAH
tCAH
tRAD
Address
tT
tASC
Row
Column
Don’t Care
tCWL
tRCS
tRWL
tRWD
tWP
Don’t Care
W
tAWD
tCWD
tCAC
tDS
tAA
tDH
tCLZ
DQ0 −DQ15
Hi-Z
Data
In
Data
Out
See Note A
tRAC
tOEZ
tOEA
tOED
OE
Don’t Care
Don’t Care
tOEH
Don’t Care
NOTE A: Data out can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 5. Read-Write-Cycle Timing
16
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRCD
tCRP
tCAS
UCAS
tRHCP
tRSH
tCSH
tHPC
tCAL
tCP
tCAS
tASR
LCAS
tRAH
tCAL
tASC
tRAL
tCAH
Address
Row
Column
#1
Don’t Care
Don’t Care
Column #2
tRAD
W
tRCH
Don’t
Care
tRRH
Don’t Care
tCAC
(see Note A)
tAA
tCPA
(see Note B)
tRCS
tRAC
tREZ
tDOH
tCLZ
DQ8 −DQ15
Data #1
(see Note C)
tAA
DQ0 −DQ7
Data #1
Data #2
(see Note C)
tOEZ
OE
NOTES: A.
B.
C.
D.
Don’t Care
tOEA
tCAC is measured from xCAS to its corresponding DQx.
Access time is tCPA-, tAA-, or tCAC-dependent.
Data out can go from the high-impedance state to an invalid-data state prior to the specified access time.
A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write timing
specifications are not violated.
Figure 6. EDO Read-Cycle Timing (see Note D)
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17
SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tHPC
tCAS
tCP
tRSH
xCAS
tASR
tRAH
Row
Address
tASC
tCAL
tCAH
tRAL
Column #1
tRAD
Column #2
Column #3
tOCH
tCHO
tOEP
OE
tOEA
tRRH
tRCS
tRCH
tOEA
tCAC
W
tDOH
tCLZ
tAA
tOEZ
tCAC
tCAC
tAA
Data #1
Data #1
Data #2
NOTE A: Data out is turned off by tCEZ if RAS goes high during xCAS low.
Figure 7. EDO Read-Cycle Timing With OE Control
18
POST OFFICE BOX 1443
(see Note A)
tREZ
tOEZ
tRAC
DQ0 −DQ15
tCEZ
tCPA
tAA
• HOUSTON, TEXAS 77251−1443
Data #3
SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRASP
tRHCP
RAS
tCSH
tHPC
tCAS
tCAL
xCAS
tCRP
tCAS
tASR
tRAH
tASC
Address
tRSH
tCP
Row
tCAH
tCAL
Column #1
tRAL
Column #2
Column #3
tRAD
OE
tOEA
tCAC
tRCS
tCAC
tWPE
tRCH
tRRH
W
tDOH
tCAC
tWEZ
tAA
tCPA
tCPA
tCLZ
tCEZ
(see Note A)
tAA
tAA
tRAC
DQ0 −DQ15
Data #1
Data #2
Data #3
NOTE A: Data out is turned off by tCEZ if RAS goes high during xCAS low.
Figure 8. EDO Read-Cycle Timing With W Control
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRSH
tCAS
UCAS
tRHCP
tHPC
tRCD
tCSH
tCP
tCAS
LCAS
tCRP
tASR
tCAH
tASC
tCAL
tCAL
tRAH
Address
Don’t Care
Column
Row
tRAD
tRAL
Don’t Care
Column
tCWL
tCWL
tWP
tDS
W
tRWL
tDS
Don’t Care
Don’t Care
Don’t Care
tDH
DQ8 −
DQ15
Don’t Care
Valid In
tDH
DQ0 −
DQ7
Valid In
Valid In
Don’t Care
tOED
OE
NOTE A: A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write timing
specifications are not violated.
Figure 9. EDO Write-Cycle Timing (see Note A)
20
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRSH
tCAS
UCAS
tRCD
tRHCP
tHPC
tCSH
tCP
tCAS
LCAS
tCRP
tASR
tCAH
tASC
tCAL
tRAH
Address
tRAL
Don’t Care
Column
Row
tRAD
tCWL
tCWL
(see Note D)
tWCS
(see Note B)
W
DQ8 −
DQ15
tRWL
tWCH
(see Note B)
Don’t Care
(see Note C)
Don’t Care
Column
Don’t Care
Don’t Care
tDS
Don’t Care
Valid In
tDH (see Note C)
DQ0 −
DQ7
Valid In
Valid In
Don’t Care
OE
NOTES: A. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write timing
specifications are not violated.
B. tWCS and tWCH must be satisfied for each xCAS in an early-write cycle.
C. tDS and tDH of a DQ input are referenced to the corresponding xCAS.
D. tCWL must be satisfied for each xCAS to ensure proper writing to each byte.
Figure 10. EDO Early Write-Cycle Timing (see Note A)
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21
SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRSH
tPRWC
tRCD
tCAS
tASR
tASC
xCAS
tCAL
tCAH
tRAL
tRAD
Row
Address
tCRP
tCP
Column 2
Column 1
Don’t Care
tRAH
tCWL
tCWD
tCPW
tAWD
tRWL
tWP
tRWD
W
tRCS
tCPA
tAA
tDH
tRAC
Valid Out 2
(see Note A)
tDS
tCAC
Valid
In 1
DQ0 −DQ15
tCLZ
tOEA
tOEH
Valid
In 2
Valid
Out 1
tOEZ
tOED
tOEH
OE
NOTES: A. Data out can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated.
Figure 11. EDO Read-Write-Cycle Timing (see Note B)
22
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tCRP
tT
xCAS
See Note A
Don’t Care
tASR
Address
Don’t Care
tRPC
tRAH
Don’t Care
Row
Row
Don’t Care
W
Hi-Z
DQ0 −DQ15
Don’t Care
OE
NOTE A: Both LCAS and UCAS must be high.
Figure 12. RAS-Only Refresh-Cycle Timing
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRP
tRAS
tRAS
RAS
tCHR
tCAS
xCAS
tCAH
tASC
tRAH
tASR
Address
Row
Don’t Care
Col
tWRH
tWRP
tWRH
tRRH
tWRP
tRAC
W
tCAC
tREZ
tWEZ
tAA
tCEZ
Valid Data Out
DQ0 −DQ15
tCLZ
tOEZ
tOEA
OE
Figure 13. Hidden-Refresh-Cycle (Read) Timing
24
tWRH
tWRP
tRCS
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
xCAS
tCAH
tASC
tRAH
tASR
Row
Address
Don’t Care
Col
tWRH
tWRP
tWCS
tWP
W
tWCH
tDH
tDS
DQ0 −DQ15
Don’t Care
Valid Data
Don’t Care
OE
Figure 14. Hidden-Refresh Cycle (Write) Timing
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25
SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
xCAS
tWRP
tWRH
Don’t Care
W
Address
Don’t Care
OE
Don’t Care
Hi-Z
DQ0 −DQ15
NOTE A: Any xCAS can be used. If both UCAS and LCAS are used, both must satisfy tCSR and tCHR.
Figure 15. Automatic (xCBR) Refresh-Cycle Timing
26
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tRASS
RAS
tRPC
tRPS
tCSR
tCHS
xCAS
tCP
Address
Don’t Care
tWRP
tWRH
W
Don’t Care
OE
Don’t Care
DQ0 −DQ15
Hi-Z
Figure 16. Self-Refresh-Cycle Timing
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27
SMHS566B − JUNE 1997 − REVISED APRIL 1998
device symbolization (TMS465169 illustrated)
-SS
TI
Speed ( - 50, - 60)
Low Power/Self Refresh Designator (Blank or P)
TMS465169
DGE
Package Code
W
A
Y
M LLLL
P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
28
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SMHS566B − JUNE 1997 − REVISED APRIL 1998
MECHANICAL DATA
DGE (R-PDSO-G50)
PLASTIC SMALL-OUTLINE PACKAGE
0.018 (0,45)
0.012 (0,30)
0.031 (0,80)
50
0.006 (0,16) M
26
0.471 (11,96)
0.455 (11,56)
0.404 (10,26)
0.396 (10,06)
1
25
0.006 (0,15) NOM
0.829 (21,05)
0.821 (20,85)
Gage Plane
0.010 (0,25)
0°−ā 5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.047 (1,20) MAX
0.000 (0,00) MIN
0.004 (0,10)
4040070-5 / D 06/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
29
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