SGLS220A − DECEMBER 2003 − REVISED MAY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D D D D MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Available in 5-V, 4.85-V, and 3.3-V Fixed-Output and Adjustable Versions Very Low-Dropout Voltage . . . Maximum of 32 mV at IO = 100 mA (TPS71H50) Very Low Quiescent Current − Independent of Load . . . 285 µA Typ Extremely Low Sleep-State Current 0.5 µA Max 2% Tolerance Over Specified Conditions For Fixed-Output Versions Output Current Range of 0 mA to 500 mA TSSOP Package Option Offers Reduced Component Height for Space-Critical Applications Thermally Enhanced Surface-Mount Package Power-Good (PG) Status Output PWP PACKAGE (TOP VIEW) GND/HEATSINK GND/HEATSINK GND NC EN IN IN NC GND/HEATSINK GND/HEATSINK 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND/HEATSINK GND/HEATSINK NC NC PG SENSE†/FB‡ OUT OUT GND/HEATSINK GND/HEATSINK PWP PACKAGE (BOTTOM VIEW) Thermal Pad description The TPS71Hxx integrated circuits are a family of micropower low-dropout (LDO) voltage regulators. An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device. NC − No internal connection † SENSE − Fixed voltage options only (TPS71H33, TPS71H48, and TPS71H50) ‡ FB − Adjustable version only (TPS71H01) Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 32 mV at an output current of 100 mA for the TPS71H50) and is directly proportional to the output current (see Figure 1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and remains independent of output loading (typically 285 µA over the full range of output current, 0 mA to 500 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. The LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 0.5 µA maximum at TJ = 25°C. Power good (PG) reports low output voltage and can be used to implement a power-on reset or a low-battery indicator. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2008 Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 description (continued) 0.25 TA = 25°C Dropout Voltage − V 0.2 TPS71H33 0.15 TPS71H48 0.1 TPS71H50 0.05 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 IO − Output Current − A Figure 1. Dropout Voltage Versus Output Current The TPS71Hxx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for adjustable version). The TPS71Hxx family is available in a TSSOP (20-pin) thermally enhanced surface-mount power package. The package has an innovative thermal pad that, when soldered to the printed-wiring board (PWB), enables the device to dissipate several watts of power (see Thermal Information section). Maximum height of the package is 1.2 mm. AVAILABLE OPTIONS†‡ OUTPUT VOLTAGE (V) TJ −40°C −40 C to 125 125°C C TSSOP (PWP) MIN TYP MAX 4.9 5 5.1 4.75 4.85 4.95 TPS71H50QPWPRQ1§ TPS71H48QPWPRQ1§ 3.23 3.3 3.37 TPS71H33QPWPRQ1 Adjustable† 1.2 V to 9.75 V TPS71H01QPWPRQ1§ † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. § Product Preview 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TPS71Hxx† 6 VI PG IN 7 PG 15 SENSE IN OUT 5 0.1 µF 16 OUT EN 14 VO 13 + GND 3 CO ‡ 10 µF CSR † TPS71H33, TPS71H48, TPS71H50 (fixed-voltage options) ‡ Capacitor selection is nontrivial. See application information section for details. Figure 2. Typical Application Configuration functional block diagram IN RESISTOR DIVIDER OPTIONS † † EN † PG _ DEVICE R1 R2 UNIT TPS71H01 TPS71H33 TPS71H48 TPS71H50 0 420 726 756 ∞ 233 233 233 Ω kΩ kΩ kΩ NOTE A: Resistors are nominal values only. + OUT COMPONENT COUNT 1.12 V SENSE‡ /FB + _ R1 Vref = 1.178 V MOS transistors Bilpolar transistors Diodes Capacitors Resistors 464 41 4 17 76 R2 GND † Switch positions are shown with EN low (active). ‡ For most applications, SENSE should be externally connected to OUT as close as possible to the device. (For other implementations, refer to SENSE-pin connection discussion in Applications Information section.) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Input voltage range‡, VI, PG, SENSE, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 11 V Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables 1 and 2 Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE 1 − FREE-AIR TEMPERATURE (see Figure 3)§ PACKAGE TA ≤ 25°C 25 C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70 70°C C POWER RATING TA = 125 125°C C POWER RATING PWP¶ 700 mW 5.6 mW/°C 448 mW 140 mW DISSIPATION RATING TABLE 2 − CASE TEMPERATURE (see Figure 4)§ PACKAGE TC ≤ 62.5 62.5°C C POWER RATING DERATING FACTOR ABOVE TC = 62.5°C TC = 70 70°C C POWER RATING TC = 125 125°C C POWER RATING PWP¶ 25 W 285.7 mW/°C 22.9 W 7.1 W § Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section. ¶ Refer to Thermal Information section for detailed power dissipation considerations when using the TSSOP packages. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 DISSIPATION DERATING CURVE† vs FREE-AIR TEMPERATURE PD − Maximum Continuous Dissipation − mW 1400 1200 1000 800 PWP Package RθJA = 178°C/W 600 400 200 0 25 50 75 100 125 150 TA − Free-Air Temperature − °C Figure 3 MAXIMUM CONTINUOUS DISSIPATION† vs CASE TEMPERATURE PD − Maximum Continuous Dissipation − W 30 25 20 PWP Package 15 10 Measured with the exposed thermal pad coupled to an infinite heat sink with a thermally conductive compound (the thermal conductivity of the compound is 0.815 W/m ⋅ °C). The RθJC is 3.5°C/W. 5 0 25 50 75 100 125 TC − Case Temperature − °C 150 Figure 4 † Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 recommended operating conditions Input voltage, VI† MIN MAX TPS71H01-Q1 2.5 10 TPS71H33-Q1 3.77 10 TPS71H48-Q1 5.2 10 TPS71H50-Q1 5.33 10 High-level input voltage at EN, VIH 2 Low-level input voltage at EN, VIL Output current range, IO 0 UNIT V V 0.5 V 500 mA Operating virtual junction temperature range, TJ −40 125 °C † Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load) Because the TPS71H01 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for calculating VDO from rDS(on) is given in Note 2 in the electrical characteristics table. The minimum value of 2.5 V is the absolute lower limit for the recommended input voltage range for the TPS71H01. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 electrical characteristics at IO = 10 mA, EN = 0 V, CO = 4.7 µF/CSR‡ = 1 Ω, SENSE/FB shorted to OUT (unless otherwise noted) TEST CONDITIONS§ PARAMETER TJ TPS71H01-Q1, TPS71H33-Q1 TPS71H48-Q1, TPS71H50-Q1 MIN Ground current (active mode) EN ≤ 0.5 V, VI = VO + 1 V, 0 mA ≤ IO ≤ 500 mA Input current (standby mode) EN = VI, 2.7 V ≤ VI ≤ 10 V Output current limit VO = 0, VI = 10 V Pass-element leakage current in standby mode EN = VI, 2.7 V ≤ VI ≤ 10 V PG leakage current Normal operation, VPG = 10 V 25°C 25°C 0.5 −40°C to 125°C 2 1.2 25°C 0.5 −40°C to 125°C 1 0.02 −40°C to 125°C 0.5 0.5 −40°C to 125°C 61 75 µA A A µA A µA A ppm/°C 2 −40°C to 125°C 6 V ≤ VI ≤ 10 V 2.7 V ≤ VI ≤ 10 V EN hysteresis voltage 0 V ≤ VI ≤ 10 V 25°C 0.5 −40°C to 125°C 0.5 50 −0.5 0.5 −40°C to 125°C −0.5 0.5 2.05 −40°C to 125°C IPG = 300 µA 25°C −40°C to 125°C µA A 2.5 2.5 1.06 V mV 25°C 25°C Minimum VI for active pass element V 2.7 25°C IPG = 300 µA µA A °C 165 2.5 V ≤ VI ≤ 6 V UNIT 2 2 Thermal shutdown junction temperature Minimum VI for valid PG 350 −40°C to 125°C Output voltage temperature coefficient EN input current 285 460 25°C EN logic low (active mode) MAX −40°C to 125°C 25°C EN logic high (standby mode) TYP 1.5 1.9 V V ‡ CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to CO. § Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TPS71H01 electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, FB shorted to OUT at device leads (unless otherwise noted) TEST CONDITIONS‡ PARAMETER Reference voltage (measured at FB with OUT connected to FB) VI = 3.5 V, 2.5 V ≤ VI ≤ 10 V, See Note 1 IO = 10 mA 5 mA ≤ IO ≤ 500 mA, Reference voltage temperature coefficient VI = 2.4 V, Pass-element series resistance (see Note 2) Input regulation Output regulation VI = 2.4 V, 50 µA A ≤ IO ≤ 150 mA 150 mA ≤ IO ≤ 500 mA TPS71H01-Q1 MIN 25°C −40°C to 125°C TYP MAX 1.178 1.143 1.213 −40°C to 125°C 61 75 25°C 0.7 1 0.83 1.3 0.52 0.85 −40°C to 125°C −40°C to 125°C 1.3 25°C 50 µA A ≤ IO ≤ 500 mA −40°C to 125°C VI = 3.9 V, VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 25°C 0.32 50 µA ≤ IO ≤ 500 mA 25°C 0.23 VI = 2.5 V to 10 V, See Note 1 50 µA ≤ IO ≤ 500 mA, 25°C 18 −40°C to 125°C 25 IO = 5 mA to 500 mA, See Note 1 2.5 V ≤ VI ≤ 10 V, 25°C 14 −40°C to 125°C 25 IO = 50 µA to 500 mA, See Note 1 2.5 V ≤ VI ≤ 10 V, 25°C 22 −40°C to 125°C 54 IO = 500 mA, See Note 1 Output noise-spectral density f = 120 Hz Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω 25°C 48 −40°C to 125°C 44 25°C 45 −40°C to 125°C 44 25°C 95 CO = 10 µF 25°C 89 CO = 100 µF 25°C 74 PG hysteresis voltage§ Measured at VFB PG output low voltage§ IPG = 400 µA, A, VI = 2.13 V FB input current 1.101 12 25°C 0.1 −40°C to 125°C −40°C to 125°C −20 mV µVrms 0.1 V mV 0.4 0.4 −10 mV µV/√Hz 1.145 25°C 25°C mV dB 54 CO = 4.7 µF −40°C to 125°C Ω 59 2 VFB voltage decreasing from above VPG ppm/°C 0.85 25°C PG trip-threshold voltage§ V 1 25°C f = 120 Hz UNIT V VI = 2.9 V, IO = 50 µA A Ripple rejection TJ 10 20 V nA † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. § Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 27) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 2. To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on) rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. (For other programmed values, see Figure 26.) 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TPS71H33 electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE shorted to OUT (unless otherwise noted) TEST CONDITIONS‡ PARAMETER Output voltage TJ VI = 4.3 V, 4.3 V ≤ VI ≤ 10 V, IO = 10 mA 5 mA ≤ IO ≤ 500 mA −40°C to 125°C IO = 10 mA, VI = 3.23 V −40°C to 125°C MIN TPS71H33-Q1 TYP MAX 25°C 3.3 3.23 25°C IO = 100 mA, VI = 3.23 V −40°C to 125°C IO = 500 mA, VI = 3.23 V −40°C to 125°C Pass-element series resistance (3.23 V − VO)/IO, IO = 500 mA VI = 3.23 V, Input regulation VI = 4.3 V to 10 V, 50 µA A ≤ IO ≤ 500 mA IO = 5 mA to 500 mA, 4.3 V ≤ VI ≤ 10 V −40°C to 125°C A to 500 mA, IO = 50 µA 4.3 V ≤ VI ≤ 10 V −40°C to 125°C IO = 50 µA A 25°C 43 −40°C to 125°C 40 25°C 39 −40°C to 125°C 36 Ripple rejection IO = 500 mA Output noise-spectral density f = 120 Hz Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω PG trip-threshold voltage 60 0.47 0.6 0.8 25°C 20 −40°C to 125°C 27 25°C 21 25°C 30 mV mV 60 120 mV 54 dB 49 25°C 274 CO = 10 µF 25°C 228 CO = 100 µF 25°C 159 2.868 µV/√Hz µVrms 3 25°C 35 25°C 0.22 −40°C to 125°C Ω 38 75 CO = 4.7 µF VI = 2.8 V mV 300 −40°C to 125°C −40°C to 125°C V 400 2 VO voltage decreasing from above VPG IPG = 1 mA, 47 25°C PG hysteresis voltage PG output low voltage 7 235 25°C f = 120 Hz 4.5 80 25°C Output regulation 3.37 8 25°C Dropout voltage UNIT V mV 0.4 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TPS71H48 electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE shorted to OUT (unless otherwise noted) TEST CONDITIONS‡ PARAMETER Output voltage TJ VI = 5.85 V, 5.85 V ≤ VI ≤ 10 V, IO = 10 mA 5 mA ≤ IO ≤ 500 mA −40°C to 125°C IO = 10 mA, VI = 4.75 V −40°C to 125°C IO = 100 mA, VI = 4.75 V −40°C to 125°C IO = 500 mA, VI = 4.75 V −40°C to 125°C 25°C TPS71H48-Q1 MIN 25°C 4.75 30 VI = 4.75 V, Input regulation VI = 5.85 V to 10 V, 50 µA A ≤ IO ≤ 500 mA IO = 5 mA to 500 mA, 5.85 V ≤ VI ≤ 10 V A to 500 mA, IO = 50 µA 5.85 V ≤ VI ≤ 10 V −40°C to 125°C IO = 50 µA A 25°C 42 −40°C to 125°C 39 25°C 39 −40°C to 125°C 35 Output noise-spectral density f = 120 Hz Output noise voltage 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω PG trip-threshold voltage PG output low voltage 180 0.32 0.35 0.52 25°C 27 −40°C to 125°C 37 25°C 12 −40°C to 125°C 25°C 42 mV mV dB 50 25°C 410 CO = 10 µF 25°C 328 CO = 100 µF 25°C 212 4.5 µV/√Hz µVrms 4.7 25°C 50 25°C 0.2 −40°C to 125°C mV 53 CO = 4.7 µF VI = 4.12 V Ω 60 130 2 −40°C to 125°C mV 42 80 25°C VO voltage decreasing from above VPG IPG = 1.2 mA, 150 −40°C to 125°C PG hysteresis voltage 37 250 (4.75 V − VO)/IO, IO = 500 mA IO = 500 mA V 6 54 Pass-element series resistance f = 120 Hz UNIT 8 25°C Ripple rejection 4.95 2.9 25°C Output regulation MAX 4.85 25°C Dropout voltage TYP V mV 0.4 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TPS71H50 electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE shorted to OUT (unless otherwise noted) TEST CONDITIONS‡ PARAMETER Output voltage TJ VI = 6 V, 6 V ≤ VI ≤ 10 V, IO = 10 mA 5 mA ≤ IO ≤ 500 mA −40°C to 125°C IO = 10 mA, VI = 4.88 V −40°C to 125°C IO = 100 mA, VI = 4.88 V −40°C to 125°C IO = 500 mA, VI = 4.88 V −40°C to 125°C 25°C TPS71H50-Q1 MIN 25°C 4.9 27 VI = 4.88 V. Input regulation VI = 6 V to 10 V, 50 µA A ≤ IO ≤ 500 mA IO = 5 mA to 500 mA, 6 V ≤ VI ≤ 10 V A to 500 mA, IO = 50 µA 6 V ≤ VI ≤ 10 V −40°C to 125°C IO = 50 µA A 25°C 45 −40°C to 125°C 40 25°C 42 −40°C to 125°C 36 Output noise-spectral density Output noise voltage PG trip-threshold voltage 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω 0.29 0.32 0.47 25°C 25 −40°C to 125°C 32 25°C 30 −40°C to 125°C 25°C 45 mV mV dB 52 2 CO = 10 µF 25°C 345 CO = 100 µF 25°C 220 4.55 µV/√Hz µVrms 4.75 25°C 53 25°C 0.2 −40°C to 125°C mV 55 430 VI = 4.25 V Ω 65 140 25°C −40°C to 125°C mV 45 86 25°C VO voltage decreasing from above VPG IPG = 1.2 mA, 170 CO = 4.7 µF PG hysteresis voltage PG output low voltage 146 −40°C to 125°C f = 120 Hz 32 230 (4.88 V − VO)/IO, IO = 500 mA IO = 500 mA V 6 47 Pass-element series resistance f = 120 Hz UNIT 8 25°C Ripple rejection 5.1 2.9 25°C Output regulation MAX 5 25°C Dropout voltage TYP V mV 0.4 0.4 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Output current 5 vs Input voltage 6 IQ Quiescent current vs Free-air temperature 7 VDO ∆VDO Typical dropout voltage vs Output current 8 Change in dropout voltage vs Free-air temperature 9 ∆VO VO Change in output voltage vs Free-air temperature 10 Output voltage vs Input voltage 11 ∆VO Change in output voltage vs Input voltage 12 13 14 VO Output voltage vs Output current 15 16 17 18 Ripple rejection vs Frequency 19 20 21 22 Output spectral noise density vs Frequency rDS(on) Pass-element resistance vs Input voltage 25 R Divider resistance vs Free-air temperature 26 II(SENSE) SENSE current vs Free-air temperature 27 FB leakage current vs Free-air temperature 28 Minimum input voltage for active-pass element vs Free-air temperature 29 VI Minimum input voltage for valid PG vs Free-air temperature 30 II(EN) Input current (EN) vs Free-air temperature 31 23 24 Output voltage response from enable (EN) 32 VPG Power-good (PG) voltage vs Output voltage CSR Compensation series resistance vs Output current CSR Compensation series resistance vs Ceramic capacitance CSR Compensation series resistance vs Output current CSR Compensation series resistance vs Ceramic capacitance 33 34 35 36 37 38 39 40 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TYPICAL CHARACTERISTICS QUIESCENT CURRENT vs OUTPUT CURRENT QUIESCENT CURRENT vs INPUT VOLTAGE 355 400 345 350 335 TPS71Hxx, VI = 10 V I Q − Quiescent Current − µ A I Q − Quiescent Current − µ A TA = 25°C RL = 10 Ω TA = 25°C 325 315 305 295 TPS71H50, VI = 6 V 285 300 TPS71H33 TPS71H48 250 TPS71H50 200 TPS71H01 With VO Programmed to 2.5 V 150 100 TPS71H48, VI = 5.85 V 275 50 TPS71H33, VI = 4.3 V 265 0 50 100 150 200 250 300 350 400 450 500 0 0 1 2 3 IO − Output Current − mA 4 5 6 7 8 9 10 VI − Input Voltage − V Figure 5 Figure 6 TPS71H48 QUIESCENT CURRENT vs FREE-AIR TEMPERATURE DROPOUT VOLTAGE vs OUTPUT CURRENT 400 0.3 TA = 25°C 0.25 350 TPS71H33 Dropout Voltage − V I Q − Quiesent Current − µ A VI = VO(nom) + 1 V IO = 10 mA 300 250 0.2 0.15 TPS71H48 0.1 TPS71H50 200 150 −50 0.05 0 −25 0 25 50 75 100 125 0 50 100 150 200 250 300 350 400 450 500 TA − Free-Air Temperature − °C IO − Output Current − mA Figure 7 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TYPICAL CHARACTERISTICS CHANGE IN DROPOUT VOLTAGE vs FREE-AIR TEMPERATURE CHANGE IN OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 20 10 ∆ VO − Change in Output Voltage − mV 8 Change in Dropout Voltage − mV VI = VO(nom) + 1 V IO = 10 mA IO = 100 mA 6 4 2 0 −2 −4 −6 −8 −10 −50 −25 0 25 50 75 100 15 10 5 0 −5 −10 −15 −20 −50 125 −25 TA − Free-Air Temperature − °C 0 Figure 9 20 TA = 25°C RL = 10 Ω ∆VO− Change In Output Voltage − mV TPS71H50 VO − Output Voltage − V 5 TPS71H48 4 3 TPS71H33 TPS71H01 With VO Programmed to 2.5 V 1 0 1 2 3 4 5 100 125 6 7 8 9 10 TA = 25°C RL = 10 Ω 15 10 TPS71H50 5 TPS71H48 0 −5 TPS71H33 −10 −15 −20 4 VI − Input Voltage − V Figure 11 14 75 CHANGE IN OUTPUT VOLTAGE vs INPUT VOLTAGE 6 0 50 Figure 10 OUTPUT VOLTAGE vs INPUT VOLTAGE 2 25 TA − Free-Air Temperature − °C 5 6 7 8 VI − Input Voltage − V Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 10 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TYPICAL CHARACTERISTICS TPS71H33 TPS71H01 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 2.52 3.34 TA = 25°C VO Programmed to 2.5 V TA = 25°C 3.33 2.51 VO − Output Voltage − V VO − Output Voltage − V 2.515 2.505 2.5 VI = 3.5 V 2.495 VI = 10 V 3.32 3.31 3.28 2.485 3.27 0 100 200 400 300 VI = 4.3 V 3.29 2.49 2.48 VI = 10 V 3.3 3.26 500 0 100 IO − Output Current − mA 200 400 500 300 200 400 IO − Output Current − mA 500 Figure 13 Figure 14 TPS71H50 TPS71H48 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 5.06 4.92 5.05 TA = 25°C 4.9 5.04 4.89 5.03 VO − Output Voltage − V VO − Output Voltage − V 4.91 4.88 4.87 VI = 5.85 V 4.86 4.85 VI = 10 V 4.84 5.01 4.99 4.96 4.81 4.95 4.94 200 400 300 500 VI = 10 V 4.98 4.82 100 VI = 6 V 5 4.97 0 TA = 25°C 5.02 4.83 4.8 300 IO − Output Current − mA 0 IO − Output Current − mA Figure 15 100 Figure 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TPS71H01 TPS71H33 RIPPLE REJECTION vs FREQUENCY RIPPLE REJECTION vs FREQUENCY 70 70 60 60 40 30 20 10 0 10 RL = 500 Ω TA = 25°C VI = 3.5 V CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance VO Programmed to 2.5 V 40 30 1K RL = 10 Ω 10 0 10K 100K 1M RL = 500 Ω 20 RL = 10 Ω 100 RL = 100 kΩ 50 RL = 100 kΩ 50 Ripple Rejection − dB Ripple Rejection − dB TYPICAL CHARACTERISTICS TA = 25°C VI = 3.5 V CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance −10 10 10M 100 f − Frequency − Hz 1k 10 k Figure 17 TPS71H48 TPS71H50 RIPPLE REJECTION vs FREQUENCY RIPPLE REJECTION vs FREQUENCY Ripple Rejection − dB Ripple Rejection − dB RL = 100 kΩ RL = 10 Ω 30 RL = 500 Ω 20 −10 10 TA = 25°C VI = 3.5 V CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance 100 1k 10 k 40 1M 10 M 10 M RL = 10 Ω 30 RL = 500 Ω 20 10 100 k RL = 100 kΩ 50 TA = 25°C VI = 3.5 V CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance 0 10 f − Frequency − Hz 100 1k 10 k 100 k f − Frequency − Hz Figure 19 16 1M 60 50 0 10 M 70 60 10 1M Figure 18 70 40 100 k f − Frequency − Hz Figure 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TYPICAL CHARACTERISTICS TPS71H01 TPS71H33 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TA = 25°C No Input Capacitance VI = 3.5 V VO Programmed to 2.5 V CO = 4.7 µF (CSR = 1 Ω) 1 CO = 10 µF (CSR = 1 Ω) 0.1 10 Output Spectral Noise Density − µV/ Hz Output Spectral Noise Density − µV/ Hz 10 TA = 25°C No Input Capacitance VI = 4.3 V CO = 10 µF (CSR = 1 Ω) 1 CO = 4.7 µF (CSR = 1 Ω) CO = 100 µF (CSR = 1 Ω) 0.1 CO = 100 µF (CSR = 1 Ω) 0.01 10 102 103 104 f − Frequency − Hz 0.01 10 105 102 104 105 f − Frequency − Hz Figure 21 Figure 22 TPS71H48 TPS71H50 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 10 TA = 25°C No Input Capacitance VI = 5.85 V CO = 10 µF (CSR = 1 Ω) 1 CO = 4.7 µF (CSR = 1 Ω) 0.1 CO = 100 µF (CSR = 1 Ω) Output Spectral Noise Density − µV/ Hz Output Spectral Noise Density − µV/ Hz 103 CO = 10 µF (CSR = 1 Ω) CO = 4.7 µF (CSR = 1 Ω) 1 TA = 25°C No Input Capacitance VI = 6 V 0.1 CO = 100 µF (CSR = 1 Ω) 0.01 10 100 1k 10 k f − Frequency − Hz 100 k 0.01 10 Figure 23 100 1k 10 k f − Frequency − Hz 100 k Figure 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TYPICAL CHARACTERISTICS PASS-ELEMENT RESISTANCE vs INPUT VOLTAGE DIVIDER RESISTANCE vs FREE-AIR TEMPERATURE 1.2 TA = 25°C VI(FB) = 1.12 V 1 0.9 0.8 IO = 500 mA 0.7 0.6 0.5 VI = VO(nom) + 1 V VI(sense) = VO(nom) 1.1 R − Divider Resistance − M Ω rDS(on) − Pass-Element Resistance − Ω 1.1 IO = 100 mA 0.4 TPS71H50 1 TPS71H48 0.9 0.8 0.7 TPS71H33 0.6 0.3 0.5 0.2 0.1 3 2 4 6 8 5 7 VI − Input Voltage − V 9 0.4 −50 10 −25 0 25 50 75 100 TA − Free-Air Temperature − °C Figure 25 Figure 26 FIXED-OUTPUT VERSIONS SENSE PIN CURRENT vs FREE-AIR TEMPERATURE ADJUSTABLE VERSION FB LEAKAGE CURRENT vs FREE-AIR TEMPERATURE 6 0.6 VI = VO(nom) + 1 V VI(sense) = VO(nom) VFB = 2.5 V 0.5 5.6 FB Leakage Current − nA I I(sense) − Sense Pin Current − µ A 5.8 5.4 5.2 5 4.8 4.4 −50 0.4 0.3 0.2 0.1 4.6 −25 0 25 50 75 100 125 0 −50 TA − Free-Air Temperature − °C −25 0 25 Figure 28 POST OFFICE BOX 655303 50 75 100 TA − Free-Air Temperature − °C Figure 27 18 125 • DALLAS, TEXAS 75265 125 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TYPICAL CHARACTERISTICS MINIMUM INPUT VOLTAGE FOR ACTIVE PASS ELEMENT vs FREE-AIR TEMPERATURE MINIMUM INPUT VOLTAGE FOR VALID POWER GOOD (PG) vs FREE-AIR TEMPERATURE 1.1 2.1 VI − Minimum Input Voltage − V VI − Minimum Input Voltage − V 2.09 RL = 500 Ω 2.08 2.07 2.06 2.05 2.04 ÁÁ ÁÁ 1.08 1.07 ÁÁ ÁÁ 2.03 2.02 2.01 −25 0 25 50 75 100 TA − Free-Air Temperature − °C 1.06 1.05 −50 125 −25 0 25 50 75 100 125 TA − Free-Air Temperature − °C Figure 29 Figure 30 EN INPUT CURRENT vs FREE-AIR TEMPERATURE 100 90 VI = VI(EN) = 10 V 80 I I(EN) − Input Current − nA 2 −50 1.09 70 60 50 40 30 20 10 0 −40 −20 0 20 40 60 80 100 120 140 TA − Free-Air Temperature − °C Figure 31 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TYPICAL CHARACTERISTICS VO − Output Voltage − V OUTPUT VOLTAGE RESPONSE FROM ENABLE (EN) VO(nom) TA = 25°C RL = 500 Ω CO = 4.7 µF (ESR = 1Ω) No Input Capacitance 4 2 0 −2 0 20 40 60 80 100 120 140 Time − µs Figure 32 POWER-GOOD (PG) VOLTAGE vs OUTPUT VOLTAGE 6 VPG − Power-Good (PG) Voltage − V TA = 25°C PG Pulled Up to 5 V With 5 kΩ 5 4 3 ÁÁ ÁÁ 2 1 0 93 94 95 96 97 98 VO − Output Voltage (VO as a percent of VO(nom)) − % Figure 33 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 EN Voltage − V 6 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TYPICAL CHARACTERISTICS TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE vs OUTPUT CURRENT 100 VI = VO(nom) + 1 V No Input Capacitance CO = 4.7 µF No Added Ceramic Capacitance TA = 25°C CSR − Compensation Series Resistance − Ω CSR − Compensation Series Resistance − Ω 100 TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE vs OUTPUT CURRENT Region of Instability 10 1 Region of Instability 0.1 0 VI = VO(nom) + 1 V No Input Capacitance CO = 4.7 µF + 0.5 µF of Ceramic Capacitance TA = 25°C 10 Region of Instability 1 Region of Instability 0.1 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 IO − Output Current − mA IO − Output Current − mA Figure 34 Figure 35 TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE vs ADDED CERAMIC CAPACITANCE COMPENSATION SERIES RESISTANCE vs ADDED CERAMIC CAPACITANCE 100 VI = VO(nom) + 1 V No Input Capacitance IO= 100 mA CO = 4.7 µF TA = 25°C 10 CSR − Compensation Series Resistance − Ω CSR − Compensation Series Resistance − Ω 100 Region of Instability 1 Region of Instability 0.1 VI = VO(nom) + 1 V No Input Capacitance IO= 500 mA CO = 4.7 µF TA = 25°C 10 Region of Instability 1 Region of Instability 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Ceramic Capacitance − µF Ceramic Capacitance − µF Figure 36 Figure 37 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TYPICAL CHARACTERISTICS TYPICAL REGIONS OF STABILITY† TYPICAL REGIONS OF STABILITY† COMPENSATION SERIES RESISTANCE vs OUTPUT CURRENT COMPENSATION SERIES RESISTANCE vs OUTPUT CURRENT Region of Instability 100 VI = VO(nom) + 1 V No Input Capacitance CO = 10 µF No Ceramic Capacitance TA = 25°C CSR − Compensation Series Resistance − Ω CSR − Compensation Series Resistance − Ω 100 10 1 0.1 VI = VO(nom) + 1 V No Input Capacitance CO = 10 µF + 0.5 µF of Added Ceramic Capacitance TA = 25°C 10 Region of Instability 1 0.1 0 0 50 100 150 200 250 300 350 400 450 500 50 100 150 200 250 300 350 400 450 500 IO − Output Current − mA IO − Output Current − mA Figure 38 TYPICAL REGIONS OF STABILITY† TYPICAL REGIONS OF STABILITY† COMPENSATION SERIES RESISTANCE vs ADDED CERAMIC CAPACITANCE COMPENSATION SERIES RESISTANCE vs ADDED CERAMIC CAPACITANCE 100 VI = VO(nom) + 1 V No Input Capacitance CO = 10 µF IO = 100 mA TA = 25°C CSR − Compensation Series Resistance − Ω CSR − Compensation Series Resistance − Ω 100 Figure 39 10 Region of Instability 1 0.1 VI = VO(nom) + 1 V No Input Capacitance CO = 10 µF IO = 500 mA TA = 25°C 10 Region of Instability 1 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Ceramic Capacitance − µF Ceramic Capacitance − µF Figure 40 Figure 41 † CSR values below 0.1 Ω are not recommended. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 TYPICAL CHARACTERISTICS VI To Load IN OUT SENSE EN + CO GND Ccer† RL CSR † Ceramic capacitor Figure 42. Test Circuit for Typical Regions of Stability (see Figures 34 through 41) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 THERMAL INFORMATION standard TSSOP-20 In response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitch surface-mount packages. Implementation of many of today’s high-performance devices in these packages requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are illustrated in this discussion: D Improving the power-dissipation capability of the PWB design D Improving the thermal coupling of the component to the PWB D Introducing airflow in the system Figure 43 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout involves adding copper on the PWB to conduct heat away from the device. The RθJA for this component/ board system is illustrated in Figure 44. The family of curves illustrates the effect of increasing the size of the copper-heat-sink surface area. The PWB is a standard FR4 board (L × W × H = 3.2 inch × 3.2 inch × 0.062 inch); the board traces and heat sink area are 1-oz (per square foot) copper. Copper Heat Sink 1 oz Copper Figure 43. Thermally Enhanced PWB Layout (not to scale) for the 20-Pin TSSOP Figure 45 shows the thermal resistance for the same system with the addition of a thermally conductive compound between the body of the TSSOP package and the PWB copper routed directly beneath the device. The thermal conductivity for the compound used in this analysis is 0.815 W/m × °C. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 THERMAL INFORMATION THERMAL RESISTANCE, JUNCTION-TO-AMBIENT vs AIR FLOW 190 Component /Board System 20-Lead TSSOP 0 cm2 170 1 cm2 150 2 cm2 130 110 90 4 cm2 8 cm2 70 50 0 50 100 150 200 Air Flow − ft /min 250 300 THERMAL RESISTANCE, JUNCTION-TO-AMBIENT vs AIR FLOW RθJA − Thermal Resistance, Junction-to-Ambient − °C/W RθJA − Thermal Resistance, Junction-to-Ambient − °C/W standard TSSOP-20 (continued) 190 Component /Board System 20-Lead TSSOP Includes Thermally Conductive Compound Between Body and Board 170 150 0 cm2 130 8 cm2 110 4 cm2 2 cm2 90 1 cm2 70 50 0 Figure 44 50 100 150 200 Air Flow − ft /min 250 300 Figure 45 Using these figures to determine the system RθJA allows the maximum power-dissipation limit to be calculated with the equation: *T J(max) A R qJA(system) T P D(max) + Where TJ(max) is the maximum allowable junction temperature (i.e., 150°C absolute maximum and 125°C maximum recommended operating temperature for specified operation). This limit should then be applied to the internal power dissipated by the TPS71Hxx regulator. The equation for calculating total internal power dissipation of the TPS71Hxx is: P D(total) ǒ Ǔ @ IO ) VI @ IQ + V *V I O Because the quiescent current of the TPS71Hxx family is very low, the second term is negligible, further simplifying the equation to: P D(total) ǒ Ǔ @ IO + V *V I O POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 THERMAL INFORMATION standard TSSOP-20 (continued) For a 20-lead TSSOP / FR4 board system with thermally conductive compound between the board and the device body, where TA = 55°C, airflow = 100 ft /min, copper heat sink area = 1 cm2, the maximum power-dissipation limit can be calculated. As indicated in Figure 45, the system RθJA is 94°C/W; therefore, the maximum power-dissipation limit is: *T J(max) A ° ° + 125 C * 55 C + 745 mW ° R 94 Cń W qJA(system) T P D(max) + If the system implements a TPS71H48 regulator where VI = 6 V and IO = 385 mA, the internal power dissipation is: P D(total) ǒ Ǔ @ IO + (6 * 4.85) @ 0.385 + 443 mW + V *V I O Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the maximum limit. When it does, one of two corrective actions can be taken. The power-dissipation limit can be raised by increasing the airflow or the heat-sink area. Alternatively, the internal power dissipation of the regulator can be lowered by reducing the input voltage or the load current. In either case, the above calculations should be repeated with the new system parameters. thermally enhanced TSSOP-20 The thermally enhanced PWP package is based on the 20-pin TSSOP, but includes a thermal pad [see Figure 46(c)] to provide an effective thermal contact between the IC and the PWB. Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO220-type packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages, however, suffer from several shortcomings: they do not address the very low profile requirements (< 2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough to accommodate increasing integration. On the other hand, traditional low-power surface-mount packages require power-dissipation derating that severely limits the usable range of many high-performance analog circuits. The PWP package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal performance comparable to much larger power packages. The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending) and manufacturing technique to provide the user with direct connection to the heat-generating IC. When this pad is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultrathin, fine-pitch, surface-mount package can be reliably achieved. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 THERMAL INFORMATION thermally enhanced TSSOP-20 (continued) DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) Figure 46. Views of Thermally Enhanced PWP Package Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface), which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference Figure 48(a), 8 cm2 of copper heat sink and natural convection). Increasing the heat-sink size increases the power dissipation range for the component. The power dissipation limit can be further improved by adding airflow to a PWB/IC assembly (see Figures 47 and 48). The line drawn at 0.3 cm2 in Figures 47 and 48 indicates performance at the minimum recommended heat-sink size, illustrated in Figure 50. The thermal pad is directly connected to the substrate of the IC, which for the TPS71HxxQPWP series is a secondary electrical connection to device ground. The heat-sink surface that is added to the PWB can be a ground plane or left electrically isolated. In other TO220-type surface-mount packages, the thermal connection is also the primary electrical connection for a given terminal which is not always ground. The PWP package provides up to 12 independent leads that can be used as inputs and outputs (Note: leads 1, 2, 9, 10, 11, 12, 19, and 20 are internally connected to the thermal pad and the IC substrate). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 THERMAL INFORMATION thermally enhanced TSSOP-20 (continued) THERMAL RESISTANCE vs COPPER HEAT-SINK AREA 150 R θ JA − Thermal Resistance − ° C/W 125 Natural Convection 50 ft/min 100 ft/min 100 150 ft/min 200 ft/min 75 50 250 ft/min 300 ft/min 25 0 0.3 1 2 3 4 5 Copper Heat-Sink Area − cm2 Figure 47 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 7 8 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 THERMAL INFORMATION thermally enhanced TSSOP-20 (continued) 3.5 3.5 TA = 55°C 300 ft/min PD − Power Dissipation Limit − W 3 150 ft/min 2.5 2 Natural Convection 1.5 1 0.5 0 3 300 ft/min 2.5 2 150 ft/min 1.5 Natural Convection 1 0.5 0 0.3 2 4 0 8 6 Copper Heat-Sink Size − cm2 0 0.3 2 4 6 8 Copper Heat-Sink Size − cm2 (a) (b) 3.5 TA = 105°C 3 PD − Power Dissipation Limit − W PD − Power Dissipation Limit − W TA = 25°C 2.5 2 1.5 150 ft/min 300 ft/min 1 Natural Convection 0.5 0 0 0.3 2 4 6 8 Copper Heat-Sink Size − cm2 (c) Figure 48. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 THERMAL INFORMATION thermally enhanced TSSOP-20 (continued) Figure 49 is an example of a thermally enhanced PWB layout for use with the new PWP package. This board configuration was used in the thermal experiments that generated the power ratings shown in Figures 47 and 48. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. RθJA for this assembly is illustrated in Figure 47 as a function of heat-sink area. A family of curves is included to illustrate the effect of airflow introduced into the system. Heat-Sink Area 1 oz Copper Board thickness Board size Board material Copper trace/heat sink Exposed pad mounting 62 mils 3.2 in. × 3.2 in. FR4 1 oz 63/67 tin/lead solder Figure 49. PWB Layout (Including Copper Heatsink Area) for Thermally Enhanced PWP Package From Figure 47, RθJA for a PWB assembly can be determined and used to calculate the maximum power-dissipation limit for the component/PWB assembly, with the equation: P D(max) + T max * T J A R qJA(system) Where TJmax is the maximum specified junction temperature (150°C absolute maximum limit, 125°C recommended operating limit) and TA is the ambient temperature. PD(max) should then be applied to the internal power dissipated by the TPS71H33QPWP regulator. The equation for calculating total internal power dissipation of the TPS71H33QPWP is: P D(total) ǒ Ǔ + V *V I O I O )V I I Q Since the quiescent current of the TPS71H33QPWP is very low, the second term is negligible, further simplifying the equation to: P D(total) ǒ Ǔ + V *V I O I O For the case where TA = 55°C, airflow = 200 ft /min, copper heat-sink area = 4 cm2, the maximum power-dissipation limit can be calculated. First, from Figure 47, we find the system RθJA is 50°C/W; therefore, the maximum power-dissipation limit is: P 30 D(max) + T max * T ° J A + 125 °C * 55 C + 1.4 W ° R 50 CńW qJA(system) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 THERMAL INFORMATION thermally enhanced TSSOP-20 (continued) If the system implements a TPS71H33QPWP regulator, where VI = 6 V and IO = 500 mA, the internal power dissipation is: P D(total) ǒ Ǔ + V *V I O I O + (6 * 3.3) 0.5 + 1.35 W Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the calculated limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing the input voltage or the load current. In either case, the above calculations should be repeated with the new system parameters. mounting information Since the thermal pad is not a primary connection for an electrical signal, the importance of the electrical connection is not significant. The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted. Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The data included in Figures 47 and 48 is for soldered connections with voiding between 20% and 50%. The thermal analysis shows no significant difference resulting from the variation in voiding percentage. Figure 50 shows the solder-mask land pattern for the PWP package. The minimum recommended heat-sink area is also illustrated. This is simply a copper plane under the body extent of the package, including metal routed under terminals 1, 2, 9, 10, 11, 12, 19, and 20. Minimum Recommended Heat-Sink Area Location of Exposed Thermal Pad on PWP Package 0.27 mm 1.2 mm reliability information This section includes demonstrated reliability test results obtained from the qualification program. Accelerated tests are performed at high-stress conditions so that product reliability can be established during a relatively short test duration. Specific stress conditions are chosen to represent accelerated versions of various deviceapplication environments and allow meaningful extrapolation to normal operating conditions. component level reliability test results 0.65 mm 5.72 mm Figure 50. PWP Package Land Pattern preconditioning Preconditioning of components prior to reliability testing is employed to simulate the actual board assembly process used by the customer. This ensures that reliability test results are more representative of those that would be seen in the final application. The general form of the preconditioning sequence includes a moisture soak followed by multiple vapor-phase-reflow or infrared-reflow solder exposures. All components used in the following reliability tests were preconditioned in accordance with JEDEC Test Method A113 for Level 1 (not moisture-sensitive) products. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 THERMAL INFORMATION high-temperature life test High-temperature life testing is used to demonstrate long-term reliability of the product under bias. The potential failure mechanisms evaluated with this stress are those associated with dielectric integrity and design or process sensitivity to mobile-ion phenomena. Components are tested at an elevated ambient temperature of 155°C for an extended period. Results are derated using the Arrhenius equation to an equivalent number of unit hours at a representative application temperature. The corresponding predicted failure rate is expressed in FITs, or failures per billion device-hours. The failure rate shown in this case is data-limited since no actual failures were experienced during qualification testing. PREDICTED LONG-TERM FAILURE RATE Number of Units Equivalent Unit Hours at 55°C and 0.7 eV FITs at 50% CL 325 24,468,090 36.2 biased humidity test Biased humidity testing is used to evaluate the effects of moisture penetration on plastic-encapsulated devices under bias. This stress verifies the integrity of the package construction and the die passivation system. The primary potential failure mechanism is electrolytic corrosion. Components are biased in a low power state to reduce heat dissipation and are subjected to a 120°C, 85%-relative-humidity environment for 100 hours. BIASED HUMIDITY TEST RESULTS Equivalent Unit Hours at 85°C and 85% RH Failures 357,000 0 autoclave test The autoclave stress is used to assess the capabilities of the die and package construction materials with respect to moisture ingress and extended exposure. Predominant failure mechanisms include leakage currents that result from internal moisture accumulation and galvanic corrosion resulting from reactions with any present ionic contaminants. Components are subjected to a 121°C, 15 PSIG, 100%-relative-humidity environment for 240 hours. AUTOCLAVE TEST RESULTS Total Unit Hours Failures 54,720 0 thermal shock test Thermal shock testing is used to evaluate the capability of the component to withstand mechanical stress resulting from differences in thermal coefficients of expansion among the die and package construction materials. Failure mechanisms are typically related to physical damage at interface locations between different materials. Components are cycled between −65°C and 150°C in liquid mediums for a total duration of 1000 cycles. THERMAL SHOCK TEST RESULTS 32 Total Unit Cycles Failures 345,000 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 THERMAL INFORMATION PWB assembly level reliability results temperature cycle test Temperature cycle testing of the PWB assembly is used to evaluate the capability of the assembly to withstand mechanical stress resulting from the differences in thermal coefficients of expansion among die, package, and PWB board materials. This testing is also used to sufficiently age the soldered thermal connection between the thermal pad and the Cu trace on the FR4 board and evaluate the degradation of the thermal resistance for a board-mounted test unit. The assemblies were cycled between temperature extremes of −40°C and 125°C for a total duration of 730 cycles. TEMPERATURE CYCLE TEST RESULTS Total Unit Cycles Failures Average Change in RθJA(system) 36,500 0 −0.41% solderability test Solderability testing is used to simulate actual board-mount performance in a reflow process. Solderability testing is conducted as follows: The test devices are first steam-aged for 8 hours. A stencil is used to apply a solder-paste terminal pattern on a ceramic substrate (nominal stencil thickness is 0.005 inch). The test units are manually placed on the solder-paste footprint with proper implements to avoid contamination. The ceramic substrate and components are subjected to the IR reflow process as follows: IR REFLOW PROCESS Temperature Time PREHEAT SOAK REFLOW 150°C to 170°C 215°C to 230°C 60 sec 60 sec After cooling to room temperature, the component is removed from the ceramic substrate and the component terminals are subjected to visual inspection at 10X magnification. Test results are acceptable if all terminations exhibit a continuous solder coating free of defects for a minimum 95% of the critical surface area of any individual termination. Causes for rejection include: dewetting, nonwetting, and pin holes. The component leads and the exposed thermal pad were evaluated against this criteria. SOLDERABILITY TEST RESULTS Number of Test Units Failures 22 0 X-ray test X-ray testing is used to examine and quantify the voiding of the soldered attachment between the thermal pad and the PWB copper trace. Voiding between 20% and 50% was observed on a 49-piece sample. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 APPLICATION INFORMATION The TPS71Hxx series of low-dropout (LDO) regulators is designed to overcome many of the shortcomings of earlier-generation LDOs, while adding features such as a power-saving shutdown mode and a power-good indicator. The TPS71Hxx family includes three fixed-output voltage regulators: the TPS71H33 (3.3 V), the TPS71H48 (4.85 V), and the TPS71H50 (5 V). The family also offers an adjustable device, the TPS71H01 (adjustable from 1.2 V to 9.75 V). device operation The TPS71Hxx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/β). Close examination of the data sheets reveals that those devices are typically specified under near no-load conditions; actual operating currents are much higher as evidenced by typical quiescent current versus load current curves. The TPS71Hxx uses a PMOS transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low and invariable over the full load range. The TPS71Hxx specifications reflect actual performance under load. Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in β forces an increase in IB to maintain the load. During power up, this translates to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS71Hxx quiescent current remains low even when the regulator drops out, eliminating both problems. Included in the TPS71Hxx family is a 4.85-V regulator, the TPS71H48. Designed specifically for 5-V cellular systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack before the device drops out, adding crucial talk minutes between charges. The TPS71Hxx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 µA. If the shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated output voltage is reestablished in typically 120 µs. minimum load requirements The TPS71Hxx family is stable even at zero load; no minimum load is required for operation. SENSE-pin connection The SENSE pin of fixed-output devices must be connected to the regulator output for proper functioning of the regulator. Normally, this connection should be as short as possible; however, the connection can be made near a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. Routing the SENSE connection to minimize/avoid noise pickup is essential. Adding an RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator to oscillate. 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 APPLICATION INFORMATION external capacitor requirements An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load transient response and noise rejection if the TPS71Hxx is located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. As with most LDO regulators, the TPS71Hxx family requires an output capacitor for stability. A low-ESR 10-µF solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the full load range (see Figure 51). Adding high-frequency ceramic or film capacitors (such as power-supply bypass capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum capacitor is less than 1.2 Ω over temperature. Capacitors with published ESR specifications such as the AVX TPSD106K035R0300 and the Sprague 593D106X0035D2W work well because the maximum ESR at 25°C is 300 mΩ (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the temperature drops from 25°C to − 40°C). Where component height and/or mounting area is a problem, physically smaller, 10-µF devices can be screened for ESR. Figures 34 through 41 show the stable regions of operation using different values of output capacitance with various values of ceramic load capacitance. In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be reduced to 4.7 µF, provided ESR is maintained between 0.7 and 2.5 Ω. Because minimum capacitor ESR is seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series with the capacitor and limit ESR to 1.5 Ω maximum. As shown in the ESR graphs (Figures 34 through 41), minimum ESR is not a problem when using 10-µF or larger output capacitors. The following is a partial listing of surface-mount capacitors usable with the TPS71Hxx family. This information (along with the ESR graphs, Figures 34 through 41) is included to assist in selection of suitable capacitance for the user’s application. When necessary to achieve low height requirements along with high output current and/or high ceramic load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 APPLICATION INFORMATION external capacitor requirements (continued) All load and temperature conditions with up to 1 µF of added ceramic load capacitance: PART NO. MFR. VALUE MAX ESR† SIZE (H × L × W)† T421C226M010AS Kemet 22 µF, 10 V 0.5 2.8 × 6 × 3.2 593D156X0025D2W Sprague 15 µF, 25 V 0.3 2.8 × 7.3 × 4.3 593D106X0035D2W Sprague 10 µF, 35 V 0.3 2.8 × 7.3 × 4.3 10 µF, 35 V 0.3 2.8 × 7.3 × 4.3 TPSD106M035R0300 AVX Load < 200 mA, ceramic load capacitance < 0.2 µF, full temperature range: SIZE (H × L × W)† MFR. VALUE MAX ESR† 592D156X0020R2T Sprague 15 µF, 20 V 1.1 1.2 × 7.2 × 6 595D156X0025C2T Sprague 15 µF, 25 V 1 2.5 × 7.1 × 3.2 595D106X0025C2T Sprague 10 µF, 25 V 1.2 2.5 × 7.1 × 3.2 293D226X0016D2W Sprague 22 µF, 16 V 1.1 2.8 × 7.3 × 4.3 PART NO. Load < 100 mA, ceramic load capacitance < 0.2 µF, full temperature range: SIZE (H × L × W)† MFR. VALUE MAX ESR† 195D106X06R3V2T Sprague 10 µF, 6.3 V 1.5 1.3 × 3.5 × 2.7 195D106X0016X2T Sprague 10 µF, 16 V 1.5 1.3 × 7 × 2.7 595D156X0016B2T Sprague 15 µF, 16 V 1.8 1.6 × 3.8 × 2.6 695D226X0015F2T Sprague 22 µF, 15 V 1.4 1.8 × 6.5 × 3.4 695D156X0020F2T Sprague 15 µF, 20 V 1.5 1.8 × 6.5 × 3.4 695D106X0035G2T Sprague 10 µF, 35 V 1.3 2.5 × 7.6 × 2.5 PART NO. † Size is in mm. ESR is maximum resistance at 100 kHz and TA = 25°C. Listings are sorted by height. TPS71Hxx† VI 6 7 C1 0.1 µF 50 V IN PG IN SENSE OUT 5 EN OUT GND 3 16 PG 15 250 kΩ 14 VO 13 + CO 10 µF CSR † TPS71H33, TPS71H48, TPS71H50 (fixed-voltage options) Figure 51. Typical Application Circuit 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 APPLICATION INFORMATION programming the TPS71H01 adjustable LDO regulator Programming the adjustable regulators is accomplished using an external resistor divider as shown in Figure 52. The equation governing the output voltage is: V O +V ǒ1 ) R1 Ǔ R2 ref where Vref = reference voltage, 1.178 V typ Resistors R1 and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2 is 169 kΩ with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at FB will introduce an error. Solving equation 1 for R1 yields a more useful equation for choosing the appropriate resistance: R1 + ǒ V V Ǔ O *1 ref R2 OUTPUT VOLTAGE PROGRAMMING GUIDE TPS71H01 VI PG IN 0.1 µF >2.7 V Power-Good Indicator 250 kΩ OUT EN VO <0.5V R1 + FB GND R2 OUTPUT VOLTAGE R1 R2 UNIT 2.5 V 191 169 kΩ 3.3 V 309 169 kΩ 3.6 V 348 169 kΩ 4V 402 169 kΩ 5V 549 169 kΩ 6.4 V 750 169 kΩ Figure 52. TPS71H01 Adjustable LDO Regulator Programming power-good indicator The TPS71Hxx features a power-good (PG) output that can be used to monitor the status of the regulator. The internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or as a low-battery indicator. PG does not assert itself when the regulated output voltage falls outside the specified 2% tolerance, but instead reports an output voltage low, relative to its nominal regulated value. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 SGLS220A − DECEMBER 2003 − REVISED MAY 2008 APPLICATION INFORMATION regulator protection The TPS71Hxx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS71Hxx also features internal current limiting and thermal protection. During normal operation, the TPS71Hxx limits output current to approximately 1 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator operation resumes. 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2012 PACKAGING INFORMATION Orderable Device TPS71H33QPWPRQ1 Status (1) ACTIVE Package Type Package Drawing HTSSOP PWP Pins Package Qty Eco Plan 20 TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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