SGLS009B − MARCH 2003 − REVISED APRIL 2008
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
D
D
D
D
D
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
1−A Low-Dropout (LDO) Voltage Regulator
Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V,
3-V, 3.3-V, 5-V Fixed-Output and Adjustable
Versions
Dropout Voltage Down to 230 mV at 1 A
(TPS76750)
Ultralow 85-µA Typical Quiescent Current
Fast Transient Response
description
These devices are designed to have a fast transient
response and be stable with 10-µF low ESR
capacitors. This combination provides high
performance at a reasonable cost.
D 2% Tolerance Over Specified Conditions for
D
D
D
Fixed-Output Versions
Open Drain Power-On Reset With 200-ms
Delay (See TPS768xx for PG Option)
20-Pin TSSOP PowerPAD (PWP) Package
Thermal Shutdown Protection
PWP PACKAGE
(TOP VIEW)
GND/HSINK
GND/HSINK
GND
NC
EN
IN
IN
NC
GND/HSINK
GND/HSINK
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
GND/HSINK
GND/HSINK
NC
NC
RESET
FB/NC
OUT
OUT
GND/HSINK
GND/HSINK
NC − No internal connection
Because the PMOS device behaves as a low-value
resistor, the dropout voltage is very low (typically 230
mV at an output current of 1 A for the TPS76750) and
is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven
device, the quiescent current is very low and independent of output loading (typically 85 µA over the full range
of output current, 0 mA to 1 A). These two key specifications yield a significant improvement in operating life
for battery-powered systems. This low-dropout (LDO) family also features a sleep mode; applying a TTL high
signal to the enable (EN) input shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C.
The RESET output of the TPS767xx initiates a reset in microcomputer and microprocessor systems in the event
of an undervoltage condition. An internal comparator in the TPS767xx monitors the output voltage of the
regulator to detect an undervoltage condition on the regulated output voltage.
The TPS767xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3-V, 3.3-V, and 5-V fixed-voltage versions and in
an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified
as a maximum of 2% over line, load, and temperature ranges. The TPS767xx family is available in a 20-pin PWP
package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright 2008, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
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1
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TPS76733
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
TPS76733
LOAD TRANSIENT RESPONSE
103
∆ VO − Change in
Output Voltage − mV
100
102
101
I O − Output Current − A
VDO − Dropout Voltage − mV
IO = 1 A
IO = 10 mA
100
10−1
IO = 0
Co = 10 µF
10−2
−60 −40 −20
0
20
40
60
Co = 10 µF
TA = 25°C
50
0
−50
−100
1
0.5
0
80 100 120 140
0
TA − Free-Air Temperature − °C
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
AVAILABLE OPTIONS†
TJ
OUTPUT
VOLTAGE
(V)
TSSOP
(PWP)‡
TYP
5
TPS76750QPWPRQ1
3.3
2.8
TPS76733QPWPRQ1
TPS76730QPWPRQ1§
TPS76728QPWPRQ1§
2.7
TPS76727QPWPRQ1§
2.5
TPS76725QPWPRQ1
1.8
TPS76718QPWPRQ1
1.5
TPS76715QPWPRQ1
Adjustable
1.5 V to 5.5 V
TPS76701QPWPRQ1
3
−40°C to 125°C
† For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see
the TI web site at www.ti.com.
‡ Available taped and reeled in quantities of 2000 per reel
§ This devices is product preview.
2
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TPS767xx
6
VI
IN
RESET
16
RESET
7
IN
OUT
5
0.1 µF
EN
OUT
14
VO
13
+
GND
Co†
10 µF
3
† See application information section for capacitor selection details.
Figure 1. Typical Application Configuration (for Fixed Output Options)
functional block diagram—adjustable version
IN
EN
RESET
_
+
OUT
+
_
200 ms Delay
Vref = 1.1834 V
R1
FB/NC
R2
GND
External to the device
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SGLS009B − MARCH 2003 − REVISED APRIL 2008
functional block diagram—fixed-voltage version
IN
EN
RESET
_
+
OUT
+
_
200 ms Delay
R1
Vref = 1.1834 V
R2
GND
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
EN
5
I
Enable
FB/NC
15
I
Feedback voltage for adjustable device (no connect for fixed options)
GND
GND/HSINK
3
Regulator ground
1, 2, 9, 10, 11,
12, 19, 20
Ground/heatsink
IN
6, 7
NC
4, 8, 17, 18
OUT
RESET
4
I
Input voltage
No connect
13, 14
O
Regulated output voltage
16
O
Reset
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SGLS009B − MARCH 2003 − REVISED APRIL 2008
timing diagram
VI
Vres†
Vres
t
VO
VIT +‡
VIT +‡
Threshold
Voltage
VIT −‡
Less than 5% of the
output voltage
VIT −‡
t
RESET
Output
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
200 ms
Delay
200 ms
Delay
Output
Undefined
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Output
Undefined
t
† Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor
symbology.
‡ VIT −Trip voltage is typically 5% lower than the output voltage (95%VO) VIT− to VIT+ is the hysteresis voltage.
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SGLS009B − MARCH 2003 − REVISED APRIL 2008
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Ĕ
Input voltage range‡, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 13.5 V
Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VI + 0.3 V
Maximum RESET voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Output voltage, VO (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating tables
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
ESD rating, Human-Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE − FREE-AIR TEMPERATURES
PACKAGE
AIR FLOW
(CFM)
PWP§
PWP¶
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
0
2.9 W
23.5 mW/°C
1.9 W
1.5 W
300
4.3 W
34.6 mW/°C
2.8 W
2.2 W
0
3W
23.8 mW/°C
1.9 W
1.5 W
300
7.2 W
57.9 mW/°C
4.6 W
3.8 W
§ This parameter is measured with the recommended copper heat-sink pattern on a 1-layer PCB, 5-in × 5-in PCB, 1-oz copper,
2-in × 2-in coverage (4 in2).
¶ This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5-in × 2-in PCB, 1-oz copper
with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more information, refer
to TI technical brief SLMA002.
recommended operating conditions
MIN
MAX
UNIT
Input voltage, VI#
2.7
10
V
Output voltage range, VO
1.5
5.5
V
0
1.0
A
Output current, IO (see Note 1)
Operating virtual junction temperature, TJ (see Note 1)
−40
125
°C
# To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the
device operate under conditions beyond those specified in this table for extended periods of time.
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electrical characteristics over recommended operating free-air temperature range,
VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TPS76701
Output voltage (10 µA to 1 A load)
(see Note 2)
1.5 V ≤ VO ≤ 5.5 V,
MIN
TJ = 25°C
TJ = −40°C to 125°C
1.5 V ≤ VO ≤ 5.5 V,
TPS76715
TJ = 25°C,
TJ = −40°C to 125°C,
2.7 V < VIN < 10 V
TPS76718
TJ = 25°C,
TJ = −40°C to 125°C,
2.8 V < VIN < 10 V
TPS76725
TJ = 25°C,
TJ = −40°C to 125°C,
3.5 V < VIN < 10 V
TPS76727
TJ = 25°C,
TJ = −40°C to 125°C,
TPS76728
TJ = 25°C,
TJ = −40°C to 125°C,
3.8 V < VIN < 10 V
TPS76730
TJ = 25°C,
TJ = −40°C to 125°C,
4.0 V < VIN < 10 V
TPS76733
TJ = 25°C,
TJ = −40°C to 125°C,
4.3 V < VIN < 10 V
TPS76750
TJ = 25°C,
TJ = −40°C to 125°C,
1.8
2.856
3.0
2.940
3.060
3.3
4.3 V < VIN < 10 V
6.0 V < VIN < 10 V
3.234
6.0 V < VIN < 10 V
4.900
3.366
5.0
TJ = 25°C
TJ = −40°C to 125°C
5.100
85
125
%/V
3
mV
55
µVrms
2
Standby current
TPS76701
EN = VI,
TJ = −40°C to 125°C
2.7 V < VI < 10 V
1
A
µA
10
FB = 1.5 V
2
High-level enable input voltage
nA
1.7
Low-level enable input voltage
V
0.9
f = 1 KHz,
Co = 10 µF,
Power-supply ripple rejection (see Note 2)
60
TJ = 25°C
NOTES: 2. Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage 10 V.
3. If VO ≤ 1.8 V then VImax = 10 V, VImin = 2.7 V:
Line Regulation (mV) + ǒ%ńVǓ
V
O
ǒVImax * 2.7 VǓ
100
If VO ≥ 2.5 V then VImax = 10 V, VImin = VO + 1 V:
V
Line Regulation (mV) + ǒ%ńVǓ
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V
dB
1000
ǒVImax * ǒVO ) 1 VǓǓ
100
A
°C
150
TJ = 25°C,
2.7 V < VI < 10 V
A
µA
0.01
1.7
Thermal shutdown junction temperature
EN = VI,
V
2.8
Load regulation
FB input current
2.754
2.744
4.0 V < VIN < 10 V
VO = 0 V
2.550
2.7
3.8 V < VIN < 10 V
Output current limit
1.836
2.5
2.646
Output noise voltage (TPS76718)
1.530
1.764
3.7 V < VIN < 10 V
BW = 200 Hz to 100 kHz, IC = 1 A,
Co = 10 µF,
TJ = 25°C
1.02VO
1.470
2.450
VO + 1 V < VI ≤ 10 V, TJ = 25°C
UNIT
1.5
3.5 V < VIN < 10 V
3.7 V < VIN < 10 V
Output voltage line regulation (∆VO/VO)
(see Notes 2 and 3)
IO = 1 A,
0.98VO
2.8 V < VIN < 10 V
10 µA < IO < 1 A,
MAX
VO
2.7 V < VIN < 10 V
Quiescent current (GND current)
EN = 0V, (see Note 2)
TYP
1000
7
SGLS009B − MARCH 2003 − REVISED APRIL 2008
electrical characteristics over recommended operating free-air temperature
VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 µF (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
Trip threshold voltage
IO(RESET) = 300 µA
VO decreasing
Hysteresis voltage
Measured at VO
Output low voltage
VI = 2.7 V,
V(RESET) = 5 V
Minimum input voltage for valid RESET
Reset
Leakage current
MIN
TYP
range,
MAX
UNIT
1.1
92
V
98
%VO
%VO
0.4
V
0.5
IO(RESET) = 1 mA
0.15
µA
1
RESET time-out delay
200
Input current (EN)
EN = 0 V
−1
EN = VI
−1
0
1
µA
A
1
IO = 1 A,
IO = 1 A,
TJ = 25°C
TJ = −40°C to 125°C
500
TPS76728
TJ = 25°C
TJ = −40°C to 125°C
450
TPS76730
IO = 1 A,
IO = 1 A,
TJ = 25°C
TJ = −40°C to 125°C
350
TPS76733
IO = 1 A,
IO = 1 A,
TJ = 25°C
TJ = −40°C to 125°C
230
TPS76750
IO = 1 A,
IO = 1 A,
Dropout voltage (see Note 4)
ms
825
675
mV
575
380
NOTE 4: IN voltage equals VO(typ) − 100 mV; TPS76701 output voltage set to 3.3 V nominal with external resistor divider. TPS76715, TPS76718,
TPS76725, and TPS76727 dropout voltage limited by input voltage range limitations (i.e., TPS76730 input voltage needs to drop to 2.9 V
for purpose of this test).
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VO
Zo
VDO
Output voltage
vs Output current
2, 3, 4
vs Free-air temperature
5, 6, 7
Ground current
vs Free-air temperature
8, 9
Power-supply ripple rejection
vs Frequency
10
Output spectral noise density
vs Frequency
11
Input voltage (min)
vs Output voltage
12
Output impedance
vs Frequency
13
Dropout voltage
vs Free-air temperature
Line transient response
Load transient response
VO
8
14
15, 17
16, 18
Output voltage
vs Time
Dropout voltage
vs Input voltage
Equivalent series resistance (ESR)
vs Output current
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22−25
SGLS009B − MARCH 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
TPS76715
TPS76733
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.4985
3.2835
VI = 4.3 V
TA = 25°C
3.2830
VI = 2.7 V
TA = 25°C
1.4980
VO − Output Voltage − V
1.4975
VO − Output Voltage − V
3.2825
1.4970
3.2820
1.4965
3.2815
1.4960
3.2810
1.4955
3.2805
1.4950
3.2800
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8
IO − Output Current − A
0.9
0
1
0.1
0.2 0.3
0.4
0.5
0.6 0.7
0.8
0.9
1
IO − Output Current − A
Figure 2
Figure 3
TPS76725
TPS76733
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
2.4960
3.32
VI = 3.5 V
TA = 25°C
2.4955
VI = 4.3 V
3.31
VO − Output Voltage − V
VO − Output Voltage − V
2.4950
2.4945
2.4940
2.4935
2.4930
3.30
3.29
IO = 1 A
IO = 1 mA
3.28
3.27
3.26
2.4925
2.4920
0
0.1 0.2 0.3
0.4 0.5
0.6 0.7
0.8 0.9
1
3.25
−60 −40 −20
0
20
40
60
80
100 120 140
TA − Free-Air Temperature − °C
IO − Output Current − A
Figure 4
Figure 5
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SGLS009B − MARCH 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
TPS76715
TPS76725
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
1.515
2.515
VI = 3.5 V
VI = 2.7 V
2.510
VO − Output Voltage − V
VO − Output Voltage − V
1.510
1.505
1.500
IO = 1 A
IO = 1 mA
1.495
1.490
2.505
2.500
IO = 1 A
2.495
IO = 1 mA
2.490
2.485
1.485
−60 −40 −20
0
20
40
60
80
2.480
−60 −40
100 120 140
TA − Free-Air Temperature − °C
−20
Figure 6
TPS76733
92
90
VI = 4.3 V
88
Ground Current − µ A
20
40
Figure 7
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
86
84
82
IO = 1 mA
80
IO = 1 A
78
IO = 500 mA
76
74
72
−60 −40 −20
0
20
40
60
80
100 120 140
TA − Free-Air Temperature − °C
Figure 8
10
0
60
80
TA − Free-Air Temperature − °C
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100 120
SGLS009B − MARCH 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
TPS76715
TPS76733
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
POWER-SUPPLY RIPPLE REJECTION
vs
FREQUENCY
90
PSRR − Power Supply Ripple Rejection − dB
100
VI = 2.7 V
90
IO = 1 A
IO = 1 mA
85
IO = 500 mA
80
75
−60 −40 −20
0
20
40
60
80
70
60
50
40
30
20
10
0
−10
10
100 120 140
100
TA − Free-Air Temperature − °C
1k
10k
100k
1M
f − Frequency − Hz
Figure 9
Figure 10
TPS76733
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
10−5
Output Spectral Noise Density − µV Hz
Ground Current − µ A
95
VI = 4.3 V
Co = 10 µF
IO = 1 A
TA = 25°C
80
VI = 4.3 V
Co = 10 µF
TA = 25°C
IO = 7 mA
10−6
IO = 1 A
10−7
10−8
102
103
104
105
f − Frequency − Hz
Figure 11
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SGLS009B − MARCH 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
INPUT VOLTAGE (MIN)
vs
OUTPUT VOLTAGE
4
IO = 1 A
VI − Input Voltage (Min) − V
TA = 25°C
TA = 125°C
3
TA = −40°C
2.7
2
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
VO − Output Voltage − V
Figure 12
TPS76733
TPS76733
OUTPUT IMPEDANCE
vs
FREQUENCY
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
103
0
IO = 1 A
VDO − Dropout Voltage − mV
Zo − Output Impedance − Ω
VI = 4.3 V
Co = 10 µF
TA = 25°C
IO = 1 mA
10−1
IO = 1 A
102
101
IO = 10 mA
100
10−1
IO = 0
Co = 10 µF
10−2
101
102
103
104
f − Frequency − kHz
105
106
10−2
−60 −40 −20
Figure 13
12
0
20
40
Figure 14
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80 100 120 140
TA − Free-Air Temperature − °C
• DALLAS, TEXAS 75265
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TYPICAL CHARACTERISTICS
TPS76715
TPS76715
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
∆ VO − Change in
Output Voltage − mV
VI − Input Voltage − V
100
3.7
2.7
Co = 10 µF
TA = 25°C
50
0
−50
I O − Output Current − A
∆ VO − Change in
Output Voltage − mV
−100
10
0
−10
Co = 10 µF
TA = 25°C
0
20
40
60
1
0.5
0
0
80 100 120 140 160 180 200
t − Time − µs
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
Figure 16
TPS76733
TPS76733
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
100
∆ VO − Change in
Output Voltage − mV
VI − Input Voltage − V
Figure 15
Co = 10 µF
TA = 25°C
5.3
I O − Output Current − A
∆ VO − Change in
Output Voltage − mV
4.3
10
0
−10
0
20
40
60
80 100 120 140 160 180 200
t − Time − µs
Co = 10 µF
TA = 25°C
50
0
−50
−100
1
0.5
0
0
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
Figure 18
Figure 17
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13
SGLS009B − MARCH 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
TPS76733
TPS76701
OUTPUT VOLTAGE
vs
TIME (AT STARTUP)
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
900
Co = 10 µF
IO = 1 A
TA = 25°C
3
IO = 1 A
800
VDO − Dropout Voltage − mV
VO− Output Voltage − V
4
2
1
Enable Pulse − V
0
0
700
600
500
TA = 25°C
400
TA = 125°C
300
200
TA = −40°C
100
0
0
0.1
0.2 0.3
0.4 0.5 0.6 0.7 0.8
t − Time − ms
0.9
1
2.5
3.5
4
VI − Input Voltage − V
4.5
5
Figure 20
Figure 19
VI
3
To Load
IN
OUT
+
EN
Co
GND
RL
ESR
Figure 21. Test Circuit for Typical Regions of Stability (Figures 22 Through 25) (Fixed-Output Options)
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TYPICAL CHARACTERISTICS
TYPICAL REGION OF STABILITY
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
ESR − Equivalent Series Resistance − Ω
ESR − Equivalent Series Resistance − Ω
10
Region of Instability
1
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TA = 25°C
Region of Stability
0.1
Region of Instability
1
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TJ = 125°C
0.1
Region of Instability
Region of Instability
0.01
0.01
0
200
400
600
800
0
1000
200
400
600
800
1000
IO − Output Current − mA
IO − Output Current − mA
Figure 22
Figure 23
TYPICAL REGION OF STABILITY
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
10
ESR − Equivalent Series Resistance − Ω
ESR − Equivalent Series Resistance − Ω
Region of Stability
Region of Instability
1
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TA = 25°C
Region of Stability
0.1
Region of Instability
0.01
Region of Instability
1
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TJ = 125°C
Region of Stability
0.1
Region of Instability
0.01
0
200
400
600
800
1000
0
200
IO − Output Current − mA
400
600
800
1000
IO − Output Current − mA
Figure 24
Figure 25
† Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to Co.
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APPLICATION INFORMATION
The TPS767xx family includes eight fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, 2.7 V, 2.8 V, 3 V, 3.3 V,
and 5 V), and an adjustable regulator, the TPS76701 (adjustable from 1.5 V to 5.5 V).
device operation
The TPS767xx features very low quiescent current, which remains virtually constant even with varying loads.
Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the
load current through the regulator (IB = IC/β). The TPS767xx uses a PMOS transistor to pass current; because
the gate of the PMOS is voltage driven, operating current is low and invariable over the full load range.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in β forces an increase in IB to maintain the load. During power up, this translates
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS767xx quiescent current remains low even when the regulator drops out, eliminating both problems.
The TPS767xx family also features a shutdown mode that places the output in the high-impedance state
(essentially equal to the feedback-divider resistance) and reduces quiescent current to 2 µA. If the shutdown
feature is not used, EN should be tied to ground.
minimum load requirements
The TPS767xx family is stable even at zero load; no minimum load is required for operation.
FB—pin connection (adjustable version only)
The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option . The output
voltage is sensed through a resistor divider network to close the loop as shown in Figure 27. Normally, this
connection should be as short as possible; however, the connection can be made near a critical circuit to
improve performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier and
noise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup
is essential.
external capacitor requirements
An input capacitor is not usually required; however, a ceramic bypass capacitor (0.047 µF or larger) improves
load transient response and noise rejection if the TPS767xx is located more than a few inches from the power
supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load
transients with fast rise times are anticipated.
Like all low dropout regulators, the TPS767xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance value is 10 µF and the equivalent
series resistance (ESR) must be between 50 mΩ and 1.5 Ω. Capacitor values 10 µF or larger are acceptable,
provided the ESR is less than 1.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic
capacitors are all suitable, provided they meet the requirements described above. Most of the commercially
available 10-µF surface-mount ceramic capacitors, including devices from Sprague and Kemet, meet the ESR
requirements stated above.
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APPLICATION INFORMATION
external capacitor requirements (continued)
TPS767xx
6
VI
7
IN
RESET
5
RESET
250 kΩ
IN
OUT
C1
0.1 µF
16
EN
OUT
14
VO
13
+
GND
Co
10 µF
3
Figure 26. Typical Application Circuit (Fixed Versions)
programming the TPS76701 adjustable LDO regulator
The output voltage of the TPS76701 adjustable regulator is programmed using an external resistor divider as
shown in Figure 27. The output voltage is calculated using:
V
O
+V
ǒ1 ) R1
Ǔ
R2
ref
(1)
Where:
Vref = 1.1834 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 50 µA and then calculate R1 using:
R1 +
ǒ
V
V
Ǔ
O *1
ref
R2
(2)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS76701
VI
0.1 µF
IN
RESET
250 kΩ
≥ 1.7 V
≤ 0.9 V
Reset Output
EN
OUT
VO
R1
FB / NC
GND
Co
OUTPUT
VOLTAGE
R1
R2
UNIT
2.5 V
33.2
30.1
kΩ
3.3 V
53.6
30.1
kΩ
3.6 V
61.9
30.1
kΩ
4.75 V
90.8
30.1
kΩ
R2
Figure 27. TPS76701 Adjustable LDO Regulator Programming
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APPLICATION INFORMATION
reset indicator
The TPS767xx features a RESET output that can be used to monitor the status of the regulator. The internal
comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal
regulated value, the RESET output transistor turns on, taking the signal low. The open-drain output requires
a pullup resistor. If not used, it can be left floating. RESET can be used to drive power-on reset circuitry or as
a low-battery indicator. RESET does not assert itself when the regulated output voltage falls outside the
specified 2% tolerance, but instead reports an output voltage low relative to its nominal regulated value (refer
to timing diagram for start-up sequence).
regulator protection
The TPS767xx PMOS pass transistor has a built-in back diode that conducts reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS767xx also features internal current limiting and thermal protection. During normal operation, the
TPS767xx limits output current to approximately 1.7 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 150°C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below
130°C (typ), regulator operation resumes.
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than
or equal to PD(max).
The maximum power dissipation limit is determined using the following equation:
P
T max * T
A
+ J
D(max)
R
θJA
Where:
TJmax is the maximum allowable junction temperature.
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 172°C/W for the 8-terminal
SOIC and 32.6°C/W for the 20-terminal PWP with no airflow.
TA is the ambient temperature.
The regulator dissipation is calculated using:
P
D
ǒ
Ǔ
+ V *V
I
O
I
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the
thermal protection circuit.
18
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TPS76701QPWPRQ1
ACTIVE
HTSSOP
PWP
20
TBD
Call TI
Call TI
TPS76715QPWPRQ1
ACTIVE
HTSSOP
PWP
20
TBD
Call TI
Call TI
TPS76718QPWPRQ1
ACTIVE
HTSSOP
PWP
20
TBD
Call TI
Call TI
TPS76725QPWPRQ1
ACTIVE
HTSSOP
PWP
20
TBD
Call TI
Call TI
TPS76733QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
TPS76750QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
OTHER QUALIFIED VERSIONS OF TPS76701-Q1, TPS76715-Q1, TPS76718-Q1, TPS76725-Q1, TPS76733-Q1, TPS76750-Q1 :
• Catalog: TPS76701, TPS76715, TPS76718, TPS76725, TPS76733, TPS76750
• Enhanced Product: TPS76701-EP, TPS76715-EP, TPS76718-EP, TPS76725-EP, TPS76733-EP, TPS76750-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
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