SCLS560 − JANUARY 2004 D Controlled Baseline D D D D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† 3-State Version of ’HC153 Wide Operating Voltage Range of 2 V to 6 V High-Current Inverting Outputs Drive Up To 15 LSTTL Loads D D D D D D Low Power Consumption, 80-µA Max ICC Typical tpd = 9 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Permit Multiplexing From n Lines to One Line Perform Parallel-to-Serial Conversion D PACKAGE (TOP VIEW) 1OE B 1C3 1C2 1C1 1C0 1Y GND † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2OE A 2C3 2C2 2C1 2C0 2Y description/ordering information Each data selector/multiplexer contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate output-control inputs are provided for each of the two 4-line sections. The 3-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (in the high-impedance state), the low impedance of the single enabled output drives the bus line to a high or low logic level. Each output has its own output-enable (OE) input. The outputs are disabled when their respective OE is high. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 125°C SOIC − D Tape and reel SN74HC253QDREP SHC253QEP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS560 − JANUARY 2004 FUNCTION TABLE INPUTS SELECT† OE OUTPUT Y DATA B A C0 C1 C2 X X X X X C3 X H Z L L L X X X L L L L H X X X L H L H X L X X L L H L H X H X X L H L X X L X L L H L X X H X L H H H X X X L L L H H X X X H L H † Select inputs A and B are common to both sections. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS560 − JANUARY 2004 logic diagram (positive logic) A B 1OE 1C0 14 2 1 6 TG TG 1C1 5 TG 7 1C2 4 1Y TG TG 1C3 2OE 2C0 3 TG 15 10 TG TG 2C1 11 TG 9 2C2 12 2Y TG TG 2C3 13 TG POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCLS560 − JANUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v MIN NOM MAX 2 5 6 Input voltage 3.15 0.5 1.35 Input transition rise/fall time VCC = 6 V V 1.8 0 VCC = 2 V VCC = 4.5 V V 4.2 0 Output voltage V 1.5 VCC = 4.5 V VCC = 6 V Low-level input voltage UNIT VCC VCC V V 1000 500 ns 400 TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS560 − JANUARY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 µA VOH VI = VIH or VIL IOH = −6 mA IOH = −7.8 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 6 mA IOL = 7.8 mA II IOZ VI = VCC or 0 VO = VCC or 0 ICC Ci VI = VCC or 0, IO = 0 VCC MIN TA = 25°C TYP MAX MIN 2V 1.9 1.998 1.9 4.5 V 4.4 4.499 4.4 6V 5.9 5.999 5.9 4.5 V 3.98 4.3 3.7 6V 5.48 5.8 MAX UNIT V 5.2 2V 0.002 0.1 0.1 4.5 V 0.001 0.1 0.1 6V 0.001 0.1 0.1 4.5 V 0.17 0.26 0.4 6V 0.15 0.26 0.4 6V ±0.1 ±100 ±1000 nA 6V ±0.01 ±0.5 ±10 µA 8 160 µA 10 10 pF 6V 2 V to 6 V 3 V switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) A or B VCC 2V 62 150 225 Any Y 4.5 V 19 30 45 6V 16 26 38 2V 54 126 210 4.5 V 16 28 42 6V 13 23 36 2V 28 100 150 4.5 V 11 20 30 6V 9 17 26 2V 21 135 203 4.5 V 14 30 45 6V 12 35 38 2V 28 60 90 4.5 V 8 12 18 6V 6 10 15 tpd Data (Any C) ten tdis tt OE OE TA = 25°C MIN TYP MAX TO (OUTPUT) Y Y Y Y POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MAX UNIT ns ns ns ns 5 SCLS560 − JANUARY 2004 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER TO (OUTPUT) VCC 2V 76 235 355 A or B Any Y 4.5 V 23 47 71 6V 20 41 60 2V 68 220 335 4.5 V 20 44 67 6V 17 38 57 tpd Data (Any C) ten TA = 25°C TYP MAX FROM (INPUT) Y OE Y tt Y MIN MIN MAX 2V 44 185 280 4.5 V 16 37 56 6V 14 32 48 2V 45 210 315 4.5 V 17 42 63 6V 13 36 53 UNIT ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd 6 TEST CONDITIONS Power dissipation capacitance per multiplexer POST OFFICE BOX 655303 No load • DALLAS, TEXAS 75265 TYP 45 UNIT pF SCLS560 − JANUARY 2004 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER Test Point From Output Under Test S1 ten RL CL (see Note A) RL tPZH tPZL tPHZ tdis S2 tPLZ 1 kΩ 1 kΩ −− tpd or tt LOAD CIRCUIT CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open 50 pF 50 pF or 150 pF VCC Input 50% 50% 0V tPLH In-Phase Output 50% 10% tPHL VOH 50% 10% V OL tf 90% 90% tr tPHL Out-of-Phase Output 90% tPLH 50% 10% 50% 10% 90% VOH VOL tf tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL Output Waveform 1 (See Note B) tPLZ 10% tPZH Input 50% 10% 90% VCC 90% 50% 10% 0 V tr Output Waveform 2 (See Note B) ≈VCC ≈VCC 50% VOL tPHZ 50% 90% VOH ≈0 V tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74HC253QDREP ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04699-01XE ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF SN74HC253-EP : SN74HC253 • Catalog: SN74HC253-Q1 • Automotive: • Military: SN54HC253 NOTE: Qualified Version Definitions: - TI's standard catalog product • Catalog - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Automotive • Military - QML certified for Military and Defense Applications Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74HC253QDREP Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.5 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC253QDREP SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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