SCAS785A − OCTOBER 2004 − REVISED JANUARY 2008 D D D D DW OR PW PACKAGE (TOP VIEW) Qualified for Automotive Applications 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 6.5 ns at 5 V 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND description/ordering information This octal buffer and line driver is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74AC240 device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION† −40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA TOP-SIDE MARKING SOIC − DW Tape and reel SN74AC240QDWRQ1 AC240Q TSSOP − PW Tape and reel SN74AC240QPWRQ1 AC240Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. FUNCTION TABLE (each buffer) INPUTS OUTPUT Y OE A L H L L L H H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2008, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCAS785A − OCTOBER 2004 − REVISED JANUARY 2008 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 2 18 4 16 6 14 8 12 1Y1 1Y2 1Y3 1Y4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCAS785A − OCTOBER 2004 − REVISED JANUARY 2008 recommended operating conditions (see Note 3) VCC VIH Supply voltage VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL MIN MAX 2 6 3.15 0.9 1.35 0 Output voltage 0 IOH High-level output current ∆t/∆v VCC VCC VCC = 3 V VCC = 4.5 V VCC = 5.5 V −12 VCC = 3 V VCC = 4.5 V 12 VCC = 5.5 V 24 Input transition rise or fall rate V 1.65 Input voltage Low-level output current V 3.85 VI VO IOL V 2.1 VCC = 4.5 V VCC = 5.5 V Low-level input voltage UNIT −24 V V mA −24 24 8 mA ns/V TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCAS785A − OCTOBER 2004 − REVISED JANUARY 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C VCC MIN IOH = −50 µA IOH = −24 mA IOH = −50 mA† IOH = −75 mA† MIN MIN MAX 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 3V 2.56 2.4 2.46 4.5 V 3.86 3.7 3.76 5.5 V 4.86 4.7 4.76 5.5 V IOL = 50 mA† IOL = 75 mA† V 3.85 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 IOL = 12 mA IOL = 24 mA UNIT MAX 3.85 5.5 V IOL = 50 µA VOL MAX TA = −40°C TO 85°C 3V IOH = −12 mA VOH TYP TA = −40°C TO 125°C 5.5 V V 1.65 5.5 V 1.65 ±0.1 ±1 ±1 ±0.1 ±1 ±1 ±0.25 ±5 ±2.5 µA ICC VI = VCC or GND, IO = 0 5.5 V 4 Ci VI = VCC or GND 5V 2.5 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ For I/O ports, the parameter IOZ includes the input leakage current. 80 40 µA switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) temperature Data inputs II Control inputs IOZ‡ 5.5 V VO = VCC or GND, VI(OE) = VIL or VIH 5.5 V FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y PARAMETER 4 VI = VCC or GND VI = VCC or GND POST OFFICE BOX 655303 free-air TA = 25°C pF TA = −40°C TO 125°C TA = −40°C TO 85°C range, UNIT MIN TYP MAX MIN MAX MIN MAX 1.5 6 8 1 11 1 9 1.5 5.5 8 1 10.5 1 8.5 1.5 6 10.5 1 11.5 1 11 1.5 7 10 1 13 1 11 1.5 7 10 1 12.5 1 10.5 1.5 7.5 10.5 1 13.5 1 11.5 • DALLAS, TEXAS 75265 µA A ns ns ns SCAS785A − OCTOBER 2004 − REVISED JANUARY 2008 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y PARAMETER free-air TA = 25°C temperature TA = −40°C TO 125°C TA = −40°C TO 85°C range, UNIT MIN TYP MAX MIN MAX MIN MAX 1.5 4.5 6.5 1 8.5 1 7 1.5 4.5 6 1 8 1 6.5 1.5 5 7 1 9 1 8 1.5 5.5 8 1 10.5 1 8.5 2.5 6.5 9 1 10.5 1 9.5 2 6.5 9 1 11 1 9.5 ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per buffer/driver CL = 50 pF, f = 1 MHz TYP UNIT 45 pF PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open 500 Ω Output Control (low-level enabling) LOAD CIRCUIT VCC Input 50% VCC 50% VCC 0V tPLH tPHL Output VOH 50% VCC VOL 50% VCC TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open VCC 50% VCC 50% VCC 0V tPLZ tPZL Output Waveform 1 S1 at 2 × VCC (see Note B) ≈VCC 50% VCC tPHZ tPZH Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS VOL + 0.3 V VOL 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 12-Oct-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp SN74AC240QPWRG4Q1 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC240QPWRQ1 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN74AC240-Q1 : • Catalog: SN74AC240 • Military: SN54AC240 Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Oct-2011 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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