CS2100-OTP Fractional-N Clock Multiplier Features General Description Clock Multiplier / Jitter Reduction The CS2100-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock with frequencies as low as 50 Hz. The CS2100-OTP has many configuration options which are set once prior to runtime. At runtime there are three hardware configuration pins available for mode and feature selection. – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source Highly Accurate PLL Multiplication Factor – Maximum Error Less Than 1 PPM in HighResolution Mode One-Time Programmability – – Configurable Hardware Control Pins Configurable Auxiliary Output Flexible Sourcing of Reference Clock – – The CS2100-OTP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) grade. Customer development kits are also available for custom device prototyping, small production programming, and device evaluation. Please see “Ordering Information” on page 28 for complete details. External Oscillator or Clock Source Supports Inexpensive Local Crystal Minimal Board Space Required – No External Analog Loop-filter Components 3.3 V Hardware Control Timing Reference Frequency Reference PLL Output Lock Indicator Hardware Configuration 8 MHz to 75 MHz Low-Jitter Timing Reference Fractional-N Frequency Synthesizer Auxiliary Output 6 to 75 MHz PLL Output N 50 Hz to 30 MHz Frequency Reference Output to Input Clock Ratio Preliminary Product Information http://www.cirrus.com Digital PLL & Fractional N Logic This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) JUN '08 DS841PP1 CS2100-OTP TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 4. ARCHITECTURE OVERVIEW ............................................................................................................... 8 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 8 4.2 Hybrid Analog-Digital Phase Locked Loop ...................................................................................... 8 5. APPLICATIONS ................................................................................................................................... 10 5.1 One Time Programmability ............................................................................................................ 10 5.2 Timing Reference Clock Input ........................................................................................................ 10 5.2.1 Internal Timing Reference Clock Divider ............................................................................... 10 5.2.2 Crystal Connections (XTI and XTO) ...................................................................................... 11 5.2.3 External Reference Clock (REF_CLK) .................................................................................. 11 5.3 Frequency Reference Clock Input, CLK_IN ................................................................................... 11 5.3.1 CLK_IN Skipping Mode ......................................................................................................... 11 5.3.2 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 13 5.4 Output to Input Frequency Ratio Configuration ............................................................................. 14 5.4.1 User Defined Ratio (RUD) ..................................................................................................... 14 5.4.2 Manual Ratio Modifier (R-Mod) ............................................................................................. 15 5.4.3 Automatic Ratio Modifier (Auto R-Mod) ................................................................................ 15 5.4.4 Effective Ratio (REFF) .......................................................................................................... 16 5.4.5 Ratio Configuration Summary ............................................................................................... 16 5.5 PLL Clock Output ........................................................................................................................... 17 5.6 Auxiliary Output .............................................................................................................................. 18 5.7 Mode Pin Functionality ................................................................................................................... 18 5.7.1 M1 and M0 Mode Pin Functionality ....................................................................................... 18 5.7.2 M2 Mode Pin Functionality .................................................................................................... 19 5.7.2.1 M2 Configured as Output Disable .............................................................................. 19 5.7.2.2 M2 Configured as R-Mod Enable .............................................................................. 19 5.7.2.3 M2 Configured as Auto R-Mod Enable ...................................................................... 19 5.7.2.4 M2 Configured as AuxOutSrc Override ..................................................................... 19 5.8 Clock Output Stability Considerations ............................................................................................ 20 5.8.1 Output Switching ................................................................................................................... 20 5.8.2 PLL Unlock Conditions .......................................................................................................... 20 6. PARAMETER DESCRIPTIONS ........................................................................................................... 21 6.1 Modal Configuration Sets ............................................................................................................... 21 6.1.1 R-Mod Selection (RModSel[1:0]) ........................................................................................... 21 6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 22 6.1.3 Auto R-Modifier Enable (AutoRMod) ..................................................................................... 22 6.2 Ratio 0 - 3 ...................................................................................................................................... 22 6.3 Global Configuration Parameters ................................................................................................... 22 6.3.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 22 6.3.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 23 6.3.3 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 23 6.3.4 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 23 6.3.5 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 23 6.3.6 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 24 6.3.7 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 24 7. CALCULATING THE USER DEFINED RATIO .................................................................................... 25 DS841PP1 2 CS2100-OTP 7.1 High Resolution 12.20 Format ....................................................................................................... 25 7.2 High Multiplication 20.12 Format ................................................................................................... 25 8. PROGRAMMING INFORMATION ........................................................................................................ 26 9. PACKAGE DIMENSIONS .................................................................................................................... 27 THERMAL CHARACTERISTICS ......................................................................................................... 27 10. ORDERING INFORMATION .............................................................................................................. 28 11. REVISION HISTORY .......................................................................................................................... 28 LIST OF FIGURES Figure 1. Typical Connection Diagram ........................................................................................................ 5 Figure 2. Delta-Sigma Fractional-N Frequency Synthesizer ....................................................................... 8 Figure 3. Hybrid Analog-Digital PLL ............................................................................................................ 9 Figure 4. Internal Timing Reference Clock Divider ................................................................................... 10 Figure 5. External Component Requirements for Crystal Circuit .............................................................. 11 Figure 6. CLK_IN removed for > 223 SysClk cycles ................................................................................. 12 Figure 7. CLK_IN removed for < 223 SysClk cycles but > tCS ................................................................. 12 Figure 8. CLK_IN removed for < tCS ........................................................................................................ 13 Figure 9. Low bandwidth and new clock domain ...................................................................................... 13 Figure 10. High bandwidth with CLK_IN domain re-use ........................................................................... 14 Figure 11. Ratio Feature Summary ........................................................................................................... 17 Figure 12. PLL Clock Output Options ....................................................................................................... 17 Figure 13. Auxiliary Output Selection ........................................................................................................ 18 Figure 14. M2 Mapping Options ................................................................................................................ 19 Figure 15. Parameter Configuration Sets .................................................................................................. 21 LIST OF TABLES Table 1. Modal and Global Configuration .................................................................................................. 10 Table 2. Ratio Modifier .............................................................................................................................. 15 Table 3. Automatic Ratio Modifier ............................................................................................................. 15 Table 4. Example Audio Oversampling Clock Generation from CLK_IN .................................................. 16 Table 5. Example 12.20 R-Values ............................................................................................................ 25 Table 6. Example 20.12 R-Values ............................................................................................................ 25 DS841PP1 3 CS2100-OTP 1. PIN DESCRIPTION VD 1 10 M0 GND 2 9 M1 CLK_OUT 3 8 M2 AUX_OUT 4 7 XTI/REF_CLK CLK_IN 5 6 XTO Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output (Output) - PLL clock output. AUX_OUT 4 Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks, or a status signal, depending on configuration. CLK_IN 5 Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference. XTO XTI/REF_CLK 6 7 Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input clock. REF_CLK is an input for an externally generated low-jitter reference clock. M2 8 Mode Select (Input) - M2 is a configurable mode selection pin. M1 9 Mode Select (Input) - M1 is a configurable mode selection pin. M0 10 Mode Select (Input) - M0 is a configurable mode selection pin. 4 DS841PP1 CS2100-OTP 2. TYPICAL CONNECTION DIAGRAM 0.1 µF 1 µF +3.3 V VD M2 System Microcontroller M1 M0 Frequency Reference CS2100-OTP CLK_IN 1 or 2 XTI/REF_CLK CLK_OUT To circuitry which requires a low-jitter clock AUX_OUT To other circuitry or Microcontroller XTO GND Low-Jitter Timing Reference 1 N.C. x REF_CLK XTO or Crystal 2 40 pF XTI XTO 40 pF Figure 1. Typical Connection Diagram DS841PP1 5 CS2100-OTP 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. (Note 1) Parameters DC Power Supply Symbol Min Typ Max Units VD 3.1 3.3 3.5 V TAC -10 - +70 °C Ambient Operating Temperature (Power Applied) Commercial Grade Notes: 1. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to ground. Parameters Symbol Min Max Units DC Power Supply VD -0.3 6.0 V Input Current IIN - ±10 mA Digital Input Voltage (Note 1) VIN -0.3 VD + 0.4 V Ambient Operating Temperature (Power Applied) TA -55 125 °C Storage Temperature Tstg -65 150 °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 1. The maximum over/under voltage is limited by the input current except on the power supply pin. DC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade). Parameters Symbol Min Typ Max Units Power Supply Current - Unloaded (Note 2) ID - 12 18 mA Power Dissipation - Unloaded (Note 2) PD - 40 60 mW Input Leakage Current IIN - - ±10 µA Input Capacitance IC - 8 - pF High-Level Input Voltage VIH 70% - - VD Low-Level Input Voltage VIL - - 30% VD High-Level Output Voltage (IOH = -1.2 mA) VOH 80% - - VD Low-Level Output Voltage (IOH = 1.2 mA) VOL - - 20% VD Notes: 2. To calculate the additional current consumption due to loading (per output pin), multiply clock output frequency by load capacitance and power supply voltage. For example, fCLK_OUT (49.152 MHz) * CL (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to these loading conditions on CLK_OUT. 6 DS841PP1 CS2100-OTP AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade); CL = 15 pF. Parameters Crystal Frequency Symbol Conditions Min Typ Max Units fXTAL Fundamental Mode 8 - 50 MHz Reference Clock Input Frequency fREF_CLK 8 - 75 MHz Reference Clock Input Duty Cycle DREF_CLK 45 - 55 % Internal System Clock Frequency fSYS_CLK 8 18.75 MHz Clock Input Frequency (Auto R-Mod Disabled) fCLK_IN 50 Hz - 30 MHz Clock Input Frequency (Auto R-mod Enabled) fCLK_IN Auto R Modifier = 1 Auto R Modifier = 0.5 Auto R Modifier = 0.25 4 72 168 - 59 138 256 kHz kHz kHz pwCLK_IN fCLK_IN < fSYS_CLK/96 fCLK_IN > fSYS_CLK/96 2 10 - - UI ns tCS (Notes 4, 5) 20 - - ms Clock Skipping Input Frequency fCLK_SKIP (Note 5) 50 Hz - 80 kHz PLL Clock Output Frequency fCLK_OUT 6 - 75 MHz Clock Input Pulse Width (Note 3) Clock Skipping Timeout PLL Clock Output Duty Cycle tOD Measured at VD/2 48 50 52 % Clock Output Rise Time tOR 20% to 80% of VD - 1.7 3.0 ns Clock Output Fall Time tOF 80% to 20% of VD - 1.7 3.0 ns Period Jitter tJIT (Note 6) - 70 150 ps rms Base Band Jitter (100 Hz to 40 kHz) (Notes 6, 7) - 50 - ps rms Wide Band JItter (100 Hz Corner) (Notes 6, 8) - 175 - ps rms - 100 1 200 3 UI ms PLL Lock Time - CLK_IN (Note 9) tLC fCLK_IN < 200 kHz fCLK_IN > 200 kHz PLL Lock Time - REF_CLK tLR fREF_CLK = 8 to 75 MHz - 1 2 ms Output Frequency Synthesis Resolution (Note 10) ferr High Resolution High Multiplication 0 0 - ±0.5 ±112 ppm ppm Notes: 3. 1 UI (unit interval) corresponds to tSYS_CLK or 1/fSYS_CLK. 4. tCS represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequency, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will result in larger values of tCS. 5. Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 11 for more information. 6. fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11. 7. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd order 100 Hz to 40 kHz bandpass filter. 8. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd order 100 Hz Highpass filter. 9. 1 UI (unit interval) corresponds to tCLK_IN or 1/fCLK_IN. 10. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the reference clock. DS841PP1 7 CS2100-OTP 4. ARCHITECTURE OVERVIEW 4.1 Delta-Sigma Fractional-N Frequency Synthesizer The core of the CS2100 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolution for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to quickly tune to a new frequency. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies the Timing Reference Clock by the value of N to generate the PLL output clock. The desired output to input clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 2). The analog PLL based frequency synthesizer uses a low-jitter timing reference clock as a time and phase reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fractional-N divided clock with the original timing reference and generates a control signal. The control signal is filtered by the internal loop filter to generate the VCO’s control voltage which sets its output frequency. The delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio between the reference clock and the VCO output (thus the duty cycle of the modulator sets the fractional value). This allows the design to be optimized for very fast lock times for a wide range of output frequencies without the need for external filter components. As with any Fractional-N Frequency Synthesizer the timing reference clock should be stable and jitter-free. Timing Reference Clock Phase Comparator Internal Loop Filter Voltage Controlled Oscillator PLL Output Fractional-N Divider Delta-Sigma Modulator N Figure 2. Delta-Sigma Fractional-N Frequency Synthesizer 4.2 Hybrid Analog-Digital Phase Locked Loop The addition of the Digital PLL and Fractional-N Logic (shown in Figure 3) to the Fractional-N Frequency Synthesizer creates the Hybrid Analog-Digital Phase Locked Loop with many advantages over classical analog PLL techniques. These advantages include the ability to operate over extremely wide frequency ranges without the need to change external loop filter components while maintaining impressive jitter reduction performance. In the Hybrid architecture, the Digital PLL calculates the ratio of the PLL output clock to the frequency reference and compares that to the desired ratio. The digital logic generates a value of N which is then applied to the Fractional-N frequency synthesizer to generate the desired PLL output frequency. Notice that the frequency and phase of the timing reference signal do not affect the output of the PLL since the digital control loop will correct for the PLL output. A major advantage of the Digital PLL is the ease with which the loop filter bandwidth can be altered. The PLL bandwidth is set to a wide-bandwidth mode to quickly achieve lock and then reduced for optimal jitter rejection. 8 DS841PP1 CS2100-OTP Delta-Sigma Fractional-N Frequency Synthesizer Timing Reference Clock Phase Comparator Internal Loop Filter Voltage Controlled Oscillator PLL Output Fractional-N Divider Delta-Sigma Modulator Digital PLL and Fractional-N Logic N Digital Filter Frequency Reference Clock Frequency Comparator for Frac-N Generation Output to Input Ratio for Hybrid mode Figure 3. Hybrid Analog-Digital PLL DS841PP1 9 CS2100-OTP 5. APPLICATIONS 5.1 One Time Programmability The one time programmable (OTP) circuitry in the CS2100-OTP allows for pre-configuration of the device prior to use in a system. There are two types of parameters that are used for device pre-configuration: modal and global. The modal parameters are features which, when grouped together, create a modal configuration set (see Figure 15 on page 21). Up to four modal configuration sets can be permanently stored and then dynamically selected using the M[1:0] mode select pins (see Table 1). The global parameters are the remaining configuration settings which do not change with the mode select pins. The modal and global parameters can be pre-set at the factory or user programmed using the customer development kit, CDK2000; Please see “Programming Information” on page 26 for more details. Parameter Type M[1:0] pins = 00 M[1:0] pins = 01 M[1:0] pins = 10 M[1:0] pins = 11 Modal Configuration Set 0 Ratio 0 Configuration Set 1 Ratio 1 Configuration Set 2 Ratio 2 Configuration Set 3 Ratio 3 Global Configuration settings set once for all modes. Table 1. Modal and Global Configuration 5.2 Timing Reference Clock Input The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL output the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock directly affects the performance of the PLL and hence the quality of the PLL output. 5.2.1 Internal Timing Reference Clock Divider The Internal Timing Reference Clock (SysClk) is limited to a lower maximum frequency than that allowed on the XTI/REF_CLK pin. The CS2100-OTP supports the wider external frequency range by offering an internal divider for RefClk. The RefClkDiv[1:0] global parameter should be configured such that SysClk, the divided RefClk, then falls within the valid range as indicated in Figure 4. XTI/REF_CLK Timing Reference Clock 8 MHz < RefClk < 50 MHz (XTI) 75 MHz (REF_CLK) Timing Reference Clock Divider ÷1 ÷2 ÷4 Internal Timing Reference Clock 8 MHz < SysClk < 18.75 MHz RefClkDiv[1:0] Fractional-N Frequency Synthesizer PLL Output N Figure 4. Internal Timing Reference Clock Divider It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent upon its configuration as either a crystal connection or external clock input. See the “AC Electrical Characteristics” on page 7 for more details. Referenced Control Parameter Definition RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 23 10 DS841PP1 CS2100-OTP 5.2.2 Crystal Connections (XTI and XTO) An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 5. As shown, nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer to the “AC Electrical Characteristics” on page 7 for the allowed crystal frequency range. XTI 40 pF XTO 40 pF Figure 5. External Component Requirements for Crystal Circuit 5.2.3 External Reference Clock (REF_CLK) For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the reference clock source and XTO should be left unconnected or terminated through a 47 kΩ resistor to GND. 5.3 Frequency Reference Clock Input, CLK_IN The frequency reference clock input (CLK_IN) is used by the Digital PLL and Fractional-N Logic block to dynamically generate a fractional-N value for the Frequency Synthesizer (see “Hybrid Analog-Digital PLL” on page 9). The Digital PLL first compares the CLK_IN frequency to the PLL output. The Fractional-N logic block then translates the desired ratio based off of CLK_IN to one based off of the internal timing reference clock (SysClk). This allows the low-jitter timing reference clock to be used as the clock which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Characteristics” on page 7. 5.3.1 CLK_IN Skipping Mode CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses for up to 20 ms (tCS) at a time (see “AC Electrical Characteristics” on page 7 for specifications). CLK_IN skipping mode can only be used when the CLK_IN frequency is below 80 kHz. The ClkSkipEn global parameter enables this function. Regardless of the setting of the ClkSkipEn parameter the PLL output will continue for 223 SysClk cycles (466 ms to 1048 ms) after CLK_IN is removed (see Figure 6). This is true as long as CLK_IN does not glitch or have an effective change in period as the clock source is removed, otherwise the PLL will interpret this as a change in frequency causing clock skipping and the 223 SysClk cycle time-out to be bypassed and the PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 223 SysClk cycles pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl parameter; See “PLL Clock Output” on page 17. If CLK_IN is re-applied after such time, the PLL will re- DS841PP1 11 CS2100-OTP main unlocked for the specified time listed in the “AC Electrical Characteristics” on page 7 after which lock will be acquired and the PLL output will resume. 223 SysClk cycles 223 SysClk cycles Lock Time Lock Time CLK_IN ClkSkipEn=0 or 1 ClkOutUnl=0 CLK_IN ClkSkipEn=0 or 1 ClkOutUnl=1 PLL_OUT UNLOCK PLL_OUT UNLOCK = invalid clocks Figure 6. CLK_IN removed for > 223 SysClk cycles f CLK_IN is removed and then reapplied within 223 SysClk cycles but later than tCS, the ClkSkipEn parameter will have no effect and the PLL output will continue until CLK_IN is re-applied (see Figure 7). Once CLK_IN is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl parameter during this time. 223 SysClk cycles 223 SysClk cycles tCS tCS Lock Time Lock Time CLK_IN ClkSkipEn=0 or 1 ClkOutUnl=0 PLL_OUT UNLOCK CLK_IN ClkSkipEn=0 or 1 ClkOutUnl=1 PLL_OUT UNLOCK = invalid clocks Figure 7. CLK_IN removed for < 223 SysClk cycles but > tCS If CLK_IN is removed and then re-applied within tCS, the ClkSkipEn parameter determines whether PLL_OUT continues while the PLL re-acquires lock (see Figure 8). When ClkSkipEn is disabled and CLK_IN is removed the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl parameter during this time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will 12 DS841PP1 CS2100-OTP remain continuous throughout the missing CLK_IN period including the time while the PLL re-acquires lock. tCS tCS Lock Time CLK_IN ClkSkipEn=1 ClkOutUnl=0 or 1 CLK_IN ClkSkipEn=0 ClkOutUnl=1 PLL_OUT UNLOCK PLL_OUT UNLOCK = invalid clocks Lock Time tCS CLK_IN ClkSkipEn=0 ClkOutUnl=0 PLL_OUT UNLOCK Figure 8. CLK_IN removed for < tCS Referenced Control Parameter Definition ClkSkipEn..............................“Clock Skip Enable (ClkSkipEn)” on page 22 ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 23 5.3.2 Adjusting the Minimum Loop Bandwidth for CLK_IN The CS2100 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128 Hz using the ClkIn_BW[2:0] global parameter. The minimum loop bandwidth of the Digital PLL directly affects the jitter transfer function; specifically, jitter frequencies below the loop bandwidth corner are passed from the PLL input directly to the PLL output without attenuation. In some applications it is desirable to have a very low minimum loop bandwidth to reject very low jitter frequencies, commonly referred to as wander. In others it may be preferable to remove only higher frequency jitter, allowing the input wander to pass through the PLL without attenuation. Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other system clocks and associated data are derived will benefit from the maximum jitter and wander rejection of the lowest PLL bandwidth setting. See Figure 9. PLL BW = 1 Hz CLK_IN Wander > 1 Hz PLL_OUT MCLK Jitter MCLK or Wander and Jitter > 1 Hz Rejected Subclocks generated from new clock domain. LRCK LRCK SCLK SCLK SDATA D0 D1 SDATA D0 D1 Figure 9. Low bandwidth and new clock domain Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the system. See Figure 10. If there is substantial wander on the CLK_IN signal in these applications, it may be necessary to increase the minimum loop bandwidth allowing this wander to pass through to the DS841PP1 13 CS2100-OTP CLK_OUT signal in order to maintain phase alignment. For these applications, it is advised to experiment with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system timing errors due to wandering between the clocks and data synchronous to the CLK_IN domain and those synchronous to the PLL_OUT domain. PLL BW = 128 Hz CLK_IN Wander < 128 Hz PLL_OUT Jitter MCLK or Jitter > 128 Hz Rejected Wander < 128 Hz Passed to Output MCLK Subclocks and data re-used from previous clock domain. LRCK LRCK SCLK SCLK SDATA D0 D1 SDATA D0 D1 Figure 10. High bandwidth with CLK_IN domain re-use While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] parameter. Referenced Control Parameter Definition ClkIn_BW[2:0] .......................“Clock Input Bandwidth (ClkIn_BW[2:0])” on page 24 5.4 5.4.1 Output to Input Frequency Ratio Configuration User Defined Ratio (RUD) The User Defined Ratio, RUD, is a 32-bit un-signed fixed-point number which determines the basis for the desired input to output clock ratio. Up to four different ratios, Ratio0-3, can be stored in the CS2100’s one time programmable memory. Selection between the four ratios is achieved by the M[1:0] mode select pins. The 32-bit RUD can be expressed in either a high resolution (12.20) or high multiplication (20.12) format selectable by the LFRatioCfg global parameter. The RUD for high resolution (12.20) format is encoded with 12 MSBs representing the integer binary portion with the remaining 20 LSBs representing the fractional binary portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See “Calculating the User Defined Ratio” on page 25 for more information. The RUD for high multiplication (20.12) format is encoded with 20 MSBs representing the integer binary portion with the remaining 12 LSBs representing the fractional binary portion. In this configuration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM. It is recommended that the 12.20 High-Resolution format be utilized whenever the desired ratio is less than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the timing reference clock and the resolution of the RUD. The status of internal dividers, such as the internal timing reference clock divider, are automatically taken into account. Therefore RUD is simply the desired ratio of the output to input clock frequencies. Referenced Control Parameter Definition Ratio 0-3................................“Ratio 0 - 3” on page 22 LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 23 M[1:0] ....................................“M1 and M0 Mode Pin Functionality” on page 18 14 DS841PP1 CS2100-OTP 5.4.2 Manual Ratio Modifier (R-Mod) The manual Ratio Modifier is used to internally multiply/divide the currently addressed RUD (Ratio0-3 stored in the register space remain unchanged). The available options for R-Mod are summarized in Table 2 on page 15. R-Mod is enabled via the M2 pin in conjunction with the appropriate setting of the M2Config[2:0] global parameter (see Section 5.7.2 on page 19). RModSel[1:0] R Modifier 00 0.5 01 0.25 10 0.125 11 0.0625 Table 2. Ratio Modifier Referenced Control Parameter Definition Ratio 0-3................................“Ratio 0 - 3” on page 22 RModSel[1:0] ........................“R-Mod Selection (RModSel[1:0])” section on page 21 M2Config[2:0]........................“M2 Pin Configuration (M2Config[2:0])” on page 24 5.4.3 Automatic Ratio Modifier (Auto R-Mod) The Automatic R-Modifier uses the CLK_IN Frequency Range Detector to implement a frequency dependent multiply of the currently addressed RUD as shown in Table 3. The CLK_IN Frequency Range Detector determines the ratio between the frequency of the internal SysClk and the CLK_IN input signal. The result of the ratio measurement is the internal status signal called FsDetect[1:0]. Like with R-Mod, the Ratio0-3 parameters stored in the one time programmable memory remain unchanged. The Automatic Ratio Modifier is enabled either by the AutoRMod modal parameter or via the M2 pin in conjunction with the appropriate setting of the M2Config[2:0] global parameter (see Section 5.7.2 on page 19). FsDetect[1:0] fSysClk / fCLK_IN Auto R Modifier 00 > 224 1 01 96 - 224 0.5 10 < 96 0.25 Table 3. Automatic Ratio Modifier It is important to note that Auto R-Mod (if enabled) is applied in addition to any R-Mod already selected by the RModSel[1:0] modal parameter and is used to calculate the Effective Ratio (see Section 5.4.4 on page 16). Auto R-Mod can be used to generate the appropriate oversampling clock (MCLK) for audio A/D and D/A converters. For example, if the clock applied to CLK_IN is the audio sample rate, Fs (also known as the word, frame or Left/Right clock), and SysClk is 12.288 MHz (REF_CLK = 12.288 MHz with RefClkDiv[1:0] DS841PP1 15 CS2100-OTP set to ‘10’), FsDetect[1:0] would then reflect the frequency range of the audio sample rate. An RUD of 512 generates the audio oversampling clocks as shown in Table 4. FsDetect[1:0] Inferred Audio Sample Rate when SysClk = 12.288 MHz Speed Mode (used for audio converters) Audio Oversampling Clock 00 < 54.8 kHz Single Speed 512 x 01 54.8 kHz to 128 kHz Double Speed 256 x 10 > 128 kHz Quad Speed 128 x Table 4. Example Audio Oversampling Clock Generation from CLK_IN Referenced Control Parameter Definition Ratio 0-3................................“Ratio 0 - 3” on page 22 RModSel[1:0] ........................“R-Mod Selection (RModSel[1:0])” section on page 21 AutoRMod .............................“Auto R-Modifier Enable (AutoRMod)” on page 22 M2Config[2:0]........................“M2 Pin Configuration (M2Config[2:0])” on page 24 5.4.4 Effective Ratio (REFF) The Effective Ratio (REFF) is an internal calculation comprised of RUD and the appropriate modifiers, as previously described. REFF is calculated as follows: REFF = RUD • R-Mod • Auto R-Mod To simplify operation the device handles some of the ratio calculation functions automatically (such as when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need to be altered to account for internal dividers. Ratio modifiers which would produce an overflow or truncation of REFF should not be used. In all cases, the maximum and minimum allowable values for REFF are dictated by the frequency limits for both the input and output clocks as shown in the “AC Electrical Characteristics” on page 7. Selection of the user defined ratio from the four stored ratios is made by using the M[1:0] pins. Referenced Control Parameter Definition M[1:0] pins.............................“M1 and M0 Mode Pin Functionality” on page 18 5.4.5 Ratio Configuration Summary The RUD is the user defined ratio for which up to four different values (Ratio0-3) can be stored in the one time programmable memory. The M[1:0] pins then select the user defined ratio to be used as well as the modal configuration set. The resolution/format for the RUD is selectable. R-Mods are applied according to their settings. The user defined ratio, ratio modifier, and automatic ratio modifier make up the effective 16 DS841PP1 CS2100-OTP ratio REFF, the final calculation used to determine the output to input clock ratio. The effective ratio is then corrected for the internal dividers. The conceptual diagram in Figure 11 summarizes the features involved in the calculation of the ratio values used to generate the fractional-N value which controls the Frequency Synthesizer. The subscript ‘4’ indicates the modal parameters. Timing Reference Clock (XTI/REF_CLK) Divide RefClkDiv[1:0] Effective Ratio REFF M2 pin M[1:0] pins User Defined Ratio RUD SysClk RModSel[1:0]4 Ratio 0 Ratio Format Ratio 1 12.20 20.12 Ratio 2 Ratio Modifier Auto R-Mod Frequency Synthesizer PLL Output RefClkDiv[1:0] R Correction Digital PLL & Fractional N Logic Dynamic Ratio, ‘N’ Ratio 3 LFRatioCfg Frequency Reference Clock (CLK_IN) AutoRMod4 or M2 pin FsDet[1:0] Figure 11. Ratio Feature Summary Referenced Control Parameter Definition Ratio 0-3................................“Ratio 0 - 3” on page 22 M[1:0] pins.............................“M1 and M0 Mode Pin Functionality” on page 18 LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 23 RModSel[1:0] ........................“R-Mod Selection (RModSel[1:0])” section on page 21 AutoRMod .............................“Auto R-Modifier Enable (AutoRMod)” on page 22 RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 23 5.5 PLL Clock Output The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the M2 pin when the M2Config[1:0] global parameter is set to either 000 or 010. The output from the PLL automatically drives a static low condition while the PLL is unlocked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl global parameter, however the state CLK_OUT may then be unreliable during an unlock condition. ClkOutUnl PLL Locked/Unlocked 0 0 2:1 Mux 1 PLL Output M2 pin with M2Config[1:0] = 000, 010 0 2:1 Mux PLL Clock Output PLLClkOut PLL Clock Output Pin (CLK_OUT) 1 Figure 12. PLL Clock Output Options Referenced Control Parameter Definition ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 23 ClkOutDis ..............................“M2 Configured as Output Disable” on page 19 M2Config[2:0]........................“M2 Pin Configuration (M2Config[2:0])” on page 24 DS841PP1 17 CS2100-OTP 5.6 Auxiliary Output The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 13, to one of four signals: reference clock (RefClk), input clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is controlled via the AuxOutSrc[1:0] modal parameter. If AUX_OUT is set to Lock, the AuxLockCfg global parameter is then used to control the output driver type and polarity of the LOCK signal (see section 6.3.2 on page 23). If AUX_OUT is set to CLK_OUT, the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The driver for the pin can be set to high-impedance using the M2 pin when the M2Config[1:0] global parameter is set to either 001 or 010. AuxOutSrc[1:0] Timing Reference Clock (RefClk) M2 pin with M2Config[1:0] = 001, 010 Frequency Reference Clock (CLK_IN) Auxiliary Output Pin (AUX_OUT) 4:1 Mux PLL Clock Output (PLLClkOut) AuxLockCfg PLL Lock/Unlock Indication (Lock) Figure 13. Auxiliary Output Selection Referenced Control Parameter Definition AuxOutSrc[1:0]......................“Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 22 AuxOutDis .............................“M2 Configured as Output Disable” on page 19 AuxLockCfg...........................“AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 23 M2Config[2:0]........................“M2 Pin Configuration (M2Config[2:0])” on page 24 5.7 5.7.1 Mode Pin Functionality M1 and M0 Mode Pin Functionality M[1:0] determine the functional mode of the device and select both the default User Defined Ratio and the set of modal parameters. The modal parameters are RModSel[1:0], AuxOutSrc[1:0], and AutoRMod. By modifying one or more of the modal parameters between the 4 sets, different functional configurations can be achieved. However, global parameters are fixed and the same value will be applied to each functional configuration. Figure 15 on page 21 provides a summary of all parameters used by the device. 18 DS841PP1 CS2100-OTP 5.7.2 M2 Mode Pin Functionality M2 usage is mapped to one of the optional special functions via the M2Config[2:0] global parameter. Depending on what M2 is mapped to, it will either act as an output enable/disable pin or override certain modal parameters. Figure 14 summarizes the available options and the following sections will describe each option in more detail. M2Config[2:0] global parameter M2 pin 000 Disable CLK_OUT pin 001 Disable AUX_OUT pin 010 Disable CLK_OUT and AUX_OUT pins 011 RModSel[1:0] Modal Parameter Enable 100 Reserved 101 AutoRMod Modal Parameter Override 110 Reserved 111 Force AuxOutSel[1:0] = 10 (PLL Clock Out) Figure 14. M2 Mapping Options 5.7.2.1 M2 Configured as Output Disable If M2Config[2:0] is set to either ‘000’, ‘001’, or ‘010’, M2 becomes an output disable pin for one or both output pins. If M2 is driven ‘low’, the corresponding output(s) will be enabled, if M2 is driven ‘high’, the corresponding output(s) will be disabled. 5.7.2.2 M2 Configured as R-Mod Enable If M2Config[2:0] is set to ‘011’, M2 becomes the R-Mod enable pin. It should be noted that M2 is the only way to enable R-Mod. Even though the RModSel[1:0] modal parameter can be set arbitrarily for each configuration set, it will not take effect unless enabled via M2. If M2 is driven ‘low’, R-Mod will be disabled, if M2 is driven ‘high’ R-Mod will be enabled. 5.7.2.3 M2 Configured as Auto R-Mod Enable If M2Config[2:0] is set to ‘101’, M2 becomes the Auto R-Mod enable pin and will override the AutoRMod modal parameter. If M2 is driven ‘low’, Auto R-Mod will be disabled, if M2 is driven ‘high’ Auto R-Mod will be enabled. 5.7.2.4 M2 Configured as AuxOutSrc Override If M2Config[2:0] is set to ‘111’, M2 when driven ‘high’ will override the AuxOutSrc[1:0] modal parameter and force the AUX_OUT source to PLL Clock Output. When M2 is driven ‘low’, AUX_OUT will function according to AuxOutSrc[1:0]. DS841PP1 19 CS2100-OTP 5.8 5.8.1 Clock Output Stability Considerations Output Switching The CS2100-OTP is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an output, changing the auxiliary output source between REF_CLK and CLK_OUT, and the automatic disabling of the output(s) during unlock will not cause a runt or partial clock period. The following exceptions/limitations exist: • Enabling/disabling AUX_OUT when AuxOutSrc = 11 (unlock indicator). • Switching AuxOutSrc[1:0] to or from 01 (CLK_IN) and to or from 11 (unlock indicator) (Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch). When any of these exceptions occur, a partial clock period on the output may result. 5.8.2 PLL Unlock Conditions Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go unlocked: 20 • Any change in the state of the M1 and M0 pins will cause the PLL to temporarily lose lock as the new setting takes affect. • Changes made to the state of the M2 when the M2Config[2:0] global parameter is set to 011, 100, 101, or 110 can cause the PLL to temporarily lose lock as the new setting takes affect. • Any discontinuities on the Timing Reference Clock, REF_CLK. • Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature is enabled and the requirements of Clock Skipping are satisfied (see “CLK_IN Skipping Mode” on page 11). • Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency. • Step changes in CLK_IN frequency. DS841PP1 CS2100-OTP 6. PARAMETER DESCRIPTIONS As mentioned in Section 5.1 on page 10, there are two different kinds of parameter configuration sets, Modal and Global. These configuration sets, shown in Figure 15, can be programmed in the field using the CDK2000 or preprogrammed at the factory. Please see “Programming Information” on page 26 for more details. M[1:0] pins Modal Configuration Set #0 Ratio 0 RModSel[1:0] AuxOutSrc[1:0] AutoRmod 00 RModSel[1:0] AuxOutSrc[1:0] AutoRmod 01 RModSel[1:0] AuxOutSrc[1:0] AutoRmod 10 RModSel[1:0] AuxOutSrc[1:0] AutoRmod 11 Ratio 1 Modal Configuration Set #2 Ratio 2 Modal Configuration Set #3 Ratio 3 Digital/PLL Core Modal Configuration Set #1 Global Configuration Set ClkSkipEn AuxLockCfg RefClkDiv[1:0] ClkOutUnl LFRatioCfg M2Config[2:0] ClkIn_BW[2:0] Figure 15. Parameter Configuration Sets 6.1 Modal Configuration Sets There are four instances of each of these configuration parameters. Selection between the four stored sets is made using the M[1:0] pins. 6.1.1 R-Mod Selection (RModSel[1:0]) Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N. RModSel[1:0] R-Mod Selection 00 Right-shift R-value by 1 (÷ 2). 01 Right-shift R-value by 2 (÷ 4). 10 Right-shift R-value by 3 (÷ 8). 11 Right-shift R-value by 4 (÷ 16). Application: “Manual Ratio Modifier (R-Mod)” on page 15 Note: This parameter does not take affect unless M2 pin is high and the M2Config[2:0] global parameter is set to ‘011’. DS841PP1 21 CS2100-OTP 6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) Selects the source of the AUX_OUT signal. AuxOutSrc[1:0] Auxiliary Output Source 00 RefClk. 01 CLK_IN. 10 CLK_OUT. 11 PLL Lock Status Indicator. Application: “Auxiliary Output” on page 18 Note: When set to 11, the AuxLockCfg global parameter sets the polarity and driver type (“AUX PLL Lock Output Configuration (AuxLockCfg)” on page 23). 6.1.3 Auto R-Modifier Enable (AutoRMod) Controls the automatic ratio modifier function. 6.2 AutoRMod Automatic R-Mod State 0 Disabled. 1 Enabled. Application: “Automatic Ratio Modifier (Auto R-Mod)” on page 15 Ratio 0 - 3 The four 32-bit User Defined Ratios are stored in the CS2100’s one time programmable memory. See “Output to Input Frequency Ratio Configuration” on page 14 and “Calculating the User Defined Ratio” on page 25 for more details. 6.3 6.3.1 Global Configuration Parameters Clock Skip Enable (ClkSkipEn) This parameter enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the CLK_IN has missing pulses. ClkSkipEn PLL Clock Skipping Mode 0 Disabled. 1 Enabled. Application: “CLK_IN Skipping Mode” on page 11 Note: 22 fCLK_IN must be < 80 kHz to use this feature. DS841PP1 CS2100-OTP 6.3.2 AUX PLL Lock Output Configuration (AuxLockCfg) When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] modal parameter = ‘11’), this global parameter configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this parameter is disregarded. AuxLockCfg AUX_OUT Driver Configuration 0 Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition). 1 Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition). Application: “Auxiliary Output” on page 18 Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. Therefore, the pin polarity is defined relative to the unlock condition. 6.3.3 Reference Clock Input Divider (RefClkDiv[1:0]) Selects the input divider for the timing reference clock. 6.3.4 RefClkDiv[1:0] Reference Clock Input Divider REF_CLK Frequency Range 00 ÷ 4. 32 MHz to 75 MHz (50 MHz with XTI) 01 ÷ 2. 16 MHz to 37.5 MHz 10 ÷ 1. 8 MHz to 18.75 MHz 11 Reserved. Application: “Internal Timing Reference Clock Divider” on page 10 Enable PLL Clock Output on Unlock (ClkOutUnl) Defines the state of the PLL output during the PLL unlock condition. 6.3.5 ClkOutUnl Clock Output Enable Status 0 Clock outputs are driven ‘low’ when PLL is unlocked. 1 Clock outputs are always enabled (results in unpredictable output when PLL is unlocked). Application: “PLL Clock Output” on page 17 Low-Frequency Ratio Configuration (LFRatioCfg) Determines how to interpret the currently indexed 32-bit User Defined Ratio . LFRatioCfg Ratio Bit Encoding Interpretation 0 20.12 - High Multiplier. 1 12.20 - High Accuracy. Application: “User Defined Ratio (RUD)” on page 14 DS841PP1 23 CS2100-OTP 6.3.6 M2 Pin Configuration (M2Config[2:0]) Controls which special function is mapped to the M2 pin. 6.3.7 M2Config[2:0] M2 pin function 000 Disable CLK_OUT pin. 001 Disable AUX_OUT pin. 010 Disable CLK_OUT and AUX_OUT. 011 RModSel[1:0] Modal Parameter Enable. 100 Reserved. 101 AutoRMod Modal Parameter Override. 110 Reserved. 111 Force AuxOutSrc[1:0] = 10 (PLL Clock Out). Application: “M2 Mode Pin Functionality” on page 19 Clock Input Bandwidth (ClkIn_BW[2:0]) Sets the minimum loop bandwidth when locked to CLK_IN. 24 ClkIn_BW[2:0] Minimum Loop Bandwidth 000 1 Hz 001 2 Hz 010 4 Hz 011 8 Hz 100 16 Hz 101 32 Hz 110 64 Hz 111 128 Hz Application: “Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 13 DS841PP1 CS2100-OTP 7. CALCULATING THE USER DEFINED RATIO Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who would like to know more about how the User Defined Ratio is calculated and stored. Most calculators do not interpret the fixed point binary representation which the CS2100-OTP uses to define the output to input clock ratio (see Section 5.4.1 on page 14); However, with a simple conversion we can use these tools to generate a binary or hex value for Ratio0-3 to be stored in one time programmable memory. Please see “Programming Information” on page 26 for more details on programming. 7.1 High Resolution 12.20 Format To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desired output clock frequency by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 220 to get the scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and write to the register. A few examples have been provided in Table 5. Scaled Decimal Representation = (output clock/input clock) • 220 Hex Representation of Binary RUD 12.288 MHz/10 MHz=1.2288 1288490 00 13 A9 2A 11.2896 MHz/44.1 kHz=256 268435456 10 00 00 00 Desired Output to Input Clock Ratio (output clock/input clock) Table 5. Example 12.20 R-Values 7.2 High Multiplication 20.12 Format To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desired output clock frequency by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 212 to get the scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and write to the register. A few examples have been provided in Table 6. Desired Output to Input Clock Ratio (output clock/input clock) Scaled Decimal Representation = (output clock/input clock) • 212 Hex Representation of Binary RUD 12.288 MHz/60 Hz=204,800 838860800 32 00 00 00 11.2896 MHz/59.97 Hz =188254.127... 771088904 2D F5 E2 08 Table 6. Example 20.12 R-Values DS841PP1 25 CS2100-OTP 8. PROGRAMMING INFORMATION Field programming of the CS2100-OTP is achieved using the hardware and software tools included with the CDK2000. The software tools can be downloaded from www.cirrus.com for evaluation prior to ordering a CDK. The CDK2000 is designed with built-in features to ease the process of programming small quantities of devices for prototype and small production builds. In addition to its field programming capabilities, the CDK2000 can also be used for the complete evaluation of programmed CS2100-OTP devices. The CS2100-OTP can also be factory programmed for large quantity orders. When ordering factory programmed devices, the CDK should first be used to program and evaluate the desired configuration. When evaluation is complete, the CS2000 Configuration Wizard is used to generate a file containing all device configuration information; this file is conveyed to Cirrus Logic as a complete specification for the factory programming configuration. Please contact your local Cirrus Logic sales representative for more information regarding factory programmed parts. See the CDK2000 datasheet, available at www.cirrus.com, for detailed information on the use of the CDK2000 programming and evaluation tools. Below is a form which represents the information required for programming a device (noted in gray). The “Parameter Descriptions” section beginning on page 21 describes the functions of each parameter. This form may be used either for personal notation for device configuration or it can be filled out and given to a Cirrus representative in conjunction with the programming file from the CDK2000 as an additional check. The User Defined Ratio may be filled out in decimal or it may be entered as hex as outlined in “Calculating the User Defined Ratio” on page 25. For all other parameters mark a ‘0’ or ‘1’ below the parameter name. OTP Modal and Global Configuration Parameters Form Modal Configuration Set #0 Ratio 0 (dec) Ratio 0 (hex) __ __ : __ __ : __ __ : __ __ RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 AutoRMod Modal Configuration Set #1 Ratio 0 (dec) Ratio 0 (hex) __ __ : __ __ : __ __ : __ __ RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 AutoRMod Modal Configuration Set #2 Ratio 0 (dec) Ratio 0 (hex) __ __ : __ __ : __ __ : __ __ RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 AutoRMod Modal Configuration Set #3 Ratio 0 (dec) Ratio 0 (hex) __ __ : __ __ : __ __ : __ __ RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 AutoRMod Global Configuration Set ClkSkipEn AuxLockCfg RefClkDiv1 LFRatioCfg ClkIn_BW2 26 ClkIn_BW1 RefClkDiv0 ClkOutUnl M2Cfg2 M2Cfg1 M2Cfg0 ClkIn_BW0 DS841PP1 CS2100-OTP 9. PACKAGE DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1) N D E11 c E A2 e b ∝ A1 SIDE VIEW 1 2 3 A END VIEW L SEATING PLANE L1 TOP VIEW DIM MIN INCHES NOM A A1 A2 b c D E E1 e L L1 -0 0.0295 0.0059 0.0031 ----0.0157 -- -----0.1181 BSC 0.1929 BSC 0.1181 BSC 0.0197 BSC 0.0236 0.0374 REF MAX 0.0433 0.0059 0.0374 0.0118 0.0091 ----0.0315 -- MIN MILLIMETERS NOM NOTE MAX -0 0.75 0.15 0.08 ----0.40 -- -----3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.60 0.95 REF 1.10 0.15 0.95 0.30 0.23 ----0.80 -- 4, 5 2 3 Notes: 1. Reference document: JEDEC MO-187 2. D does not include mold flash or protrusions which is 0.15 mm max. per side. 3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max. 5. Exceptions to JEDEC dimension. THERMAL CHARACTERISTICS Parameter Junction to Ambient Thermal Impedance DS841PP1 JEDEC 2-Layer JEDEC 4-Layer Symbol Min Typ Max Units θJA θJA - 170 100 - °C/W °C/W 27 CS2100-OTP 10.ORDERING INFORMATION The CS2100-OTP is ordered as an un-programmed device. The CS2100-OTP can also be factory programmed for large quantity orders. Please see “Programming Information” on page 26 for more details. Product Description Package Pb-Free CS2100-OTP Clocking Device 10L-MSOP Yes CS2100-OTP Clocking Device 10L-MSOP Yes CDK2000 Evaluation Platform - Yes Grade Commercial - Temp Range Container Order# -10° to +70°C Rail CS2100P-CZZ -10° to +70°C Tape and Reel CS2100P-CZZR - - CDK-2000-CLK 11.REVISION HISTORY Release A1 PP1 Changes Initial Release Updated “AC Electrical Characteristics” on page 7 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. 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IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 28 DS841PP1