CIRRUS CS61575-IL1Z

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CS61574A
CS61575
T1/E1 Line Interface
Features
General Description
•
4HE# 3!AND # 3CO MBINET HE COMPLETE
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APPLICATIONSI NAL OWPOW ER PINDE VICEOPE RATING
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BASED ORST ANDALONEOPE RATIONAND INTERFACEW ITH
INDUSTRYSTANDARD4AND%FRAMERS
4HERECEIVERUSESADIGITAL$ELAY,OCKED,OOPWHICHIS
CONTINUOUSLYCALIBRATEDFROMACRYSTALREFERENCET OPRO
VIDEE XCELLENTS TABILITY ANDJITT ERTO LERANCE4H E
#3!HASARECEIVERJITTERATTENUATOROPTIMIZEDFOR
MINIMUMDE LAY INS WITCHINGAN DT RANSMISSION APPLICA
TIONSW HILET HE# 3AT TENUATOR IS OPTIMIZED FOR
#0%APPLICATIONSSUBJECTTO!44 REQUIREMENTS
4HET RANSMITTERF EATURESI NTERNALP ULSESHA PINGAND A
MATCHEDC ONSTANTI MPEDANCEO UTPUT STAGET O INSURE
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#3
Cirrus Logic,
Inc.
Crystal
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Corporation
http://www.cirrus.com
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Copyright ¤ Cirrus Logic, Inc. 2009
#OPYRIGHT
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(All
Rights Reserved)
!LL2IGHTS2ESERVED
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CS61574A CS61575
ABSOLUTE MAXIMUM RATINGS
Parameter
REFERENCEDTO2'.$4'.$6
Symbol
Min
Max
Units
$#3UPPLY
26
6
46
26
6
)NPUT6OLTAGE!NY0IN
.OTE
6IN
2'.$
26 6
)NPUT#URRENT!NY0IN
.OTE
)IN
M!
!MBIENT/PERATING4EMPERATURE
4!
°#
3TORAGE4EMPERATURE
4STG
°#
7!2.).'/PERATIONSATORBEYONDTHESELIMITSMAYRESULTINPERMANENTDAMAGETOTHEDEVICE
.ORMALOPERATIONISNOTGUARANTEEDATTHESEEXTREMES
.OTES %XCLUDING24)022).'WHICHMUSTSTAYWITHIN6TO266
4RANSIENTCURRENTSOFUPTOM!WILLNOTCAUSE3#2LATCHUP!LSO44)042).' 46AND4'.$
CANWITHSTANDACONTINUOUSCURRENTOFM!
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Units
$#3UPPLY
.OTE 2646
6
!MBIENT/PERATING4EMPERATURE
4!
°#
M7
0OWER#ONSUMPTION
.OTES
0#
0OWER#ONSUMPTION
.OTES
0#
M7
.OTES 46MUSTNOTEXCEED26BYMORETHAN6
0OWERCONSUMPTIONWHILEDRIVINGLINELOADOVEROPERATINGTEMPERATURERANGE)NCLUDES)#ANDLOAD
$IGITALINPUTLEVELSAREWITHINOFTHESUPPLYRAILSANDDIGITALOUTPUTSAREDRIVINGAP&
CAPACITIVELOAD
!SSUMESONESDENSITYANDMAXIMUMLINELENGTHAT6
!SSUMESONESDENSITYANDFTLINELENGTHAT6
DIGITAL CHARACTERISTICS
Parameter
4!°#TO°#46266±'.$ 6
Symbol
Min
Typ
Max
(IGH,EVEL)NPUT6OLTAGE
.OTES
6)(
0).3
,OW,EVEL)NPUT6OLTAGE
.OTES
6),
0).3
(IGH,EVEL/UTPUT6OLTAGE
.OTES
6/(
)/54 μ!
0).3
,OW,EVEL/UTPUT6OLTAGE
.OTES
6/,
)/54M!
0).3
)NPUT,EAKAGE#URRENT%XCEPT0IN
±
,OW,EVEL)NPUT6OLTAGE0).
6),
(IGH,EVEL)NPUT6OLTAGE0).
6)(
26 -ID,EVEL)NPUT6OLTAGE0).
.OTE
6)
.OTES )N%XTENDED(ARDWARE-ODEPINSANDAREDIGITALINPUTS)N(OST-ODEPINIS
ANOPENDRAINOUTPUTANDPINISATRISTATEOUTPUT
4HISSPECIFICATIONGUARANTEES44,COMPATIBILITY6 /(6 ) /54 μ!
/UTPUTDRIVERSWILLDRIVE#-/3LOGICLEVELSINTOA#-/3LOAD
!SANALTERNATIVETOSUPPLYINGATO6INPUTTHISPINMAYBELEFTFLOATING
2
Units
6
6
6
6
μ!
6
6
6
DS154F3
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ANALOG SPECIFICATIONS
Parameter
CS61574A CS61575
4!°#TO°#46266±'.$ 6
Min
Typ
Max
Units
Transmitter
!-)/UTPUT0ULSE!MPLITUDES
.OTE
6
%Ω
.OTE
6
%Ω
.OTE
6
4&##0ART
.OTE
6
4$38
.OTE
%:EROSPACELEVEL,%.
6
TRANSFORMERANDΩLOAD
6
TRANSFORMERANDΩLOAD
2ECOMMENDED/UTPUT,OADAT44)0AND42).'
Ω
*ITTER!DDED$URING2EMOTE,OOPBACK
.OTE
(ZK(Z
5)
K(ZK(Z
5)
5)
(ZK(Z
5)
"ROAD"AND
0OWERINK(ZBANDABOUTK(Z
.OTES
D"M
0OWERINK(ZBANDABOUT-(Z
.OTES
D"
REFERENCEDTOPOWERINK(ZBANDATK(Z
0OSITIVETO.EGATIVE0ULSE)MBALANCE
.OTES
4$38
D"
%AMPLITUDEATCENTEROFPULSE
%PULSEWIDTHATOFNOMINALAMPLITUDE
4RANSMITTER2ETURN,OSS
.OTES
K(ZTOK(Z
D"
K(ZTO-(Z
D"
-(ZTO-(Z
D"
4RANSMITTER3HORT#IRCUIT#URRENT
.OTES
M!2-3
Driver Performance Monitor
-4)0-2).'3ENSITIVITY
$IFFERENTIAL6OLTAGE2EQUIREDFOR$ETECTION
6
.OTES 5SINGA μ&CAPACITORINSERIESWITHTHEPRIMARYOFATRANSFORMERRECOMMENDED
INTHE!PPLICATIONSSECTION
0ULSEAMPLITUDEMEASUREDATTHEOUTPUTOFAORTRANSFORMERACROSSAΩLOADFOR
LINELENGTHSETTING,%.
0ULSEAMPLITUDEMEASUREDATTHEOUTPUTOFA TRANSFORMERACROSSA ΩLOADFORLINELENGTH
SETTING,%.
0ULSEAMPLITUDEMEASUREDATTHEOUTPUTOFA TRANSFORMERACROSSA ΩLOADFOR
LINELENGTHSETTING,%.
0ULSEAMPLITUDEMEASUREDATTHE$38CROSSCONNECTACROSSAΩLOADFORLINELENGTHSETTINGS
,%.ORUSINGATRANSFORMERANDTHELENGTHOF!7'
!"!-OREQUIVALENTCABLESPECIFIEDIN4ABLE
)NPUTSIGNALTO24)022).'ISJITTERFREE6ALUESWILLREDUCESLIGHTLYIFJITTERFREECLOCKISINPUTTO4#,+
.OTPRODUCTIONTESTED0ARAMETERSGUARANTEEDBYDESIGNANDCHARACTERIZATION
2ETURNLOSSLOG!"3ZZZZWHEREZIMPEDANCEOFTHETRANSMITTERAND
ZIMPEDANCEOFLINELOAD -EASUREDWITHAREPEATINGDATAPATTERNWITH,%.
ANDATRANSFORMERTERMINATEDWITHAΩLOADORATRANSFORMERTERMINATEDWITHA
ΩLOAD
-EASUREDBROADBANDTHROUGHAΩRESISTORACROSSTHESECONDARYOFATRANSFORMER
DURINGTHETRANSMISSIONOFANALLONESDATAPATTERNFOR,%.
DS154F3
3
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ANALOG SPECIFICATIONS
Parameter
Receiver
24)022).')NPUT)MPEDANCE
3ENSITIVITY"ELOW$38D" 6
CS61574A CS61575
4!°#TO°#46266±'.$ 6
Min
Typ
Max
Units
K
Ω
D"
M6
$ATA$ECISION4HRESHOLD
4$38
.OTE
OFPEAK
4$38
.OTE
OFPEAK
4&##0ARTAND%
.OTE
OFPEAK
!LLOWABLE#ONSECUTIVE:EROSBEFORE,/3
BITS
2ECEIVER)NPUT*ITTER4OLERANCE
.OTE
K(ZK(Z
5)
5)
K(Z
(ZANDBELOW
5)
,OSSOF3IGNAL4HRESHOLD
.OTE
6
.OTES &ORINPUTAMPLITUDEOF6 PKTO6 PK
&ORINPUTAMPLITUDEOF6 PKTO6 PKANDFROM6PKTO26
&ORINPUTAMPLITUDEOF6 PKTO6 PK
*ITTERTOLERANCEINCREASESATLOWERFREQUENCIES3EE&IGURE
4HEANALOGINPUTSQUELCHCIRCUITSHALLOPERATEWHENTHEINPUTSIGNALAMPLITUDEABOVEGROUNDONTHE
24)0AND22).'PINSFALLSWITHINTHERANGEOF6TO6 /PERATIONOFTHESQUELCHRESULTSIN
THERECOVERYOFZEROS$URINGRECEIVE,/3THE20/32.%'OR2$!4!OUTPUTSAREFORCEDLOW
4
DS154F3
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ANALOG SPECIFICATIONS
Parameter
CS61574A CS61575
4!°#TO°#46266±'.$ 6
Min
Typ
Max
Units
Jitter Attenuator
*ITTER!TTENUATION#URVE#ORNER&REQUENCY
.OTES
#3!
(Z
#3
(Z
#3!42ECEIVER*ITTER4RANSFER
.OTES
*ITTER&REQ;(Z=
!MPLITUDE;5)PP=
D"
D"
D"
D"
K
D"
KK
#342ECEIVER*ITTER4RANSFER
.OTES
*ITTER&REQ;(Z=
!MPLITUDE;5)PP=
D"
D"
D"
D"
K
D"
KK
#3!%2ECEIVER*ITTER4RANSFER
.OTES
*ITTER&REQ;(Z=
!MPLITUDE;5)PP=
D"
D"
D"
D"
K
D"
D"
KK
#3%2ECEIVER*ITTER4RANSFER
.OTES
*ITTER&REQ;(Z=
!MPLITUDE;5)PP=
D"
D"
D"
D"
D"
K
KK
D"
!TTENUATOR)NPUT*ITTER4OLERANCE
.OTES
"EFORE/NSETOF&)&//VERFLOWOR5NDERFLOW0ROTECTION
#3!
5)
#3
5)
.OTES !TTENUATIONMEASUREDATTHEDEMODULATOROUTPUTOFAN(0"WITHINPUTJITTEREQUALTOOF
MEASUREDJITTERTOLERANCEUSINGAMEASUREMENTBANDWIDTHOF(ZF(Z(ZF
(ZAND(ZFK(ZCENTEREDAROUNDTHEJITTERFREQUENCY7ITHA 02"3DATAPATTERN
#RYSTALMUSTMEETSPECIFICATIONSDESCRIBEDIN!PPENDIX!
*ITTERMEASUREDATTHEDEMODULATOROUTPUTOFAN(0!OREQUIVALENTUSINGAMEASUREMENT
BANDWIDTHNOTTOEXCEED(ZCENTEREDAROUNDTHEJITTERFREQUENCY7ITHA 02"3 DATAPATTERN
*ITTERBELOWK(ZANDWITHINTHEATTENUATORSINPUTJITTERTOLERANCEISNOTTRANSLATEDORALIASEDTO
OTHERFREQUENCIES/UTPUTJITTERINCREASESSIGNIFICANTLYWHENATTENUATORINPUTJITTERTOLERANCEIS
EXCEEDED
DS154F3
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T1 SWITCHING CHARACTERISTICS
CS61574A CS61575
4! °#TO°#46 266±
'.$6)NPUTS,OGIC6,OGIC263EE&IGURES Parameter
Symbol
Min
Typ
#RYSTAL&REQUENCY
.OTE
FC
4#,+&REQUENCY
FTCLK
4#,+0ULSE7IDTH
.OTE
TPWH
!#,+)$UTY#YCLE
TPWHTPW
!#,+)&REQUENCY
.OTE
FACLKI
2#,+$UTY#YCLE
.OTE TPWHTPW
2ISE4IME!LL$IG ITAL/UTPUTS
.OTE
TR
&ALL4IME!LL$IGITAL/UTPUTS
.OTE
TF
40/34.%'4$!4!TO4#,+&ALLING3ETUP4IME
TSU
4#,+&ALLINGTO40/34.%' 4$!4!(OLD4IME
TH
20/32.%'6ALID"EFORE2#,+&ALLING
.OTE
TSU
2$!4!6ALID"EFORE2#,+&ALLING
.OTE
TSU
20/32.%'6ALID"EFORE2#,+2ISING
.OTE
TSU
20/32.%'6ALID!FTER2#,+&ALLING
.OTE
TH
2$!4!6ALID!FTER2#,+&ALLING
.OTE
TH
20/32.%'6ALID!FTER2#,+2ISING
.OTE
TH
.OTES 4HETRANSMITTEDPULSEWIDTHDOESNOTDEPENDONTHE4#,+DUTYCYCLE
!#,+)PROVIDEDBYANEXTERNALSOURCEOR4#,+
2#,+DUTYCYCLEWILLB EORWHENJITTERATTENUATORLIMITSAREREACHED
!TMAXLOADOFM!ANDP&
(OST-ODE#,+%
%XTENDED(ARDWARE-ODE
(ARDWARE-ODEOR(OST-ODE#,+%
E1 SWITCHING CHARACTERISTICS
Max
Units
-(Z
-(Z
NS
-(Z
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
4!°#TO°#46266±
'.$6)NPUTS,OGIC6,OGIC263EE&IGURES Parameter
#RYSTAL&REQUENCY
.OTE
4#,+&REQUENCY
4#,+0ULSE7IDTH
.OTE
!#,+)$UTY#YCLE
!#,+)&REQUENCY
.OTE
2#,+$UTY#YCLE
.OTE
2ISE4IME!LL$IG ITAL/UTPUTS
.OTE
&ALL4IME!LL$IGITAL/UTPUTS
.OTE
40/34.%'4$!4!TO4#,+&ALLING3ETUP4IME
4#,+&ALLINGTO40/34.%' 4$!4!(OLD4IME
20/32.%'6ALID"EFORE2#,+&ALLING
.OTE
2$!4!6ALID"EFORE2#,+&ALLING
.OTE
20/32.%'6ALID"EFORE2#,+2ISING
.OTE
20/32.%'6ALID!FTER2#,+&ALLING
.OTE
2$!4!6ALID!FTER2#,+&ALLING
.OTE
20/32.%'6ALID!FTER2#,+2ISING
.OTE
6
Symbol
FC
FTCLK
TPWH
TPWHTPW
FACLKI
TPWHTPW
TR
TF
TSU
TH
TSU
TSU
TSU
TH
TH
TH
Min
Typ
Max
Units
-(Z
-(Z
NS
-(Z
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
DS154F3
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SWITCHING CHARACTERISTICS
CS61574A CS61575
4!°TO°#4626±
)NPUTS,OGIC6,OGIC26
Parameter
3$)TO3#,+3ETUP4IM E
3#,+TO3$)(OLD4IME
3#,+,OW4IME
3#,+(IGH4IME
3#,+2ISEAND&ALL4IME
#3TO3#,+3ETUP4IME
3#,+TO#3(OLD4IME
#3)NACTIVE4IME
3#,+TO3$/6ALID
#3TO3$/(IG H:
)NPUT6ALID4O0#3&ALLING3ETUP4IME
0#32ISINGTO)NPUT)NVALID(OLD4IME
0#3!CTIVE,OW4IME
.OTES /UTPUTLOADCAPACITANCEP&
.OTE
Symbol
Min
Typ
Max
Units
TDC
TCDH
TCL
TCH
TRT F
TCC
TCCH
TCWH
TCDV
TCDZ
TSU
TH
TPCSL
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
TR
!NY$IGITAL/UTPUT
TF
Figure 1. Signal Rise and Fall Characteristics
TPW
2#,+
T PWL
20/3
2.%'
2$!4!
"06
T SU
T PWH
%84%.$%$
(!2$7!2%
-/$%/2
(/34-/$%
#,+%
T H
(!2$7!2%
-/$%/2
(/34-/$%
#,+%
2#,+
Figure 2. Recovered Clock and Data Switching Characteristics
DS154F3
7
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CS61574A CS61575
T PW
T PWH
T PW
4#,+
T SU
T H
T PWH
40/34.%'
!#,+)
Figure 3a. Transmit Clock and Data Switching
Characteristics
Figure 3b. Alternate External Clock Characteristics
T CWH
#3
T CC
T CH
T CCH
T CL
3#,+
T CDH
T DC
3$)
,3"
T CDH
,3"
#/.42/,"94%
-3"
$!4!"94%
Figure 4. Serial Port Write Timing Diagram
#3
T CDZ
3#,+
T CDV
3$/
()'(:
#,+%
Figure 5. Serial Port Read Timing Diagram
0#3
,%.4!/3
2,//0,,//0
2#/$%4#/$%
T SU
TH
T PCSL
6!,)$).054$!4!
Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram
8
DS154F3
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CS61574A CS61575
THEORY OF OPERATION
Introduction to Operating Modes
Enhancements in CS61575 and CS61574A
The CS61574A and CS61575 support three operating modes which are selected by the level of the
MODE pin as shown in Tables 1 and 2, Figure 7,
and Figures A1-A3 of the Applications section.
The CS61574A and CS61575 provide higher performance and more features than the CS61574
including:
•
•
•
•
•
•
•
•
AT&T 62411, Stratum 4 compliant jitter attenuation over the full range of operating
frequency and jitter amplitude (CS61575),
50% lower power consumption,
Internally matched transmitter output impedance for improved signal quality,
Optional AMI, B8ZS, HDB3 encoder/decoder or external line coding support,
Receiver AIS (unframed all ones) detection,
ANSI T1.231-1993 compliant receiver
LOS (Loss of Signal) handling,
Transmitter TTIP and TRING outputs are
forced low when TCLK is static,
The Driver Performance Monitor operates
over a wider range of input signal levels.
Existing designs using the CS61574 can be converted to the higher performance, pin-compatible
CS61574A or CS61575 if the transmit transformer is replaced by a pin-compatible
transformer with a new turns ratio.
Understanding the Difference Between the
CS61575 and CS61574A
The CS61574A and CS61575 provide receiver
jitter attenuation performance optimized for different applications. The CS61575 is optimized to
attenuate large amplitude, low frequency jitter for
T1 Customer Premises Equipment (CPE) applications as required by AT&T 62411. The
CS61574A is optimized to minimize data delay in
T1 and E1 switching or transmission applications.
Refer to the "Jitter Attenuator" section for additional information.
DS154F3
The modes are Hardware Mode, Extended Hardware Mode, and Host Mode. In Hardware and
Extended Hardware Modes, discrete pins are used
to configure and monitor the device. The Extended Hardware Mode provides a parallel chip
select input which latches the control inputs allowing individual ICs to be configured using a
common set of control lines. In the Host Mode,
an external processor monitors and configures the
device through a serial interface. There are thirteen multi-function pins whose functionality is
determined by the operating mode. (see Table 2).
Hardware
Mode
Control
Method
Control
Pins
MODE
Pin
Level
Line
Coding
<0.2 V
AIS
Detection
Driver
Performance
Monitor
External
Extended
Host
Hardware
Mode
Mode
Control Pins
Serial
with Parallel Interface
Chip Select
Floating or >(RV+)-0.2
2.5 V
V
External
No
InternalAMI, B8ZS,
or HDB3
Yes
Yes
No
Yes
No
Table 1. Differences Between Operating Modes
9
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CS61574A CS61575
HARDWARE MODE
4!/3
,,//0
2,//0
,%.
#/.42/,
40/3
44)0
,).%$2)6%2
4.%'
#3"
&2!-%2
#)2#5)4
CS61575
CS61574A
42).'
-2).'
-4)0
$2)6%2-/.)4/2
$024)0
20/3
2.%'
*)44%2
!44%.5!4/2
42!.3-)4
42!.3&/2-%2
,).%2%#%)6%2
22).'
2%#%)6%
42!.3&/2-%2
EXTENDED HARDWARE MODE
4#/$%
2#/$%
4!/3 ,,//0
2,//0
0#3
,%.
#/.42/,
44)0
4$!4!
,).%$2)6%2
!-)
":3
($"
#/$%2
4OR%
2%0%!4%2
/2
-58
"06
*)44%2
!44%.5!4/2
,).%
2%#%)6%2
24)0
22).'
2%#%)6%
42!.3&/2-%2
!)3
HOST MODE
μ03%2)!,0/24
#/.42/,
42!.3-)4
42!.3&/2-%2
CS61575
CS61574A
!)3
$%4%#4
2$!4!
42).'
#,+%
#/.42/,
44)0
40/3
,).%$2)6%2
4.%'
#3"
&2!-%2
#)2#5)4
CS61575
CS61574A
$2)6%2-/.)4/2
42).'
-2).'
-4)0
$024)0
20/3
2.%'
*)44%2
!44%.5!4/2
42!.3-)4
42!.3&/2-%2
,).%2%#%)6%2
22).'
2%#%)6%
42!.3&/2-%2
Figure 7. Overview of Operating Modes
10
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%84%.$%$
&5.#4)/.
0). (!2$7!2% (!2$7!2%
40/3
4$!4!
42!.3-)44%2
4#/$%
4.%'
2.%'
"06
20/3
2$!4!
2%#%)6%2$0
$0!)3
2#/$%
-4)0
-2).'
0#3
,%.
,%.
,%.
,%.
#/.42/,
,%.
,%.
2,//0
2,//0
,,//0
,,//0
4!/3
4!/3
./2-!,):%$
!-0,)45$%
(/34
40/3
4.%'
2.%'
20/3
$0-4)0
-2).'
).4
3$)
3$/
#3
3#,+
#,+%
Table 2. Pin Definitions
The transmitter takes digital T1 or E1 input data
and drives appropriately shaped bipolar pulses
onto a transmission line. The transmit data (TPOS
& TNEG or TDATA) is supplied synchronously
and sampled on the falling edge of the input
clock, TCLK.
Either T1 (DSX-1 or Network Interface) or E1
CCITT G.703 pulse shapes may be selected.
Pulse shaping and signal level are controlled by
"line length select" inputs as shown in Table 3.
LEN2 LEN1 LEN0
Option Selected
Application
&%%4
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Table 3. Line Length Selection
DS154F3
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Figure 8. Typical Pulse Shape at DSX-1 Cross Connect
The CS61575 and CS61574A line drivers are designed to drive a 75 Ω equivalent load.
Transmitter
CS61574A CS61575
For E1 applications, the CS61574A and CS61575
drivers provide 14 dB of return loss during the
transmission of both marks and spaces. This improves signal quality by minimizing reflections
off the transmitter. Similar levels of return loss
are provided for T1 applications.
For T1 DSX-1 applications, line lengths from 0 to
655 feet (as measured from the transmitter to the
DSX-1 cross connect) may be selected. The five
partition arrangement in Table 3 meets ANSI
T1.102 and AT&T CB-119 requirements when
using #22 ABAM cable. A typical output pulse is
shown in Figure 8. These pulse settings can also
be used to meet CCITT pulse shape requirements
for 1.544 MHz operation.
For T1 Network Interface applications, two additional options are provided. Note that the optimal
pulse width for Part 68 (324 ns) is narrower than
the optimal pulse width for DSX-1 (350 ns). The
CS61575 and CS61574A automatically adjusts
the pulse width based upon the "line length" selection made.
11
-XO¶
&21),'(17,$/
0ERCENTOF
NOMINAL
PEAK
VOLTAGE
CS61574A CS61575
NS
when RLOOP is selected because the timing circuitry must adjust to the new frequency.
NS
Transmit All Ones Select
NS
.OMINAL0ULSE
The transmitter provides for all ones insertion at
the frequency of TCLK. Transmit all ones is selected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. If Remote
Loopback is in effect, any TAOS request will be
ignored.
Receiver
NS
NS
Figure 9. Mask of the Pulse at the 2048 kbps Interface
The E1 G.703 pulse shape is supported with line
length selection LEN2/1/0=0/0/0. The pulse
width will meet the G.703 pulse shape template
shown in Figure 9, and specified in Table 4.
The CS61574A and CS61575 will detect a static
TCLK, and will force TTIP and TRING low to
prevent transmission when data is not present.
When any transmit control pin (TAOS, LEN0-2
or LLOOP) is toggled, the transmitter outputs
will require approximately 22 bit periods to stabilize. The transmitter will take longer to stabilize
The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and outputs clock and synchronized data. The receiver is
sensitive to signals over the entire range of
ABAM cable lengths and requires no equalization
or ALBO (Automatic Line Build Out) circuits.
The signal is received on both ends of a centertapped, center-grounded transformer. The
transformer is center tapped on the IC side. The
clock and data recovery circuit exceeds the jitter
tolerance specifications of Publications 43802,
43801, AT&T 62411, TR-TSY-000170, and
CCITT REC. G.823.
&ORC OAX IA LC ABLE &OR SHIELDEDTWIS TED
Ω L
OA D A ND PAIR ΩL OADAND
TRANSFORMERSP ECIFIED TRANSFORMERSP ECIFIED
IN!PPLICATION3ECTION IN!PPLICATION3ECTION
6
6
±6
±6
NS
.OMINALPEAKVOLTAGEOFAMARKPULSE
0EAKVOLTAGEOFASPACENOPULSE
.OMINALPULSEWIDTH
2ATIOOFTHEAMPLITUDESOFPOSITIVEANDNEGATIVE
TO
PULSESATTHECENTEROFTHEPULSEINTERVAL
2ATIO OFT HE WIDTHS OFPOS ITIVEAND NEGATIVE
TO
PULSESATTHENOMINALHALFAMPLITUDE
7HENCONFIGUREDWITHAμ&NONPOLARIZEDCAPACITORINSERIESWITHTHE48TRANSFORMER
PRIMARYASSHOWNIN&IGURES!!AND!
Table 4. CCITT G.703 Specifications
12
DS154F3
-XO¶
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Figure 10. Receiver Block Diagram
A block diagram of the receiver is shown in Figure 10. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar signals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0 inputs).
The leading edge of an incoming data pulse triggers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The output from the phase selector feeds the clock and
data recovery circuits which generate the recovered clock and sample the incoming signal at
appropriate intervals to recover the data.
sampler will continuously sample data based on
its last input until a new pulse arrives to update
the clock phase selector.
The delay line is continuously calibrated using
the crystal oscillator reference clock. The delay
line produces 13 phases for each cycle of the reference clock. In effect, the 13 phases are
analogous to a 20 MHz clock when the reference
clock is 1.544 MHz. This implementation utilizes
the benefits of a 20 MHz clock for clock recovery
without actually having the clock present to impede analog circuit performance.
-INIMUM
0ERFORMANCE
!44
Data sampling will continue at the periods selected by the phase selector until an incoming
pulse deviates enough to cause a new phase to be
selected for data sampling. The phases of the delay line are selected and updated to allow as much
as 0.4 UI of jitter from 10 kHz to 100 kHz, without error. The jitter tolerance of the receiver
exceeds that shown in Figure 11. Additionally,
this method of clock and data recovery is tolerant
of long strings of consecutive zeros. The data
DS154F3
0%!+4/0%!+
*)44%2
UNITINTERVALS
K
*)44%2&2%15%.#9
K
K
(Z
Figure 11. Minimum Input Jitter Tolerance of Receiver
13
-XO¶
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In the Hardware Mode, data at RPOS and RNEG
should be sampled on the rising edge of RCLK,
the recovered clock. In the Extended Hardware
Mode, data at RDATA should be sampled on the
falling edge of RCLK. In the Host Mode, CLKE
determines the clock polarity for which output
data should be sampled as shown in Table 5.
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Table 5. Data Output/Clock Relationship
Loss of Signal
The receiver will indicate loss of signal after
power-up, reset or upon receiving 175 consecutive zeros. A digital counter counts received
zeros, based on RCLK cycles. A zero is received
when the RTIP and RRING inputs are below the
input comparator slicing threshold level established by the peak detector. After the signal is
removed for a period of time the data slicing
threshold level decays to approximately
300 mVpeak.
If ACLKI is present during the LOS state, ACLKI
is switched into the input of the jitter attenuator,
resulting in RCLK matching the frequency of
ACLKI. The jitter attenuator buffers any instantaneous changes in phase between the last
recovered clock and the ACLKI reference clock.
This means that RCLK will smoothly transition
to the new frequency. If ACLKI is not present,
then the crystal oscillator of the jitter attenuator is
14
CS61574A CS61575
forced to its center frequency. Table 6 shows the
status of RCLK upon LOS.
#RYSTAL
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!#,+)
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Table 6. RCLK Status at LOS
Jitter Attenuator
The jitter attenuator reduces wander and jitter in
the recovered clock signal. It consists of a 32 or
192-bit FIFO, a crystal oscillator, a set of load
capacitors for the crystal, and control logic. The
jitter attenuator exceeds the jitter attenuation requirements of Publications 43802 and REC.
G.742. A typical jitter attenuation curve is shown
in Figure 12. The CS61575 fully meets AT&T
62411 jitter attenuation requirements. The
CS61574A will have a discontinuity in the jitter
transfer function when the incoming jitter amplitude exceeds approximately 23 UIs.
The jitter attenuator works in the following manner. The recovered clock and data are input to the
FIFO with the recovered clock controlling the
FIFO’s write pointer. The crystal oscillator controls the FIFO’s read pointer which reads data out
of the FIFO and presents it at RPOS and RNEG
(or RDATA). RCLK is equivalent to the oscillator’s output. By changing the load capacitance
that the IC presents to the crystal, the oscillatior
frequency (and RCLK) is adjusted to the average
frequency of the recovered signal. Logic determines the phase relationship between the read and
write pointers and decides how to adjust the load
capacitance of the crystal. Jitter is absorbed in the
FIFO according to the jitter transfer characteristic
shown in Figure 12.
DS154F3
-XO¶
&21),'(17,$/
A-INIMUM!TTENUATION,IMIT
!TTENUATIONIND"
2EQUIREMENTS
B-AXIMUM
!TTENUATION
,IMIT
-EASURED0ERFORMANCE
K
K
&REQUENCYIN(Z
Figure 12. Typical Jitter Transfer Function
The FIFO in the jitter attenuator is designed to
prevent overflow and underflow. If the jitter amplitude becomes very large, the read and write
pointers may get very close together. Should they
attempt to cross, the oscillator’s divide by four
circuit adjusts by performing a divide by 3 1/2 or
divide by 4 1/2 to prevent the overflow or underflow. During this activity, data will never be lost.
The difference between the CS61575 and
CS61574A is the depth of the FIFO in the jitter
attenuator. The CS61575 has a 192-bit FIFO
which allows it to attenuate large amplitude, low
frequency jitter as required by AT&T 62411 (e.g.,
28 UIpp @ 300 Hz). This makes the CS61575
ideal for use in T1 Customer Premises Equipment
which must be compatible with AT&T 62411 requirements. In single-line Stratum 4, Type II
systems which are loop-timed, he CS61575 recovered clock can be used as the transmit clock
eliminating the need for an external system clock
synchronizer. In Stratum 4, Type I systems which
transfer timing and require a clock synchronizer,
the CS61575 simplifies the design of the synchronizer by absorbing large amplitude low frequency
jitter before it reaches the synchronizer.
DS154F3
CS61574A CS61575
The CS61574A has a 32-bit FIFO which allows it
to absorb jitter with minimum data delay in T1
and E1 switching or transmission applications.
The CS61574A will tolerate large amplitude jitter
by tracking rather than attenuating it, preventing
data errors so that the jitter may be absorbed in
external frame buffers. With large amplitude input
jitter, the CS61574A jitter transfer function may
exhibit some jitter peaking, but will offer performance comparable to the CS61574.
The jitter attenuator may be bypassed by pulling
XTALIN to RV+ through a 1 kΩ resistor and providing a 1.544 MHz (or 2.048 MHz) clock on
ACLKI. RCLK may exhibit quantization jitter of
approximately 1/13 UIpp and a duty cycle of approximately 30% (70%) when the attenuator is
disabled.
Local Loopback
Local loopback is selected by taking LLOOP, pin
27, high or by setting the LLOOP register bit via
the serial interface.
The local loopback mode takes clock and data
presented on TCLK, TPOS, and TNEG (or
TDATA), sends it through the jitter attenuator and
outputs it at RCLK, RPOS and RNEG (or
RDATA). If the jitter attenuator is disabled, it is
bypassed. Inputs to the transmitter are still transmitted on TTIP and TRING, unless TAOS has
been selected in which case, AMI-coded continuous ones are transmitted at the TCLK frequency.
The receiver RTIP and RRING inputs are ignored
when local loopback is in effect.
15
-XO¶
&21),'(17,$/
mally low, and goes high upon detecting a driver
failure.
Remote Loopback
Remote loopback is selected by taking RLOOP,
pin 26, high or by setting the RLOOP register bit
via the serial interface.
In remote loopback, the recovered clock and data
input on RTIP and RRING are sent through the
jitter attenuator and back out on the line via TTIP
and TRING. Selecting remote loopback overrides
any TAOS request (see Table 7). The recovered
incoming signals are also sent to RCLK, RPOS
and RNEG (or RDATA). Simultaneous selection
of local and remote loopback modes is not valid
(see Reset).
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INPUTISIGNOREDWHENTHEINDICATEDLOOPBACK
ISINEFFECT
,OGICINDICATESTHAT,OOPBACKOR!LL/NES
OPTIONISSELECTED
Table 7. Interaction of RLOOP with TAOS
In the Extended Hardware Mode the transmitted
data is looped before the AMI/B8ZS/HDB3 encoder/decoder during remote loopback so that the
transmitted signal matches the received signal,
even in the presence of received bipolar violations. Data output on RDATA is decoded,
however, if RCODE is low.
Driver Performance Monitor
To aid in early detection and easy isolation of
non-functioning links, the IC is able to monitor
transmit drive performance and report when the
driver is no longer operational. This feature can
be used to monitor either the device’s performance or the performance of a neighboring driver.
The driver performance monitor indicator is nor16
CS61574A CS61575
The driver performance monitor consists of an activity detector that monitors the transmitted signal
when MTIP is connected to TTIP and MRING is
connected to TRING. DPM will go high if the
absolute difference between MTIP and MRING
does not transition above or below a threshold
level within a time-out period. In the Host Mode,
DPM is available from both the register and pin
11.
Whenever more than one line interface IC resides
on the same circuit board, the effectiveness of the
driver performance monitor can be maximized by
having each IC monitor performance of a neighboring IC, rather than having it monitor its own
performance. Note that a CS61574A or CS61575
can not be used to monitor a CS61574 due to output stage differences.
Line Code Encoder/Decoder
In the Extended Hardware Mode, three line codes
are available: AMI, B8ZS and HDB3. The input
to the encoder is TDATA. The outputs from the
decoder are RDATA and BPV (Bipolar Violation
Strobe). The encoder and decoder are selected
using the LEN2, LEN1, LEN0, TCODE and
RCODE pins as shown in Table 8.
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Table 8. Encoder/Decoder Selection
DS154F3
-XO¶
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Alarm Indication Signal
In the Extended Hardware Mode, the receiver sets
the output pin AIS high when less than 9 zeros
are detected out of 8192 bit periods. AIS returns
low when 9 or more zeros are detected out of
8192 bit periods.
Parallel Chip Select
In the Extended Hardware Mode, PCS can be
used to gate the digital control inputs: TCODE,
RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP
and TAOS. Inputs are accepted on these pins only
when PCS is low and will immediately change
the operating state of the device. Therefore, when
cycling PCS to update the operating state, the
digital control inputs should be stable for the entire PCS low period. The digital control inputs are
ignored when PCS is high.
Power On Reset / Reset
Upon power-up, the IC is held in a static state
until the supply crosses a threshold of approximately 3 Volts. When this threshold is crossed,
the device will delay for about 10 ms to allow the
power supply to reach operating voltage. After
this delay, calibration of the delay lines used in
the transmit and receive sections commences. The
delay lines can be calibrated only if a reference
clock is present. The reference clock for the receiver is provided by the crystal oscillator, or
ACLKI if the oscillator is disabled. The reference
clock for the transmitter is provided by TCLK.
The initial calibration should take less than
20 ms.
In operation, the delay lines are continuously calibrated, making the performance of the device
independent of power supply or temperature variations. The continuous calibration function
forgoes any requirement to reset the line interface
when in operation. However, a reset function is
available which will clear all registers.
DS154F3
CS61574A CS61575
In the Hardware and Extended Hardware Modes,
a reset request is made by simultaneously setting
both the RLOOP and LLOOP pins high for at
least 200 ns. Reset will initiate on the falling edge
of the reset request (falling edge of RLOOP and
LLOOP). In the Host Mode, a reset is initiated by
simultaneously writing RLOOP and LLOOP to
the register. In either mode, a reset will set all registers to 0 and force the oscillator to its center
frequency before initiating calibration. A reset
will also set LOS high.
Serial Interface
In the Host Mode, pins 23 through 28 serve as a
microprocessor/microcontroller interface. One
on-board register can be written to via the SDI
pin or read from via the SDO pin at the clock rate
determined by SCLK. Through this register, a
host controller can be used to control operational
characteristics and monitor device status. The serial port read/write timing is independent of the
system transmit and receive timing.
Data transfers are initiated by taking the chip select input, CS, low (CS must initially be high).
Address and input data bits are clocked in on the
rising edge of SCLK. The clock edge on which
output data is stable and valid is determined by
CLKE as shown in Table 5. Data transfers are terminated by setting CS high. CS may go high no
sooner than 50 ns after the rising edge of the
SCLK cycle corresponding to the last write bit.
For a serial data read, CS may go high any time
to terminate the output.
Figure 13 shows the timing relationships for data
transfers when CLKE = 1. When CLKE = 1, data
bit D7 is held until the falling edge of the 16th
clock cycle. When CLKE = 0, data bit D7 is held
until the rising edge of the 17th clock cycle. SDO
goes High-Z after CS goes high or at the end of
the hold period of data bit D7.
17
-XO¶
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CS61574A CS61575
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Figure 13. Input/Output Timing
An address/command byte, shown in Table 9, precedes a data register. The first bit of the
address/command byte determines whether a read
or a write is requested. The next six bits contain
the address. The line interface responds to address
16 (0010000). The last bit is ignored.
,3"FIRSTBIT
-3"LASTBIT
27
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Table 9. Address/Command Byte
The data register, shown in Table 10, can be written to the serial port. Data is input on the eight
clock cycles immediately following the address/command byte. Bits 0 and 1 are used to
clear an interrupt issued from the INT pin, which
occurs in response to a loss of signal or a problem
with the output driver.
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4RANSMIT!LL/NES3ELECT
Table 10. Input Data Register
18
Writing a "1" to either "Clear LOS" or "Clear
DPM" over the serial interface has three effects:
1) The current interrupt on the serial interface
will be cleared. (Note that simply reading
the register bits will not clear the interrupt).
2) Output data bits 5, 6 and 7 will be reset as
appropriate.
3) Future interrupts for the corresponding LOS
or DPM will be prevented from occurring.
Writing a "0" to either "Clear LOS" or "Clear
DPM" enables the corresponding interrupt for
LOS or DPM.
Output data from the serial interface is presented
as shown in Tables 11 and 12. Bits 2, 3 and 4 can
be read to verify line length selection. Bits 5, 6
and 7 must be decoded. Codes 101, 110 and 111
(Bits 5, 6 and 7) indicate intermittent loss of signal and/or driver problems.
SDO goes to a high impedance state when not in
use. SDO and SDI may be tied together in applications where the host processor has a
bi-directional I/O port.
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Table 11. Output Data Bits 0 - 4
DS154F3
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CS61574A CS61575
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Schematic & Layout Review Service
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Table 12. Coding for Serial Output bits 5,6,7
Power Supply
The device operates from a single +5 Volt supply.
Separate pins for transmit and receive supplies
provide internal isolation. These pins should be
connected externally near the device and decoupled to their respective grounds. TV+ must not
exceed RV+ by more than 0.3V.
Decoupling and filtering of the power supplies is
crucial for the proper operation of the analog circuits in both the transmit and receive paths. A 1.0
μF capacitor should be connected between TV+
and TGND, and a 0.1 μF capacitor should be connected between RV+ and RGND. Use mylar or
ceramic capacitors and place them as closely as
possible to their respective power supply pins. A
68 μF tantalum capacitor should be added close
to the RV+/RGND supply. Wire-wrap breadboarding of the line interface is not recommended
because lead resistance and inductance serve to
defeat the function of the decoupling capacitors.
DS154F3
19
-XO¶
&21),'(17,$/
CS61574A CS61575
PIN DESCRIPTIONS
Hardware Mode
ACLKI TAOS
TCLK LLOOP
TPOS
RLOOP
+DUGZDUH0RGH
TNEG LEN2
MODE LEN1
RNEG LEN0
RPOS RGND
RCLK RV+
XTALIN RRING
XTALOUT RTIP
DPM MRING
LOS MTIP
TTIP TRING
TGND TV+
ACLKI
TCLK
TAOS
TPOS
LLOOP
TNEG
RLOOP
MODE
LEN2
RNEG
RPOS
RCLK
XTALIN
XTALOUT
TOP
VIEW
LEN1
LEN0
RGND
RV+
RRING
DPM
RTIP
LOS
MRING
TTIP
MTIP
TGND
TRING
TV+
20
DS154F3
-XO¶
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CS61574A CS61575
Extended Hardware Mode
ACLKI TAOS
TCLK LLOOP
TDATA
RLOOP
([WHQGHG+DUGZDUH0RGH
TCODE LEN2
MODE LEN1
BPV LEN0
RDATA RGND
RCLK RV+
XTALIN RRING
XTALOUT RTIP
AIS PCS
LOS RCODE
TTIP TRING
TGND TV+
ACLKI
TCLK
TAOS
TDATA
LLOOP
TCODE
RLOOP
MODE
BPV
RDATA
RCLK
XTALIN
XTALOUT
LEN2
TOP
VIEW
LEN1
LEN0
RGND
RV+
RRING
AIS
RTIP
LOS
PCS
TTIP
RCODE
TGND
TRING
TV+
DS154F3
21
-XO¶
&21),'(17,$/
CS61574A CS61575
Host Mode
ACLKI CLKE
TCLK SCLK
TPOS CS
([WHQGHG+DUGZDUH0RGH
TNEG SDO
MODE SDI
RNEG INT
RPOS RGND
RCLK RV+
XTALIN RRING
XTALOUT RTIP
DPM MRING
LOS MTIP
TTIP TRING
TGND TV+
ACLKI
TCLK
CLKE
TPOS
SCLK
TNEG
CS
MODE
SDO
RNEG
RPOS
RCLK
XTALIN
XTALOUT
TOP
VIEW
SDI
INT
RGND
RV+
RRING
DPM
RTIP
LOS
MRING
TTIP
MTIP
TGND
TRING
TV+
22
DS154F3
-XO¶
&21),'(17,$/
CS61574A CS61575
Power Supplies
RGND - Ground, Pin 22.
Power supply ground for all subcircuits except the transmit driver; typically 0 Volts.
RV+ - Power Supply, Pin 21.
Power supply for all subcircuits except the transmit driver; typically +5 Volts.
TGND - Ground, Transmit Driver, Pin 14.
Power supply ground for the transmit driver; typically 0 Volts.
TV+ - Power Supply, Transmit Driver, Pin 15.
Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than
0.3 V.
Oscillator
XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.
A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or
2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying
XTALIN, Pin 9 to RV+ through a 1 kΩ resistor, and floating XTALOUT, Pin 10.
Overdriving the oscillator with an external clock is not supported. See Appendix A.
Control
ACLKI - Alternate External Clock Input, Pin 1.
A 1.544 MHz (or 2.048 MHz) clock may be input to ACLKI, or this pin must be tied to ground.
During LOS, the ACLKI input signal, if present, is output on RCLK through the jitter attenuator.
CLKE - Clock Edge, Pin 28. (Host Mode)
Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and
SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS
and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of
SCLK.
CS - Chip Select, Pin 26. (Host Mode)
This pin must transition from high to low to read or write the serial port.
INT - Receive Alarm Interrupt, Pin 23. (Host Mode)
Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing
"clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the
power supply through a resistor.
DS154F3
23
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CS61574A CS61575
LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended
Hardware Modes)
Determines the shape and amplitude of the transmitted pulse to accommodate several cable types
and lengths. See Table 3 for information on line length selection. Also controls the receiver
slicing level and the line code in Extended Hardware Mode.
LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes)
Setting LLOOP to a logic 1 routes the transmit clock and data through the jitter attenuator to the
receive clock and data pins. TCLK and TPOS/TNEG (or TDATA) are still transmitted unless
overridden by a TAOS request. Inputs on RTIP and RRING are ignored.
MODE - Mode Select, Pin 5.
Driving the MODE pin high puts the line interface in the Host Mode. In the host mode, a serial
control port is used to control the line interface and determine its status. Grounding the MODE
pin puts the line interface in the Hardware Mode, where configuration and status are controlled
by discrete pins. Floating the MODE pin or driving it to +2.5 Vselects the Extended Hardware
Mode, where configuration and status are controlled by discrete pins. When floating MODE,
there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2).
PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode)
Setting PCS high causes the line interface to ignore the TCODE, RCODE, LEN0, LEN1, LEN2,
RLOOP, LLOOP and TAOS inputs.
RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode)
Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting
RCODE high enables the AMI receiver decoder (see Table 8).
RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes)
Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter
attenuator (if active) and through the driver back to the line. The recovered signal is also sent to
RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored.
Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset.
SCLK - Serial Clock, Pin 27. (Host Mode)
Clock used to read or write the serial port registers. SCLK can be either high or low when the line
interface is selected using the CS pin.
SDI - Serial Data Input, Pin 24. (Host Mode)
Data for the on-chip register. Sampled on the rising edge of SCLK.
SDO - Serial Data Output, Pin 25. (Host Mode)
Status and control information from the on-chip register. If CLKE is high SDO is valid on the
rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to
a high-impedance state when the serial port is being written to or after bit D7 is output.
24
DS154F3
-XO¶
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CS61574A CS61575
TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes)
Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined
by TCLK.
TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode)
Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting
TCODE high enables the AMI transmitter encoder .
Data
RCLK - Recovered Clock, Pin 8.
The receiver recovered clock generated by the jitter attenuator is output on this pin.When in the
loss of signal state ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is
not present during LOS, RCLK is forced to the center frequency of the crystal oscillator..
RDATA - Receive Data - Pin 7. (Extended Hardware Mode)
Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the
line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK.
RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host
Modes)
The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS
and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines
the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse
(with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive
pulse received on the RRING pin generates a logic 1 on RNEG.
RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20.
The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up
transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data
and clock are recovered and output on RCLK and RPOS/RNEG or RDATA.
TCLK - Transmit Clock, Pin 2.
The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are
sampled on the falling edge of TCLK.
TDATA - Transmit Data, Pin 3. (Extended Hardware Mode)
Transmitter NRZ input data which passes through the line code encoder, and is then driven on to
the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK.
TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and
Host Modes)
Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and
TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a
positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted.
DS154F3
25
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CS61574A CS61575
TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16.
The AMI signal is driven to the line through these pins. The transmitter output is designed to
drive a 75 Ω load between TTIP and TRING. A transformer is required as shown in Table A1.
Status
AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode)
AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection
criteria of less than three zeros out of 2048 bit periods.
BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode)
BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3)
zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been
enabled.
DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes)
DPM goes high if no activity is detected on MTIP and MRING.
LOS - Loss of Signal, Pin 12.
LOS goes high when 175 consecutive zeros have been received. LOS returns low when the ones
density reaches 12.5% (based upon 175 bit periods starting with a one and containing less than
100 consectutive zeros) as prescribed in ANSI T1.231-1993. When in the loss of signal state
RPOS/RNEG or RDATA are forced low, and ACLKI (if present) is output on RCLK via the jitter
attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the
crystal oscillator.
MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes)
These pins are normally connected to TTIP and TRING and monitor the output of a line interface
IC. If the INT pin in the host mode is used, and the monitor is not used, writing "clear DPM" to
the serial interface will prevent an interrupt from the driver performance monitor.
Ordering Guide
Model
#3)0
#3),Z
#3!)0
#3!),Z
26
Frequency
4%
T%1
4%
T%
FIFO Depth (Bits)
12
3
Package
PIN0LASTIC$)0
2PIN0,##, Lead-free
PIN0LASTIC$)0
PIN0,##, Lead-free
DS154F3
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28 pin
Plastic DIP
%
$
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$)-%.3)/.E!4/#%.4%2/&,%!$37(%.&/2-%$0!2!,,%,
$)-%.3)/.%$/%3./4).#,5$%-/,$&,!3(
CS61574A CS61575
MILLIMETERS
INCHES
DIM MIN NOM MAX MIN NOM MAX
A
A1 B
B1 C
D
E1 e1 eA L
∝
28-pin PLCC
28
% %
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MILLIMETERS
INCHES
MIN NOM MAX
MIN NOM MAX
A1
B
D/E $
D1/E1 $
D2/E2 e
"
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CS61574A CS61575
APPLICATIONS
6
μ&
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26
&RAME
&ORMAT
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46
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4'.$
26
#,+%
20/3
84,
μ&
40/3
CS61574A
OR
CS61575
IN
HOST
MODE
24)0
84!,/54
2'.$
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0ORT
22).'
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Figure A1. T1 Host Mode Configuration
Frequency
MHz
1.544 (T1)
2.048 (E1)
Cable
Ω
100
120
75
R1 and R2
Transmit
Crystal
Transformer
XTL
Ω
200
1:1.15
6.176 MHz
240
1:1.26
8.192 MHz
150
1:1
Table A1. External Component Values
Line Interface
Figures A1-A3 show typical T1 and E1 line interface application circuits. Table A1 shows the
external components which are specific to each
application. Figure A1 illustrates a T1 interface in
the Host Mode. Figure A2 illustrates a 120 Ω E1
interface in the Hardware Mode. Figure A3 illustrates a 75 Ω E1 interface in the Extended
Hardware Mode
The receiver transformer has a grounded center
tap on the IC side. Resistors between the RTIP
28
and RRING pins to ground provide the termination for the receive line.
The transmitter transformer matches the 75 Ω
transmitter output impedance to the line impedance. Figures A1-A3 show a 0.47 μF capacitor in
series with the transmit transformer primary. This
capacitor is needed to prevent any output stage
imbalance from resulting in a DC current through
the transformer primary. This current might saturate the transformer producing an output offset
level shift.
DS154F3
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CS61574A CS61575
6
μ&
2'.$
#ONTROL
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4!/3
!#,+)
26
4'.$
46
2,//0
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20/3
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OR
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MODE
-/$%
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2
2
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4#,+
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Figure A2. 120 Ω, E1 Hardware Mode Configuration
6
μ&
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26
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CS61574A
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HARDWARE
MODE
4#,+
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2
2
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22).'
84!,).
84!,/54
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Figure A3. 75 Ω, E1 Extended Hardware Mode Configuration
DS154F3
29
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CS61574A CS61575
Parameter
Turns Ratio
Receiver
Transmitter
1:2 CT ± 5%
Primary Inductance
600 μH min. @ 772 kHz
1:1 ± 1.5 % for 75 Ω E1
1:1.15 ± 5 % for 100 Ω T1
1:1.26 ± 1.5 % for 120 Ω E1
1.5 mH min. @ 772 kHz
Primary Leakage Inductance
1.3 μH max. @ 772 kHz
0.4 μH max. @ 772 kHz
23 pF max.
0.3 μH max. @ 772 kHz
0.4 μH max. @ 772 kHz
18 pF max.
16 V-μs min. for T1
12 V-μs min. for E1
16 V-μs min. for T1
12 V-μs min. for E1
Secondary Leakage Inductance
Interwinding Capacitance
ET-constant
Table A2. Transformer Specifications
Transformers
Designing for AT&T 62411
Recommended transmitter and receiver transformer specifications are shown in Table A2. The
transformers in Table A3 have been tested and
recommended for use with the CS61574A and
CS61575. Refer to the "Telecom Transformer Selection Guide" for detailed schematics which
show how to connect the line interface IC with a
particular transformer.
For additional information on the requirements of
AT&T 62411 and the design of an appropriate
system synchronizer, please refer to the Crystal
Semiconductor Application Notes: "AT&T 62411
Design Considerations – Jitter and Synchronization" and "Jitter Testing Procedures for
Compliance with AT&T 62411".
Transmit Side Jitter Attenuation
In applications where it is advantageous to use a
single transmitter transformer for 75Ω and 120Ω
E1 applications, a 1:1.26 transformer may be
used. Although transmitter return loss will be reduced for 75Ω applications, the pulse amplitude
will be correct across a 75Ω load.
Selecting an Oscillator Crystal
Specific crystal parameters are required for
proper operation of the jitter attenuator. It is recommended that a 6.176 MHz
crystal be used for T1 applications and a
8.192 MHz crystal be used for E1 applications.
30
In some applications it is desirable to attenuate
jitter from the signal to be transmitted. A
CS61575 in local loopback mode can be used as a
jitter attenuator. The inputs to the jitter attenuator
are TPOS, TNEG, TCLK. The outputs from the
jitter attenuator are RPOS, RNEG and RCLK.
Line Protection
Secondary protection components can be added
to provide lightning surge and AC power-cross
immunity. Refer to the application note "Secondary Line Protection for T1 and E1 Line Cards"
for detailed information on the different electrical
safety standards and specific application circuit
recommendations.
DS154F3
-XO¶
&21),'(17,$/
Application
RX:
T1 & E1
Turns
Ratio(s)
1:2CT
TX:
T1
1:1.15
TX:
E1 (75 & 120 Ω)
1:1.26
1:1
RX &TX:
T1
RX &TX:
E1 (75 & 120 Ω)
1:2CT
1:1.15
1:2CT
1:1.26
1:1
1:2CT
1:1.15
1:2CT
1:1.26
1:1
1:2CT
RX &TX:
T1
RX &TX:
E1 (75 & 120 Ω)
RX :
T1 & E1
TX:
E1 (75 & 120 Ω)
1:1.26
1:1
CS61574A CS61575
Manufacturer
Part Number
Package Type
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Bel Fuse
Pulse Engineering
Bel Fuse
PE-65351
67129300
0553-0013-HC
PE-65388
67129310
0553-0013-RC
PE-65389
67129320
0553-0013-SC
PE-65565
0553-0013-7J
PE-65566
0553-0013-8J
1.5 kV through-hole, single
Pulse Engineering
Bel Fuse
Pulse Engineering
Bel Fuse
PE-65765
S553-0013-06
PE-65766
S553-0013-07
Pulse Engineering
PE-65835
Pulse Engineering
PE-65839
1.5 kV through-hole, single
1.5 kV through-hole, single
1.5 kV through-hole, dual
1.5 kV through-hole, dual
1.5 kVsurface-mount, dual
1.5 kV surface-mount, dual
3 kV through-hole, single
EN60950, EN41003 approved
3 kV through-hole, single
EN60950, EN41003 approved
Table A3. Recommended Transformers
Interfacing The CS61575 and CS61574A With
the CS62180B T1 Transceiver
To interface with the CS62180B, connect the devices as shown in Figure A4. In this case, the line
interface and CS62180B are in Host Mode controlled by a microprocessor serial interface. If the
line interface is used in Hardware Mode, then the
line interface RCLK output must be inverted before being input to the CS62180B. If the
CS61575 or CS61574A is used in Extended
Hardware Mode, the RCLK output does not have
to be inverted before being input to the
CS62180B.
4/(/34#/.42/,,%2
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2.%'
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K
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6
K
6
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Figure A4. Interfacing the CS61574A or CS61575
with a CS62180B (Host Mode)
DS154F3
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Cirrus Logic telecommunication devices that offer jitter attenuation require crystals with specifications for
frequency pullability. The crystal oscillation frequency is dictated by capacitive loading, which is controlled by the chip. Therefore, the crystals must meet the following specifications.
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Total Frequency Range
Operating Frequency
Cload = 11.6 pF
Cload = 19.0 pF
Cload = 37.0 pF
0LQ
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8QLWV
(Note 1)
-
370
390
ppm
(Note 2)
(Note 3)
(Note 2)
6.176803
6.175846
-
6.176000
-
6.176154
6.175197
MHz
MHz
MHz
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Total Frequency Range
Operating Frequency
Notes:
Cload = 11.6 pF
Cload = 19.0 pF
Cload = 37.0 pF
0LQ
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0D[
8QLWV
(Note 1)
-
210
245
ppm
(Note 2)
(Note 3)
(Note 2)
8.192410
8.191795
-
8.192000
-
8.192205
8.191590
MHz
MHz
MHz
1. With Cload varying from 11.6 to 37.0 pF at a given temperature.
2. Measured at -40 to 85°C.
3. Measured with Saunders 150D meter at 25 °C.
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For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to KWWSZZZFLUUXVFRP
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