MH89792 E1 Transceiver Preliminary Information Features ISSUE 3 April 1995 Ordering Information • Complete primary rate 2048kb/s CEPT line driver and receiver MH89792-1 MH89792-2 MH89792-3 • Onboard pulse transformers for transmit and receive • Meets latest ETSI requirements (ETSI ETS 300 011 (NET 5)) • Inductorless clock recovery • Loss of signal indication/ polarity selection • Programmable polarity of extracted clock & receive data • Single +5V operation • Compatible with all E1 framers • Small footprint area (<330mm 2) 0°C to 70°C Description The Mitel MH89792 is a low cost E1 line driver/ receiver with clock extraction requiring no external components. There are three versions available: MH89792-1 for 120Ω twisted pair cable; MH89792-2 for 75Ω co-axial links; MH89792-3 for 100Ω digital twisted pair. Applications • 20 Pin SIL Package 20 Pin SIL Package 20 Pin SIL Package Primary rate ISDN network Interface • Multiplexer equipment • Private Network links • Isochronous LANS/WANS VDD TxA TxB VSS Line Driver Transmit Isolation Transformer 6dB Pad TLA TLB E2o LOSP CLKF/ CLKR RxINV Polarity Selection Clock/Data Clock Recovery Receive Isolation Transformer RxA RxB LOS RLA RLB Line Receiver RxD EQUIPMENT SIDE LINE SIDE Figure 1 - Functional Block Diagram 4-223 MH89792 Preliminary Information E2o VDD RxA RxB VSS RxD RxINV CLKF/CLKR LOS LOSP NC RLA RLB TLA TLB NC NC NC TxA TxB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 2 - Pin Connections Pin Description Pin # Name Description 1 E2o 2048kHz Extracted clock (Output). This clock is extracted by the device from the received signal. It is used internally to clock in data received from RLA and RLB. 2 VDD D.C. Power (Input) +5V supply 3 RxA Receiver A (Output). The bipolar CEPT signal received by the device at RLA and RLB inputs is converted to a unipolar format and output at this pin. This pin should be connected to the positive receive pin of the framer. 4 RxB Receiver A (Output). This pin should be connected to the negative receive gain pin of the framer and provides a signal of the same format as RxA. 5 VSS Ground (Input). D.C. power return path. 6 RxD Received Data (Output) This unipolar return to zero format signal is the product of RxA and RxB logically “OR” ed and is required by some framers. 7 RxINV RxA/RxB inversion (Input). A logic low applied to this pin will invert the outputs RxA and RxB. A logic high should be applied if no inversion is required. 8 CLKF/ CLKR E2o phase selection is achieved by use of this pin. A logic low provides E2o with a falling edge coinciding with the centre of the data bit. A logic high provides E2o with a rising edge. 9 LOS Loss of signal (Output). This pin goes low when 128 continuous zeros are received on the RLA and RLB inputs. When RxINV and LOS are low RxA and RxB are forced high. When RxINV is high and LOS is low RxA and RxB are forced low. LOS is reset when 64 ones are received in two dual E1 framer periods. 10 LOSP Loss of signal Polarity (Input). A logic low applied to this pin will invert LOS. A logic high should be applied when LOS is required. 11 NC No connection. This pin is not fitted. 12 RLA Received Line A (Input). The A wire or Tip Connection of the E1 receive line should be connected to this pin. 13 RLB Receive Line B (Input). The B wire or Ring connection of the E1 receive line should be connected to this pin. 4-224 MH89792 Preliminary Information Pin Description (Continued) Pin # Name Description 14 TLA Transmit Line B (Output). The B wire of Ring connection of the E1 receive line should be connected to this pin. 15 TLB Transmit Line B (Output). The B wire or Tip connection of the E1 receive line should be connected to this pin. 16 NC No Connection. This pin is not fitted. 17 NC No Connection. This pin is not fitted. 18 NC No Connection. This pin is not fitted. 19 TXA Transmit A (Input). A unipolar signal from the framer device used in conjunction with TxB is used to generate the bipolar output signal. 20 TXB Transmit B (Input). A unipolar signal from the framer device used in conjunction with TxA is used to generate the bipolar output signal. Functional Description Bipolar Line Transmitter The MH89792 is a E1 digital trunk interface which when used with an approved framer will conform to CCITT recommendation G.703 for PCM30 and I.431 for the ISDN. The functions provided include line driver and receive circuitry, inductorless clock recovery, data and clock polarity selection and loss of signal indication. The MH89792 transmitter interfaces to the transmission line through an internal pulse transformer which combines the TxA and TxB data into an AMI line coded signal. This is then passed through the 6dB pad prior to being applied to the line. Bipolar Line Receiver Clock Extractor The MH89792 receiver interfaces to the transmission line through an internal pulse transformer which splits the received AMI lines signal into RxA and RxB. These two signals are combined by internal logic to form a new signal which represents the received data, RxD. The signals RxA and RxB may be inverted where required by applying a logic low signal permanently to pin 7, (RxINV). RxD will not be affected by use of this pin. The MH89792 contains a clock extraction circuit which generates the E2o clock from the received data without the use of external crystals or a tunable inductor. The input impedance seen by the transmission line is about 120 ohms when using the -1 variant for twisted pair applications, about 75 ohms when using the -2 variant for coaxial cable applications, and is about 100 ohms when using the -3 variant for digital twisted pair applications. Attenuation of the transmission line shall not exceed 6dB (at 1024kHz) and attenuation characteristics shall be close to the “square root of f” Af (dB) = AFref (dB)* √f fref Where: AF - attenuation at frequency f in dB AFref - attenuation at frequency fref in dB (in kHz) fref - reference frequency (in this case 1024) kHz f - frequency in kHz The edge of the E2o extracted clock approximately aligns with the centre of the received data pulse and can be configured as either rising or falling edge by the use of pin 8. (CLKF/CLKR). Loss of Signal The circuitry on the MH89792 is capable of detecting 128 continuous ZEROs received on RLA and RLB and indicating this condition as a logic low on pin 9, (LOS). When LOS and RxINV are low RxA and RxB are forced high, when LOS is low and RxINV is high RxA and RxB are forced low LOS will not reset until 64 ONEs are received in a two E1 frame period. LOS may be inverted by applying a logic low to pin 10, (LOSP). 4-225 MH89792 Preliminary Information INT MH89792-1 MT8979 9 XSt DSTi 19 DSTo TxA CSTio 20 TxB TLA LOS TLB 14 Twisted Pair 15 TxA TxB CSTo CSTi1 C2i 6 RxD 3 RxA 4 1 RxB E2o RxINV VSS 5 7 RxD RxA RxB F0i E2i 12 RLA Twisted Pair RLB 13 CLKF/ CLKR 8 VDD LOSP 2 10 Coax Connection -2 Version only Coax Connection -2 Version only MT9042 MT8941 +5V Figure 3a - Application Circuit VDD 10K +5 +5 0.1µ 1 33 2 41 RESET TAIS VDD DSTi DSTo MH89792-1 16 35 TxMF TxA 43 19 42 20 TxB 32 E8Ko VDD RLA TLA TLB RLB TxA TxB 2 12 14 15 13 MT9079 8-15 18-22 23 24 25 7 D0-7 AC0-4 RxA R/W RxB CS E2i DS F0i IRQ C4i S/P 36 30 3 RxA 29 4 RxB 27 1 E2o 9 LOS 8 CLKF/CLKP 7 RXINV 10 LOSP 31 26 VSS 37 MT9042 Figure 3b - Application Circuit 4-226 NETWORK CONNECTOR MH89792 Preliminary Information ISOLATION BARRIER MH89792 1 PLL LINE CONNECTORS FRAMER NETWORK SIDE SYSTEM SIDE 20 NOTES: X = Pin not fitted Separation across barrier > 2mm recommended. Figure 3c - Application Circuit Side View 0.1 Max (2.5 Max) 2.0 + 0.040 (50.8 + 1.0) 0.56 Max (14.2 Max) 1 0.010 + 0.002 (0.25 + 0.05) 0.27 Max (6.9 Max) * 0.05 + 0.01 (1.3 + 0.5) Notes 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) * Dimensions to pin center & tolerance non accumulative. * * 0.05 + 0.02 (1.225 + 0.05) 0.020 + 0.005 (0.51 + 0.13) * 0.18 + 0.02 (4.6 + 0.5) 0.100 + 0.010 (2.54 + 0.26) Figure 4 - Mechanical Data 4-227 MH89792 Notes: 4-228 Preliminary Information