CIRRUS EP7309_05

EP7309 Data Sheet
FEATURES
High-performance,
Low-power, System-on-chip
with Enhanced
Digital Audio Interface
■ ARM720T Processor
— ARM7TDMI CPU
— 8 KB of four-way set-associative cache
— MMU with 64-entry TLB
— Thumb code support enabled
■ Ultra low power
— 90 mW at 74 MHz typical
— 30 mW at 18 MHz typical
— 10 mW in the Idle State
— <1 mW in the Standby State
■ Advanced audio decoder/decompression capability
— Supports bit streams with adaptive bit rates
— Allows for support of multiple audio decompression
algorithms (MP3, WMA, AAC, ADPCM, Audible,
etc.)
OVERVIEW
The Maverick™ EP7309 is designed for ultra-low-power
applications such as digital music players, internet appliances,
smart cellular phones or any hand-held device that features the
added capability of digital audio decompression. The corelogic functionality of the device is built around an ARM720T
processor with 8 KB of four-way set-associative unified cache
and a write buffer. Incorporated into the ARM720T is an
enhanced memory management unit (MMU) which allows for
support of sophisticated operating systems like Microsoft®
Windows® CE and Linux®.
(cont.)
(cont.)
BLOCK DIAGRAM
Digital
Audio
Interface
SERIAL PORTS
Clocks &
Timers
ICE-JTAG
Power
Management
Interrupts,
PWM & GPIO
ARM720T
ARM7TDMI CPU Core
(2) UARTs
w/ IrDA
8 KB
Write
Cache
Buffer
MMU
Boot
ROM
Bus
Bridge
Keypad&
Touch
Screen I/F
Internal Data Bus
MaverickKeyTM
SRAM &
FLASH I/F
On-chip SRAM
48 KB
USER INTERFACE
Serial
Interface
EPB Bus
LCD
Controller
MEMORY AND STORAGE
©Copyright Cirrus Logic, Inc. 2005
http://www.cirrus.com
(All Rights Reserved)
AUG ‘05
DS507F1
EP7309
High-Performance, Low-Power System on Chip
FEATURES (cont)
■ Dynamically programmable clock speeds of 18, 36, 49, and
74 MHz
■ 48 KB of on-chip SRAM
■ MaverickKey™ IDs
— 32-bit unique ID can be used for SDMI compliance
— 128-bit random ID
■ LCD controller
— Interfaces directly to a single-scan panel monochrome
STN LCD
— Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
■ Full JTAG boundary scan and Embedded ICE® support
■ Integrated Peripheral Interfaces
— 8/32/16-bit SRAM/FLASH/ROM Interface
— Digital Audio Interface providing glueless interface to
low-power DACs, ADCs and CODECs
— Two Synchronous Serial Interfaces (SSI1, SSI2)
— CODEC Sound Interface
— 8×8 Keypad Scanner
— 27 General Purpose Input/Output pins
— Dedicated LED flasher pin from the RTC
■ Internal Peripherals
— Two 16550 compatible UARTs
— IrDA Interface
— Two PWM Interfaces
— Real-time Clock
— Two general purpose 16-bit timers
— Interrupt Controller
— Boot ROM
■ Package
— 208-Pin LQFP
— 256-Ball PBGA
— 204-Ball TFBGA
■ The fully static EP7309 is optimized for low power
dissipation and is fabricated on a 0.25 micron CMOS
process
OVERVIEW (cont.)
The EP7309 is designed for ultra-low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of
2.5 V–3.3 V. The device has three basic power states:
operating, idle and standby.
MaverickKey unique hardware programmed IDs are a solution
to the growing concern over secure web content and
commerce. With Internet security playing an important role in
the delivery of digital media such as books or music,
traditional software methods are quickly becoming unreliable.
The MaverickKey unique IDs provide OEMs with a method of
utilizing specific hardware IDs such as those assigned for
SDMI (Secure Digital Music Initiative) or any other
authentication mechanism.
2
The EP7309 integrates an interface to enable a direct
connection to many low cost, low power, high quality audio
converters. In particular, the DAI can directly interface with
the Crystal‚ CS43L41/42/43 low-power audio DACs and the
Crystal‚ CS53L32 low-power ADC. Some of these devices
feature digital bass and treble boost, digital volume control and
compressor-limiter functions.
Simply by adding desired memory and peripherals to the
highly integrated EP7309 completes a low-power system
solution. All necessary interface logic is integrated on-chip.
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Table of Contents
FEATURES...................................................................................................................................................................1
OVERVIEW ..................................................................................................................................................................1
Processor Core - ARM720T ..................................................................................................................................6
Power Management ..............................................................................................................................................6
MaverickKey™ Unique ID ......................................................................................................................................6
Memory Interfaces .................................................................................................................................................6
Digital Audio Capability .........................................................................................................................................6
Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................6
Digital Audio Interface (DAI) ..................................................................................................................................7
CODEC Interface ..................................................................................................................................................7
SSI2 Interface ........................................................................................................................................................7
Synchronous Serial Interface ................................................................................................................................8
LCD Controller .......................................................................................................................................................8
Interrupt Controller ................................................................................................................................................8
Real-Time Clock ....................................................................................................................................................8
PLL and Clocking ..................................................................................................................................................9
DC-to-DC converter interface (PWM) ....................................................................................................................9
Timers ...................................................................................................................................................................9
General Purpose Input/Output (GPIO) ..................................................................................................................9
Hardware debug Interface .....................................................................................................................................9
Internal Boot ROM ...............................................................................................................................................10
Packaging ............................................................................................................................................................10
Pin Multiplexing ...................................................................................................................................................10
System Design ....................................................................................................................................................11
ELECTRICAL SPECIFICATIONS ......................................................................................................12
Absolute Maximum Ratings .................................................................................................................................12
Recommended Operating Conditions .................................................................................................................12
DC Characteristics ..............................................................................................................................................12
Timings ...............................................................................................................................................14
Timing Diagram Conventions ....................................................................................................................14
Timing Conditions ......................................................................................................................................14
Static Memory .....................................................................................................................................................15
Static Memory Single Read Cycle .............................................................................................................16
Static Memory Single Write Cycle .............................................................................................................17
Static Memory Burst Read Cycle ...............................................................................................................18
Static Memory Burst Write Cycle ...............................................................................................................19
SSI1 Interface ......................................................................................................................................................20
SSI2 Interface ......................................................................................................................................................21
LCD Interface ......................................................................................................................................................22
JTAG Interface .....................................................................................................................................................23
Packages ............................................................................................................................................24
208-Pin LQFP Package Characteristics ..............................................................................................................24
208-Pin LQFP Package Specifications ......................................................................................................24
208-Pin LQFP Pin Diagram .......................................................................................................................25
208-Pin LQFP Numeric Pin Listing ............................................................................................................26
204-Ball TFBGA Package Characteristics ...........................................................................................................29
204-Ball TFBGA Package Specifications ..................................................................................................29
204-Ball TFBGA Pinout (Top View) ...........................................................................................................30
DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
3
EP7309
High-Performance, Low-Power System on Chip
204-Ball TFBGA Ball Listing ...................................................................................................................... 31
256-Ball PBGA Package Characteristics ............................................................................................................ 38
256-Ball PBGA Package Specifications .................................................................................................... 38
256-Ball PBGA Pinout (Top View)) ............................................................................................................ 39
256-Ball PBGA Ball Listing ........................................................................................................................ 39
JTAG Boundary Scan Signal Ordering ............................................................................................................... 43
CONVENTIONS ................................................................................................................................. 48
Acronyms and Abbreviations .............................................................................................................................. 48
Units of Measurement ......................................................................................................................................... 48
General Conventions .......................................................................................................................................... 49
Pin Description Conventions ............................................................................................................................... 49
49
Ordering Information ....................................................................................................................... 50
Environmental, Manufacturing, & Handling Information .............................................................. 50
Revision History ............................................................................................................................... 51
4
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
List of Figures
Figure 1. A Maximum EP7309 Based System ..............................................................................................................11
Figure 2. Legend for Timing Diagrams .........................................................................................................................14
Figure 3. Static Memory Single Read Cycle Timing Measurement ...............................................................................16
Figure 4. Static Memory Single Write Cycle Timing Measurement ...............................................................................17
Figure 5. Static Memory Burst Read Cycle Timing Measurement ................................................................................18
Figure 6. Static Memory Burst Write Cycle Timing Measurement ................................................................................19
Figure 7. SSI1 Interface Timing Measurement .............................................................................................................20
Figure 8. SSI2 Interface Timing Measurement .............................................................................................................21
Figure 9. LCD Controller Timing Measurement ............................................................................................................22
Figure 10. JTAG Timing Measurement .........................................................................................................................23
Figure 11. 208-Pin LQFP Package Outline Drawing ....................................................................................................24
Figure 12. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ..........................................................................25
Figure 13. 204-Ball TFBGA Package ............................................................................................................................29
Figure 14. 256-Ball PBGA Package ..............................................................................................................................38
List of Tables
Table 1. Power Management Pin Assignments ..............................................................................................................6
Table 2. Static Memory Interface Pin Assignments ........................................................................................................6
Table 3. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7
Table 4. DAI Interface Pin Assignments .........................................................................................................................7
Table 5. CODEC Interface Pin Assignments ..................................................................................................................7
Table 6. SSI2 Interface Pin Assignments .......................................................................................................................7
Table 7. Serial Interface Pin Assignments ......................................................................................................................8
Table 8. LCD Interface Pin Assignments ........................................................................................................................8
Table 9. Keypad Interface Pin Assignments ...................................................................................................................8
Table 10. Interrupt Controller Pin Assignments ..............................................................................................................8
Table 11. Real-Time Clock Pin Assignments ..................................................................................................................9
Table 12. PLL and Clocking Pin Assignments ................................................................................................................9
Table 13. DC-to-DC Converter Interface Pin Assignments .............................................................................................9
Table 14. General Purpose Input/Output Pin Assignments ............................................................................................9
Table 15. Hardware Debug Interface Pin Assignments ..................................................................................................9
Table 16. LED Flasher Pin Assignments ........................................................................................................................9
Table 17. DAI/SSI2/CODEC Pin Multiplexing ...............................................................................................................10
Table 18. Pin Multiplexing .............................................................................................................................................10
Table 19. 208-Pin LQFP Numeric Pin Listing ...............................................................................................................26
Table 20. 204-Ball TFBGA Ball Listing .........................................................................................................................31
Table 21. 256-Ball PBGA Ball Listing ...........................................................................................................................39
Table 22. JTAG Boundary Scan Signal Ordering .........................................................................................................43
Table 23. Acronyms and Abbreviations ........................................................................................................................48
Table 24. Unit of Measurement .....................................................................................................................................48
Table 25. Pin Description Conventions .........................................................................................................................49
DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
5
EP7309
High-Performance, Low-Power System on Chip
Processor Core - ARM720T
The EP7309 incorporates an ARM 32-bit RISC
microcontroller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key features
include:
•
•
•
•
ARM (32-bit) and Thumb (16-bit compressed) instruction
sets
Enhanced MMU for Microsoft Windows CE and other
operating systems
8 KB of 4-way set-associative cache.
Translation Look Aside Buffers with 64 Translated Entries
Power Management
The EP7309 is designed for ultra-low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of
2.5 V–3.3 V allowing the device to achieve a performance
level equivalent to 60 MIPS. The device has three basic power
states:
• Operating — This state is the full performance state.
All the clocks and peripheral logic are enabled.
• Idle — This state is the same as the Operating State,
except the CPU clock is halted while waiting for an
event such as a key press.
• Standby — This state is equivalent to the computer
being switched off (no display), and the main
oscillator shut down. An event such as a key press
can wake-up the processor.
Pin Mnemonic
I/O
Pin Description
BATOK
I
Battery ok input
nEXTPWR
I
External power supply sense
input
nPWRFL
I
Power fail sense input
nBATCHG
I
Battery changed sense input
MaverickKey
The EP7309 is equiped with a ROM/SRAM/FLASH-style
interface that has programmable wait-state timings and
includes burst-mode capability, with six chip selects decoding
six 256 MB sections of addressable space. For maximum
flexibility, each bank can be specified to be 8-, 16-, or 32-bits
wide. This allows the use of 8-bit-wide boot ROM options to
minimize overall system cost. The on-chip boot ROM can be
used in product manufacturing to serially download system
code into system FLASH memory. To further minimize system
memory requirements and cost, the ARM Thumb instruction
set is supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-leading
code density.
Pin Mnemonic
I/O
Pin Description
nCS[5:0]
O
Chip select out
A[27:0]
O
Address output
D[31:0]
I/O
Data I/O
nMOE
O
ROM expansion OP enable
nMWE
O
ROM expansion write enable
HALFWORD
O
Halfword access select
output
WORD
O
Word access select output
WRITE
O
Transfer direction
Digital Audio Capability
Unique ID
MaverickKey unique hardware programmed IDs are a solution
to the growing concern over secure web content and
commerce. With Internet security playing an important role in
the delivery of digital media such as books or music,
traditional software methods are quickly becoming unreliable.
The MaverickKey unique IDs provide OEMs with a method of
utilizing specific hardware IDs such as those assigned for
SDMI (Secure Digital Music Initiative) or any other
authentication mechanism.
6
Memory Interfaces
Table 2. Static Memory Interface Pin Assignments
Table 1. Power Management Pin Assignments
™
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7309 through the use of laser probing
technology. These IDs can then be used to match secure
copyrighted content with the ID of the target device the
EP7309 is powering, and then deliver the copyrighted
information over a secure connection. In addition, secure
transactions can benefit by also matching device IDs to server
IDs. MaverickKey IDs provide a level of hardware security
required for today’s Internet appliances.
The EP7309 uses its powerful 32-bit RISC processing engine
to implement audio decompression algorithms in software. The
nature of the on-board RISC processor, and the availability of
efficient C-compilers and other software development tools,
ensures that a wide range of audio decompression algorithms
can easily be ported to and run on the EP7309
Universal Asynchronous
Receiver/Transmitters (UARTs)
The EP7309 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte FIFOs
for receiving and transmitting data. The UARTs support bit
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
rates up to 115.2 kbps. An IrDA SIR protocol encoder/decoder
can be optionally switched into the RX/TX signals to/from
UART 1 to enable these signals to drive an infrared
communication interface directly.
Pin Mnemonic
I/O
Pin Description
TXD[1]
O
UART 1 transmit
RXD[1]
I
UART 1 receive
CTS
I
UART 1 clear to send
DCD
I
UART 1 data carrier detect
DSR
I
UART 1 data set ready
TXD[2]
O
UART 2 transmit
RXD[2]
I
UART 2 receive
LEDDRV
O
Infrared LED drive output
PHDIN
I
Photo diode input
Digital Audio Interface (DAI)
The EP7309 integrates an interface to enable a direct
connection to many low cost, low power, high quality audio
converters. In particular, the DAI can directly interface with
the Crystal‚ CS43L41/42/43 low-power audio DACs and the
Crystal‚ CS53L32 low-power ADC. Some of these devices
feature digital bass and treble boost, digital volume control and
compressor-limiter functions.
I/O
Pin Mnemonic
I/O
is
Pin Description
PCMCLK
O
Serial bit clock
PCMOUT
O
Serial data out
PCMIN
I
Serial data in
PCMSYNC
O
Frame sync
Table 5. CODEC Interface Pin Assignments
Note:
See Table 17 on page 10 for information on pin
multiplexes.
SSI2 Interface
Table 3. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Pin Mnemonic
communications systems. The CODEC interface
multiplexed to the same pins as the DAI and SSI2.
Pin Description
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode communications. The
SSI2 unit shares the same pins as the DAI and CODEC
interfaces through a multiplexer.
•
•
•
•
Synchronous clock speeds of up to 512 kHz
Separate 16 entry TX and RX half-word wide FIFOs
Half empty/full interrupts for FIFOs
Separate RX and TX frame sync signals for asymmetric
traffic
Pin Mnemonic
I/O
Pin Description
SSICLK
I/O
Serial bit clock
SSITXDA
O
Serial data out
Serial data in
SCLK
O
Serial bit clock
SSIRXDA
I
SDOUT
O
Serial data out
SSITXFR
I/O
Transmit frame sync
SDIN
I
Serial data in
SSIRXFR
I/O
Receive frame sync
LRCK
O
Sample clock
MCLKIN
I
Master clock input
MCLKOUT
O
Master clock output
Table 6. SSI2 Interface Pin Assignments
Note:
See Table 17 on page 10 for information on pin
multiplexes.
Table 4. DAI Interface Pin Assignments
Note:
See Table 17 on page 10 for information on pin
multiplexes.
CODEC Interface
The EP7309 includes an interface to telephony-type CODECs
for easy integration into voice-over-IP and other voice
DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
7
EP7309
High-Performance, Low-Power System on Chip
Synchronous Serial Interface
•
•
•
ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
Selectable serial clock polarity
Pin Mnemonic
I/O
•
•
Pin Description
ADCLK
O
SSI1 ADC serial clock
ADCIN
I
SSI1 ADC serial input
ADCOUT
O
SSI1 ADC serial output
nADCCS
O
SSI1 ADC chip select
SMPCLK
O
SSI1 ADC sample clock
•
•
Column outputs can be individually set high with the
remaining bits left at high-impedance
Column outputs can be driven all-low, all-high, or all-highimpedance
Keyboard interrupt driven by OR'ing together all Port A
bits
Keyboard interrupt can be used to wake up the system
8×8 keyboard matrix usable with no external logic, extra
keys can be added with minimal glue logic
Pin Mnemonic
•
•
Keyboard scanner column drive
Interrupt Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The display
frame buffer start address is programmable, allowing the LCD
frame buffer to be in SDRAM, internal SRAM or external
SRAM.
•
O
Table 9. Keypad Interface Pin Assignments
LCD Controller
•
Pin Description
COL[7:0]
Table 7. Serial Interface Pin Assignments
•
I/O
Interfaces directly to a single-scan panel monochrome STN
LCD
Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
Panel width size is programmable from 32 to 1024 pixels in
16-pixel increments
Video frame buffer size programmable up to
128 KB
Bits per pixel of 1, 2, or 4 bits
When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the same
time, a fixed priority system determines the order in which
they are handled. The EP7309 interrupt controller has two
interrupt types: interrupt request (IRQ) and fast interrupt
request (FIQ). The interrupt controller has the ability to control
interrupts from 22 different FIQ and IRQ sources.
•
•
•
Supports 22 interrupts from a variety of sources (such as
UARTs, SSI1, and key matrix.)
Routes interrupt sources to the ARM720T’s IRQ or FIQ
(Fast IRQ) inputs
Five dedicated off-chip interrupt lines operate as level
sensitive interrupts
.
Pin Mnemonic
Pin Mnemonic
I/O
I/O
Pin Description
Pin Description
CL1
O
LCD line clock
CL2
O
LCD pixel clock out
DD[3:0]
O
LCD serial display data bus
FRM
O
LCD frame synchronization pulse
M
O
LCD AC bias drive
nEINT[2:1]
I
External interrupt
EINT[3]
I
External interrupt
nEXTFIQ
I
External Fast Interrupt input
I
Media change interrupt input
nMEDCHG/nBROM
(Note)
Table 10. Interrupt Controller Pin Assignments
Note:
Table 8. LCD Interface Pin Assignments
Pins are multiplexed. See Table 18 on page 10 for
more information.
64-Keypad Interface
Real-Time Clock
Matrix keyboards and keypads can be easily read by the
EP7309. A dedicated 8-bit column driver output generates
strobes for each keyboard column signal. The pins of Port A,
when configured as inputs, can be selectively OR'ed together
to provide a keyboard interrupt that is capable of waking the
system from a STANDBY or IDLE state.
The EP7309 contains a 32-bit Real Time Clock (RTC) that can
be written to and read from in the same manner as the timer
counters. It also contains a 32-bit output match register which
can be programmed to generate an interrupt.
8
•
Driven byan external 32.768 kHz crystal oscillator
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Pin Mnemonic
Pin Description
Pin Mnemonic
Real-Time Clock Oscillator Input
PA[7:0]
I/O
GPIO port A
RTCOUT
Real-Time Clock Oscillator Output
PB[7:0]
I/O
GPIO port B
VDDRTC
Real-Time Clock Oscillator Power
PD[0]/LEDFLSH
I/O
GPIO port D
VSSRTC
Real-Time Clock Oscillator Ground
PD[5:1]
I/O
GPIO port D
(Note)
I/O
GPIO port D
PE[1:0]/BOOTSEL[1:0] (Note)
I/O
GPIO port E
PE[2]/CLKSEL
I/O
GPIO port E
PD[7:6]/SDQM[1:0]
PLL and Clocking
•
Processor and Peripheral Clocks operate from a single
3.6864 MHz crystal or external 13 MHz clock
Programmable clock speeds allow the peripheral bus to run
at 18 MHz when the processor is set to 18 MHz and at
36 MHz when the processor is set to 36, 49 or 74 MHz
Pin Mnemonic
Note:
Pins are multiplexed. See Table 18 on page 10 for
more information.
Hardware debug Interface
Full JTAG boundary scan and Embedded ICE® support
Main Oscillator Input
MOSCOUT
Main Oscillator Output
VDDOSC
Main Oscillator Power
TCLK
I
JTAG clock
VSSOSC
Main Oscillator Ground
TDI
I
JTAG data input
TDO
O
JTAG data output
nTRST
I
JTAG async reset input
TMS
I
JTAG mode select
Pin Mnemonic
Provides two 96 kHz clock outputs with programmable
duty ratio (from 1-in-16 to 15-in-16) that can be used to
drive a positive or negative DC to DC converter
Pin Mnemonic
DRIVE[1:0]
FB[1:0]
I/O
I/O
I
Pin Description
PWM drive output
PWM feedback input
Table 13. DC-to-DC Converter Interface Pin Assignments
Timers
Internal (RTC) timer
Two internal 16-bit programmable hardware count-down
timers
General Purpose Input/Output (GPIO)
•
•
(Note)
MOSCIN
DC-to-DC converter interface (PWM)
•
•
(Note)
Table 14. General Purpose Input/Output Pin Assignments
•
Pin Description
Table 12. PLL and Clocking Pin Assignments
•
Pin Description
RTCIN
Table 11. Real-Time Clock Pin Assignments
•
I/O
Three 8-bit and one 3-bit GPIO ports
Supports scanning keyboard matrix
Pin Description
Table 15. Hardware Debug Interface Pin Assignments
LED Flasher
A dedicated LED flasher module can be used to generate a low
frequency signal on Port D pin 0 for the purpose of blinking an
LED without CPU intervention. The LED flasher feature is
ideal as a visual annunciator in battery powered applications,
such as a voice mail indicator on a portable phone or an
appointment reminder on a PDA.
•
•
•
•
Software adjustable flash period and duty cycle
Operates from 32 kHz RTC clock
Will continue to flash in IDLE and STANDBY states
4 mA drive current
Pin Mnemonic
PD[0]/LEDFLSH
(Note)
I/O
O
Pin Description
LED flasher driver
Table 16. LED Flasher Pin Assignments
Note:
DS507F1
I/O
Pins are multiplexed. See Table 18 on page 10 for
more information.
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
9
EP7309
High-Performance, Low-Power System on Chip
Internal Boot ROM
The internal 128 byte Boot ROM facilitates download of saved
code to the on-board SRAM/FLASH.
Packaging
The EP7309 is available in a 208-pin LQFP package, 256-ball
PBGA package or a 204-ball TFBGA package.
Pin Multiplexing
The following table shows the pin multiplexing of the DAI,
SSI2 and the CODEC. The selection between SSI2 and the
CODEC is controlled by the state of the SERSEL bit in
SYSCON2. The choice between the SSI2, CODEC, and the
DAI is controlled by the DAISEL bit in SYSCON3 (see the
EP7309 User’s Manual for more information).
Pin
Mnemonic
Pin
Mnemonic
I/O
DAI
SSI2
CODEC
SSITXFR
I/O
LRCK
SSITXFR
PCMSYNC
SSIRXFR
I
MCLKIN
SSIRXFR
p/u
BUZ
O
MCLKOUT
Table 17. DAI/SSI2/CODEC Pin Multiplexing
The following table shows the pins that have been multiplexed
in the EP7309.
Signal
Block
Signal
Block
RUN
System
Configuration
CLKEN
System
Configuration
nMEDCHG
Interrupt
Controller
nBROM
Boot ROM
select
I/O
DAI
SSI2
CODEC
PD[0]
GPIO
LEDFLSH
LED Flasher
SSICLK
I/O
SCLK
SSICLK
PCMCLK
PE[1:0]
GPIO
BOOTSEL[1:0]
System
Configuration
SSITXDA
O
SDOUT
SSITXDA
PCMOUT
PE[2]
GPIO
CLKSEL
SSIRXDA
I
SDIN
SSIRXDA
PCMIN
System
Configuration
Table 18. Pin Multiplexing
Table 17. DAI/SSI2/CODEC Pin Multiplexing
10
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
System Design
As shown in system block diagram, simply adding desired
memory and peripherals to the highly integrated EP7309
CRYSTAL
MOSCIN
CRYSTAL
RTCIN
completes a low-power system solution. All necessary
interface logic is integrated on-chip.
DD[0-3]
CL1
CL2
FRM
M
LCD
COL[0-7]
PA[0-7]
nCS[4]
PB0
EXPCLK
KEYBOARD
PB[0-7]
PD[0-7]
D[0-31]
PC CARD
CONTROLLER
A[0-27]
nMOE
WRITE
nCS[0]
nCS[1]
×16
FLASH
×16
FLASH
×16
FLASH
×16
FLASH
PE[0-2]
EP7309
PC CARD
SOCKET
nPOR
nPWRFL
BATOK
nEXTPWR
nBATCHG
RUN
WAKEUP
DRIVE[0-1]
FB[0-1]
SSICLK
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
LEDDRV
PHDIN
CS[n]
WORD
EXTERNAL MEMORYMAPPED EXPANSION
BUFFERS
nCS[2]
nCS[3]
ADDITIONAL I/O
BUFFERS
AND
LATCHES
LEDFLSH
RXD1/2
TXD1/2
DSR
CTS
DCD
ADCCLK
nADCCS
ADCOUT
ADCIN
SMPCLK
POWER
SUPPLY UNIT
AND
COMPARATORS
DC
INPUT
BATTERY
DC-TO-DC
CONVERTERS
CODEC/SSI2/
DAI
IR LED AND
PHOTODIODE
2× RS-232
TRANSCEIVERS
ADC
DIGITIZER
Figure 1. A Maximum EP7309 Based System
Note:
DS507F1
A system can only use one of the following peripheral
interfaces at any given time: SSI2,CODEC or DAI.
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
11
EP7309
High-Performance, Low-Power System on Chip
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
DC Core, PLL, and RTC Supply Voltage
2.9 V
DC I/O Supply Voltage (Pad Ring)
3.6 V
DC Pad Input Current
±10 mA/pin; ±100 mA cumulative
Storage Temperature, No Power
–40°C to +125°C
Recommended Operating Conditions
DC core, PLL, and RTC Supply Voltage
2.5 V ± 0.2 V
DC I/O Supply Voltage (Pad Ring)
2.3 V - 3.5 V
DC Input / Output Voltage
O–I/O supply voltage
Operating Temperature
Extended -20°C to +70°C; Commercial 0°C to +70°C;
Industrial -40°C to +85°C
DC Characteristics
All characteristics are specified at VDDCORE = 2.5 V, VDDIO = 3.3 V and VSS = 0 V over an operating temperature of 0°C to +70°C
for all frequencies of operation. The current consumption figures have test conditions specified per parameter.”
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
VIH
CMOS input high voltage
0.65 × VDDIO
-
VDDIO + 0.3
V
VDDIO = 2.5 V
VIL
CMOS input low voltage
VSS − 0.3
-
0.25 × VDDIO
V
VDDIO = 2.5 V
VT+
Schmitt trigger positive going
threshold
-
-
2.1
V
VT-
Schmitt trigger negative going
threshold
0.8
-
-
V
Vhst
Schmitt trigger hysteresis
0.1
-
0.4
V
VIL to VIH
VDD – 0.2
2.5
2.5
-
-
V
V
V
IOH = 0.1 mA
IOH = 4 mA
IOH = 12 mA
Output drive 2a
-
-
0.3
0.5
0.5
V
V
V
IOL = –0.1 mA
IOL = –4 mA
IOL = –12 mA
Input leakage current
-
-
1.0
µA
VIN = VDD or GND
currentb c
25
-
100
µA
VOUT = VDD or GND
CIN
Input capacitance
8
-
10.0
pF
COUT
Output capacitance
8
-
10.0
pF
CMOS output high voltagea
VOH
Output drive 1a
Output drive 2a
CMOS output low voltagea
VOL
IIN
IOZ
12
Output drive 1a
Bidirectional 3-state leakage
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Symbol
CI/O
Parameter
Transceiver capacitance
IDDSTANDBY
@ 25 C
IDDSTANDBY
@ 70 C
IDDSTANDBY
@ 85 C
IDDidle
at 74 MHz
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Typ
Max
Unit
8
-
10.0
pF
-
77
41
-
-
-
570
111
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
Idle current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
-
-
1693
163
Conditions
µA
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
µA
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
µA
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
Standby current consumption1
VDDSTANDBY Standby supply voltage
a.
Min
-
6
10
-
mA
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = VDD ± 0.1 V, VIL
= GND ± 0.1 V
2.0
-
-
V
Minimum standby voltage for
state retention, internal SRAM
cache, and RTC operation only
Refer to the strength column in the pin assignment tables for all package types.
b.
Assumes buffer has no pull-up or pull-down resistors.
c.
The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.
Note:
DS507F1
1) Total power consumption = IDDCORE x 2.5 V + IDDIO x 3.3 V
2) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be
compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).
2) Pull-up current = 50 µA typical at VDD = 3.3 V.
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
13
EP7309
High-Performance, Low-Power System on Chip
Timings
Timing Diagram Conventions
This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are
clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.
C lo c k
H ig h
H ig h / L o w
to
to
L o w
H ig h
B u s C h a n g e
B u s
V a lid
U n d e f in e d / I n v a lid
V a lid
B u s to
T r is ta te
B u s / S ig n a l O m is s io n
Figure 2. Legend for Timing Diagrams
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified at
VDDIO = 3.1 - 3.5 V and VSS = 0 V over an operating temperature of -40°C to +85°C. Pin loadings is 50 pF. The timing values are
referenced to 1/2 VDD.
14
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Static Memory
Figure 3 through Figure 6 define the timings associated with all phases of the Static Memory. The following table contains the
values for the timings of each of the Static Memory modes.
Parameter
Symbol
Min
Typ
Max
Unit
EXPCLK rising edge to nCS assert delay time
tCSd
2
8
20
ns
EXPCLK falling edge to nCS deassert hold time
tCSh
2
7
20
ns
EXPCLK rising edge to A assert delay time
tAd
4
9
16
ns
EXPCLK falling edge to A deassert hold time
tAh
3
10
19
ns
EXPCLK rising edge to nMWE assert delay time
tMWd
3
6
10
ns
EXPCLK rising edge to nMWE deassert hold time
tMWh
3
6
10
ns
EXPCLK falling edge to nMOE assert delay time
tMOEd
3
7
10
ns
EXPCLK falling edge to nMOE deassert hold time
tMOEh
2
7
10
ns
EXPCLK falling edge to HALFWORD deassert delay time
tHWd
2
8
20
ns
EXPCLK falling edge to WORD assert delay time
tWDd
2
8
16
ns
EXPCLK rising edge to data valid delay time
tDv
8
13
21
ns
EXPCLK falling edge to data invalid delay time
tDnv
6
15
30
ns
Data setup to EXPCLK falling edge time
tDs
-
-
1
ns
EXPCLK falling edge to data hold time
tDh
-
-
3
ns
EXPCLK rising edge to WRITE assert delay time
tWRd
5
11
23
ns
EXPREADY setup to EXPCLK falling edge time
tEXs
-
-
0
ns
EXPCLK falling edge to EXPREADY hold time
tEXh
-
-
0
ns
DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
15
EP7309
High-Performance, Low-Power System on Chip
Static Memory Single Read Cycle
EXPCLK
t C Sd
t C Sh
nCS
t Ad
A
nM W E
t M O Ed
t M O Eh
nM OE
tH W d
HALFW ORD
tW D d
W ORD
tD s
tD h
D
t EXs
t EXh
EXPRDY
tW R d
W R IT E
Figure 3. Static Memory Single Read Cycle Timing Measurement
Note:
16
1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Address, Halfword, Word, and Write hold state until next cycle.
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Static Memory Single Write Cycle
EXPCLK
t C Sd
t C Sh
nCS
t Ad
A
tM W d
tM W h
nM W E
nM OE
tH W d
HALFW ORD
tW D d
W ORD
tD v
D
t EXs
t EXh
EXPRDY
W R IT E
Figure 4. Static Memory Single Write Cycle Timing Measurement
Note:
DS507F1
1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
3. Address, Data, Halfword, Word, and Write hold state until next cycle.
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
17
EP7309
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
EXPCLK
t C Sd
t C Sh
nCS
t Ad
t Ah
t Ah
t Ah
A
nM W E
t M O Ed
t M O Eh
nM OE
tH W d
HALF
W ORD
tW D d
W ORD
tD s
tD h
tD s
tD h
tD s
tD h
tD s
tD h
D
t EXs
t EXh
EXPRDY
tW R d
W R IT E
Figure 5. Static Memory Burst Read Cycle Timing Measurement
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.
18
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
EXPCLK
t C Sd
t C Sh
nCS
t Ah
t Ah
t Ah
t Ad
A
tM W d
tM W d
tM W d
tM W h
nM W E
tM W d
tM W h
tM W h
tM W h
nM OE
tH W d
HALF
W ORD
W ORD
tW D d
tD v
t D nv
tD v
t D nv
tD v
t D nv
tD v
D
t EXs
t EXh
EXPRDY
W R IT E
Figure 6. Static Memory Burst Write Cycle Timing Measurement
Note:
DS507F1
1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
19
EP7309
High-Performance, Low-Power System on Chip
SSI1 Interface
Parameter
Symbol
Min
Max
Unit
ADCCLK falling edge to nADCCSS deassert delay time
tCd
9
10
ms
ADCIN data setup to ADCCLK rising edge time
tINs
-
15
ns
ADCIN data hold from ADCCLK rising edge time
tINh
-
14
ns
ADCCLK falling edge to data valid delay time
tOvd
−7
13
ns
ADCCLK falling edge to data invalid delay time
tOd
−2
3
ns
ADC
CLK
tCd
nADC
CSS
tINs
tINh
ADCIN
tOvd
tOd
ADC
OUT
Figure 7. SSI1 Interface Timing Measurement
20
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
SSI2 Interface
Parameter
Symbol
Min
Max
Unit
SSICLK period (slave mode)
tclk_per
185
2050
ns
SSICLK high time
tclk_high
925
1025
ns
SSICLK low time
tclk_low
925
1025
ns
SSICLK rise/fall time
tclkrf
3
18
ns
SSICLK rising edge to RX and/or TX frame sync high time
tFRd
-
3
ns
SSICLK rising edge to RX and/or TX frame sync low time
tFRa
-
8
ns
tFR_per
960
990
ns
SSIRXDA setup to SSICLK falling edge time
tRXs
3
7
ns
SSIRXDA hold from SSICLK falling edge time
tRXh
3
7
ns
SSICLK rising edge to SSITXDA data valid delay time
tTXd
-
2
ns
SSITXDA valid time
tTXv
960
990
ns
SSIRXFR and/or SSITXFR period
t clk_per
t clk_high
t clk_low
SSI
CLK
t clkrf
t FR _per
t FR d
t FR a
S S IR X F R /
S S IT X F R
t R Xh
t R Xs
SSI
RXDA
D7
D2
D1
D0
D7
D2
D1
D0
t TXd
SSI
TXDA
t TXv
Figure 8. SSI2 Interface Timing Measurement
DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
21
EP7309
High-Performance, Low-Power System on Chip
LCD Interface
Parameter
Symbol
Min
Max
Unit
CL[2] falling to CL[1] rising delay time
tCL1d
− 10
25
ns
CL[1] falling to CL[2] rising delay time
tCL2d
80
3,475
ns
CL[1] falling to FRM transition time
tFRMd
300
10,425
ns
CL[1] falling to M transition time
tMd
− 10
20
ns
CL[2] rising to DD (display data) transition time
tDDd
− 10
20
ns
C L [2 ]
t C L2d
t C L1d
C L [1 ]
t FR M d
FRM
tM d
M
tD D d
D D [3 :0 ]
Figure 9. LCD Controller Timing Measurement
22
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
JTAG Interface
Parameter
Symbol
Min
Max
Units
TCK clock period
tclk_per
2
-
ns
TCK clock high time
tclk_high
1
-
ns
TCK clock low time
tclk_low
1
-
ns
JTAG port setup time
tJPs
-
0
ns
JTAG port hold time
tJPh
-
3
ns
JTAG port clock to output
tJPco
-
10
ns
JTAG port high impedance to valid output
tJPzx
-
12
ns
JTAG port valid output to high impedance
tJPxz
-
19
ns
t clk_per
t clk_high
t clk_low
TCK
t JPh
t JPs
TM S
TDI
t JPzx
t JPco
t JPxz
TDO
Figure 10. JTAG Timing Measurement
DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
23
EP7309
High-Performance, Low-Power System on Chip
Packages
208-Pin LQFP Package Characteristics
208-Pin LQFP Package Specifications
29.60 (1.165)
30.40 (1.197)
27.80 (1.094)
28.20 (1.110)
0.17 (0.007)
0.27 (0.011)
27.80 (1.094)
28.20 (1.110)
EP7309
29.60 (1.165)
30.40 (1.197)
208-Pin LQFP
0.50
(0.0197)
BSC
Pin 1 Indicator
Pin 208
Pin 1
1.35 (0.053)
1.45 (0.057)
0.45 (0.018)
0.75 (0.030)
1.00 (0.039) BSC
0.09 (0.004)
0.20 (0.008)
0° MIN
7° MAX
0.05 (0.002)
0.15 (0.006)
1.40 (0.055)
1.60 (0.063)
Figure 11. 208-Pin LQFP Package Outline Drawing
Note:
24
1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.
2) Drawing above does not reflect exact package pin count.
3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
4) For pin locations, please see Figure 12. For pin descriptions see the EP7309 User’s Manual.
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
nURESET
nMEDCHG/nBROM
nPOR
BATOK
nEXTPWR
nBATCHG
D[7]
VSSIO
A[7]
D[8]
A[8]
D[9]
A[9]
D[10]
A[10]
D[11]
VSSIO
VDDIO
A[11]
D[12]
A[12]
D[13]
A[13]
D[14]
A[14]
D[15]
A[15]
D[16]
A[16]
D[17]
A[17]
nTRST
VSSIO
VDDIO
D[18]
A[18
D[19]
A[19]
D[20]
A[20]
VSSIO
D[21]
A[21]
D[22]
A[22]
D[23]
A[23]
D[24]
VSSIO
VDDIO
A[24]
HALFWORD
208-Pin LQFP Pin Diagram
N/C
N/C
N/C
N/C
VDDIO
VSSIO
N/C
N/C
EP7309
208-Pin LQFP
(Top View)
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
D[25]
A[25]
D[26]
A[26]
D[27]
A[27]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
VSSIO
FB[1]
SMPCLK
ADCOUT
ADCCLK
DRIVE[0]
DRIVE[1]
VDDIO
VSSIO
VDDCORE
VSSCORE
nADCCS
ADCIN
SSIRXFR
SSIRXDA
SSITXDA
SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]
PD[2]
PD[3]
TMS
VDDIO
PD[4]
PD[5]
PD[6]
PD[7]
nCS[5]
VDDIO
VSSIO
EXPCLK
WORD
WRITE
RUN/CLKEN
EXPRDY
TXD[2]
RXD[2]
TDI
VSSIO
PB[7]
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]
PB[0]
VDDIO
TDO
PA[7]
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
PA[0]
LEDDRV
TXD[1]
VSSIO
PHDIN
CTS
RXD[1]
DCD
DSR
nTEST[1]
nTEST[0]
EINT[3]
nEINT[2]
nEINT[1]
nEXTFIQ
PE[2]/CLKSEL
PE[1]BOOTSEL[1]
PE[0]BOOTSEL[0]
VSSRTC
RTCOUT
RTCIN
VDDRTC
N/C
nMWE
nMOE
VSSIO
nCS[0]
nCS[1]
nCS[2]
nCS[3]
nCS[4]
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VDDOSC
MOSCIN
MOSCOUT
VSSOSC
WAKEUP
nPWRFL
A[6]
D[6]
A[5]
D[5]
VDDIO
VSSIO
A[4]
D[4]
A[3]
D[3]
A[2]
VSSIO
D[2]
A[1]
D[1]
A[0]
D[0]
VSSCORE
VDDCORE
VSSIO
VDDIO
CL[2]
CL[1]
FRM
M
DD[3]
DD[2]
VSSIO
DD[1]
DD[0]
Figure 12. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
Note:
DS507F1
1. N/C should not be grounded but left as no connects.
2. Pin differences between the EP7212 and the EP7309 are bolded.
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
25
EP7309
High-Performance, Low-Power System on Chip
208-Pin LQFP Numeric Pin Listing
Table 19. 208-Pin LQFP Numeric Pin Listing (Continued)
Table 19. 208-Pin LQFP Numeric Pin Listing
Pin
No.
Signal
Type
37
DCD
I
38
DSR
I
39
nTEST[1]
I
With p/u*
40
nTEST[0]
I
With p/u*
41
EINT[3]
I
42
nEINT[2]
I
43
nEINT[1]
I
44
nEXTFIQ
I
45
PE[2]/CLKSEL
I/O
1
Input
46
PE[1]/
BOOTSEL[1]
I/O
1
Input
47
PE[0]/
BOOTSEL[0]
I/O
1
Input
Input
48
VSSRTC
RTC Gnd
1
Input
49
RTCOUT
O
I/O
1
Input
50
RTCIN
I
PB[4]
I/O
1
Input
51
VDDRTC
RTC power
17
PB[3]
I/O
1
Input
52
N/C
18
PB[2]
I/O
1
Input
53
PD[7]
I/O
1
Low
19
PB[1]/PRDY2
I/O
1
Input
54
PD[6]
I/O
1
Low
20
PB[0]/PRDY1
I/O
1
Input
55
PD[5]
I/O
1
Low
21
VDDIO
Pad Pwr
56
PD[4]
I/O
1
Low
22
TDO
O
1
Three state
57
VDDIO
Pad Pwr
23
PA[7]
I/O
1
Input
58
TMS
I
with p/u*
24
PA[6]
I/O
1
Input
59
PD[3]
I/O
1
Low
25
PA[5]
I/O
1
Input
60
PD[2]
I/O
1
Low
26
PA[4]
I/O
1
Input
61
PD[1]
I/O
1
Low
27
PA[3]
I/O
1
Input
62
PD[0]/LEDFLSH
I/O
1
Low
28
PA[2]
I/O
1
Input
63
SSICLK
I/O
1
Input
29
PA[1]
I/O
1
Input
64
VSSIO
Pad Gnd
30
PA[0]
I/O
1
Input
65
SSITXFR
I/O
1
Low
31
LEDDRV
O
1
Low
66
SSITXDA
O
1
Low
32
TXD[1]
O
1
High
67
SSIRXDA
I
33
VSSIO
Pad Gnd
1
High
68
SSIRXFR
I/O
34
PHDIN
I
69
ADCIN
I
35
CTS
I
70
nADCCS
O
36
RXD[1]
I
71
VSSCORE
Core Gnd
72
VDDCORE
Core Pwr
Pin
No.
Signal
Type
Strength
Reset
State
1
nCS[5]
O
1
High
2
VDDIO
Pad Pwr
3
VSSIO
Pad Gnd
4
EXPCLK
I/O
1
5
WORD
Out
1
Low
6
WRITE
Out
1
Low
7
RUN/CLKEN
O
1
Low
8
EXPRDY
I
1
9
TXD[2]
O
1
10
RXD[2]
I
11
TDI
I
12
VSSIO
Pad Gnd
13
PB[7]
I/O
1
14
PB[6]
I/O
15
PB[5]
16
26
High
with p/u*
Strength
Reset
State
Input
1
High
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Table 19. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Signal
Type
Strength
Reset
State
Pad Gnd
110
A[23]
O
1
Low
VDDIO
Pad Pwr
111
D[23]
I/O
1
Low
DRIVE[1]
I/O
112
A[22]
O
1
Low
Pin
No.
Signal
Type
73
VSSIO
74
75
Strength
Reset
State
2
High /
Low
113
D[22]
I/O
1
Low
114
A[21]
O
1
Low
115
D[21]
I/O
1
Low
116
VSSIO
Pad Gnd
117
A[20]
O
1
Low
118
D[20]
I/O
1
Low
119
A[19]
O
1
Low
120
D[19]
I/O
1
Low
121
A[18]
O
1
Low
122
D[18]
I/O
1
Low
123
VDDIO
Pad Pwr
124
VSSIO
Pad Gnd
125
nTRST
I
126
A[17]
O
1
Low
127
D[17]
I/O
1
Low
128
A[16]
O
1
Low
129
D[16]
I/O
1
Low
130
A[15]
O
1
Low
131
D[15]
I/O
1
Low
132
A[14]
O
1
Low
133
D[14]
I/O
1
Low
134
A[13]
O
1
Low
135
D[13]
I/O
1
Low
136
A[12]
O
1
Low
137
D[12]
I/O
1
Low
138
A[11]
O
1
Low
139
VDDIO
Pad Pwr
140
VSSIO
Pad Gnd
141
D[11]
I/O
1
Low
142
A[10]
O
1
Low
143
D[10]
I/O
1
Low
144
A[9]
O
1
Low
145
D[9]
I/O
1
Low
146
A[8]
O
1
Low
147
D[8]
I/O
1
Low
76
DRIVE[0]
I/O
2
High /
Low
77
ADCCLK
O
1
Low
78
ADCOUT
O
1
Low
79
SMPCLK
O
1
Low
80
FB[1]
I
81
VSSIO
Pad Gnd
82
FB[0]
I
83
COL[7]
O
1
High
84
COL[6]
O
1
High
85
COL[5]
O
1
High
86
COL[4]
O
1
High
87
COL[3]
O
1
High
88
COL[2]
O
1
High
89
VDDIO
Pad Pwr
90
TCLK
I
91
COL[1]
O
1
High
92
COL[0]
O
1
High
93
BUZ
O
1
Low
94
D[31]
I/O
1
Low
95
D[30]
I/O
1
Low
96
D[29]
I/O
1
Low
97
D[28]
I/O
1
Low
98
VSSIO
Pad Gnd
99
A[27]
O
2
Low
100
D[27]
I/O
1
Low
101
A[26]
O
2
Low
102
D[26]
I/O
1
Low
103
A[25]
O
2
Low
104
D[25]
I/O
1
Low
105
HALFWORD
O
1
Low
106
A[24]
O
1
Low
107
VDDIO
Pad Pwr
—
108
VSSIO
Pad Gnd
—
109
D[24]
I/O
DS507F1
Table 19. 208-Pin LQFP Numeric Pin Listing (Continued)
1
Low
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
27
EP7309
High-Performance, Low-Power System on Chip
Table 19. 208-Pin LQFP Numeric Pin Listing (Continued)
Table 19. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Signal
Type
Strength
Reset
State
Pin
No.
Signal
Type
Strength
Reset
State
148
A[7]
O
1
Low
186
FRM
O
1
Low
149
VSSIO
Pad Gnd
187
M
O
1
Low
150
D[7]
I/O
188
DD[3]
I/O
1
Low
151
nBATCHG
I
189
DD[2]
I/O
1
Low
152
nEXTPWR
I
190
VSSIO
Pad Gnd
153
BATOK
I
191
DD[1]
I/O
1
Low
154
nPOR
I
192
DD[0]
I/O
1
Low
155
nMEDCHG/
nBROM
I
193
N/C
O
1
High
194
N/C
O
1
High
156
nURESET
I
195
N/C
I/O
2
Low
157
VDDOSC
Osc Pwr
196
N/C
I/O
2
Low
158
MOSCIN
Osc
197
VDDIO
Pad Pwr
159
MOSCOUT
Osc
198
VSSIO
Pad Gnd
160
VSSOSC
Osc Gnd
199
N/C
I/O
2
Low
161
WAKEUP
I
200
N/C
I/O
2
Low
162
nPWRFL
I
201
nMWE
O
1
High
163
A[6]
O
1
Low
202
nMOE
O
1
High
164
D[6]
I/O
1
Low
203
VSSIO
Pad Gnd
165
A[5]
Out
1
Low
204
nCS[0]
O
1
High
166
D[5]
I/O
1
Low
205
nCS[1]
O
1
High
167
VDDIO
Pad Pwr
206
nCS[2]
O
1
High
168
VSSIO
Pad Gnd
207
nCS[3]
O
1
High
169
A[4]
O
1
Low
208
nCS[4]
O
1
High
170
D[4]
I/O
1
Low
171
A[3]
O
2
Low
172
D[3]
I/O
1
Low
173
A[2]
O
2
Low
174
VSSIO
Pad Gnd
175
D[2]
I/O
1
Low
176
A[1]
O
2
Low
177
D[1]
I/O
1
Low
178
A[0]
O
2
Low
179
D[0]
I/O
1
Low
180
VSS CORE
Core Gnd
181
VDD CORE
Core Pwr
182
VSSIO
Pad Gnd
183
VDDIO
Pad Pwr
184
CL[2]
O
1
Low
185
CL[1]
O
1
Low
28
1
Low
Schmitt
Schmitt
Schmitt
*With p/u’ means with internal pull-up on the pin.
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
204-Ball TFBGA Package Characteristics
204-Ball TFBGA Package Specifications
Ø0.08 M
C
Ø0.15 M C A
B
Ø0.25~0.35(204X)
TOP VIEW
A1 CORNER
1 2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
BOTTOM VIEW
A1 CORNER
20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
A
B
B
C
C
D
D
E
E
F
F
0.65
A
G
G
J
K
L
12.35
H
J
13±0.05
H
K
L
M
M
N
N
P
P
R
R
T
T
U
U
V
V
W
W
Y
Y
A
0.65
12.35
13±0.05
0.20 C
0.15(4X) C
0.10 C
0.53±0.05
B
Ball Pitch :
SEATING PLANE
Ball Diam eter :
1.20
M AX.
C
0.20~0.30
0.36
0.65
0.3
Substrate Thickness :
0.36
Mold Thickness
:
0.53
Figure 13. 204-Ball TFBGA Package
DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
29
EP7309
High-Performance, Low-Power System on Chip
204-Ball TFBGA Pinout (Top View)
1
2
3
A VDDR
EXPCLK
nCS3
B WORD
VDDR
C
4
5
6
7
8
9
10
11
12
13
14
15
nCS1 nMWE
N/C
N/C
DD2
FRM
CL1
GNDD
D1
A2
D4
A5
nCS5
nCS2
nMOE
N/C
N/C
DD1
M
CL2
D0
A1
D3
A4
D6
RUN/
EXPRDY VDDR
CLKEN
nCS4
nCS0
N/C
N/C
DD0
DD3
VDDD
A0
D2
A3
D5
A6
16
18
19
20
nPWRFL MOSCOUT
GNDR
GNDR
GNDR
WAKEUP MOSCIN
GNDR
GNDR nURESET B
GNDR
BATOK
nPOR
C
GNDR
nBATCHG
A7
D
nMEDCHG
nEXTPWR
/nBROM
D9
E
GNDO
17
VDDO
A
D
PB7
RXD2
VDDR
E
PB4
TXD2
WRITE
F
PB3
PB6
TDI
D7
A8
D10
F
G
PB1
PB2
PB5
D8
A9
D11
G
H
PA7
TDO
PB0
A10
D12
A12
H
J
PA4
PA5
PA6
A11
D13
A13
J
K
PA1
PA2
VDDR
D14
A14
D15
K
L
TXD1
LEDDRV
PA3
VDDR
D16
A16
L
CTS
PA0
A15
A17
nTEST1 PHDIN
D17
D19
A18
N
P EINT3
nEINT2
D18
A20
D20
P
R nEXTFIQ
PE2/
nTEST0
CLKSEL
A19
D22
A21
R
D21
D23
A22
T
HALF
WORD
D24
A23
U
M RXD1
N
T
DSR
PE1/
BOOT
SEL1
U GNDC
PE0/
BOOT
SEL0
DCD
nEINT1
RTCOUT RTCIN
V VDDC
GNDR
GNDR
PD7
PD4
PD2
W GNDR
GNDR
GNDR
PD6
TMS
PD1
Y GNDR
GNDR
GNDR
PD5
PD3
30
SSICLK SSIRXDA nADCCS VDDR ADCCLK COL7
SSITXFR SSIRXFR GNDD1 DRIVE1 ADCOUT
PD0/
LED SSITXDA ADCIN
FLSH
VDD1 DRIVE0 SMPLCK
nTRST M
COL4 TCLK
BUZ
D29
A26
VDDR
VDDR
A24
V
FB0
COL5 COL2
COL0
D30
A27
D26
VDDR
D25
W
FB1
COL6 COL3
COL1
D31
D28
D27
A25
VDDR
Y
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
204-Ball TFBGA Ball Listing
The list is ordered by ball location.
Table 20. 204-Ball TFBGA Ball Listing
Ball Location
Name
†
Strength
Reset
State
Type
Digital I/O power,
3.3 V
A1
VDDIO
A2
EXPCLK
1
A3
nCS[3]
1
High
O
Chip select 3
A4
nCS[1]
1
High
O
Chip select 1
A5
nMWE/nSDWE
1
High
O
ROM, expansion write enable/ SDRAM write enable control signal
A6
N/C
A7
N/C
A8
DD[2]
1
Low
O
LCD serial display data
A9
FRM
1
Low
O
LCD frame synchronization pulse
A10
CL[1]
1
Low
O
LCD line clock
A11
VSSCORE
A12
D[1]
1
Low
I/O
Data I/O
A13
A[2]
2
Low
O
System byte address
A14
D[4]
1
Low
I/O
Data I/O
A15
A[5]
1
Low
O
System byte address
A16
nPWRFL
I
Power fail sense input
A17
MOSCOUT
O
Main oscillator out
A18
VSSIO
Pad ground
I/O ground
A19
VSSIO
Pad ground
I/O ground
A20
VSSIO
Pad ground
I/O ground
B1
WORD
B2
VDDIO
B3
nCS[5]
1
Low
O
Chip select 5
B4
nCS[2]
1
High
O
Chip select 2
B5
nMOE/nSDCAS
1
High
O
ROM, expansion OP enable/SDRAM CAS control signal
B6
N/C
B7
N/C
B8
DD[1]
1
Low
O
LCD serial display data
B9
M
1
Low
O
LCD AC bias drive
B10
CL[2]
1
Low
0
LCD pixel clock out
B11
D[0]
1
Low
I/O
Data I/O
B12
A[1]
2
Low
O
System byte address
B13
D[3]
2
Low
I/O
Data I/O
B14
A[4]
1
Low
O
System byte address
DS507F1
Pad power
Description
I
Core ground
1
Low
O
Pad power
Expansion clock input
Core ground
Word access select output
Digital I/O power, 3.3 V
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
31
EP7309
High-Performance, Low-Power System on Chip
Table 20. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
†
Strength
Type
Low
I/O
Description
B15
D[6]
B16
WAKEUP
B17
MOSCIN
B18
VSSIO
Pad ground
I/O ground
B19
VSSIO
Pad ground
I/O ground
B20
nURESET
C1
RUN/CLKEN
1
C2
EXPRDY
1
C3
VDDIO
C4
nCS[4]
1
High
O
Chip select 4
C5
nCS[0]
1
High
O
Chip select 0
C6
N/C
C7
N/C
C8
DD[0]
1
Low
O
LCD serial display data
C9
DD[3]
1
Low
O
LCD serial display data
C10
VDDCORE
Core power
Digital core power, 2.5 V
C11
A[0]
2
Low
O
System byte address
C12
D[2]
1
Low
I/O
Data I/O
C13
A[3]
2
Low
O
System byte address
C14
D[5]
1
Low
I/O
Data I/O
C15
A[6]
1
Low
O
System byte address
C16
VSSOSC
Oscillator ground
PLL ground
C17
VDDOSC
Oscillator power
Oscillator power in, 2.5V
C18
VSSIO
Pad ground
C19
BATOK
I
32
1
Reset
State
Schmitt
Schmitt
Low
Data I/O
I
System wake up input
I
Main oscillator input
I
User reset input
0
Run output / clock enable output
I
Expansion port ready input
Pad power
Digital I/O power,
3.3 V
I/O ground
Battery ok input
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Table 20. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
†
Strength
C20
nPOR
Schmitt
D1
PB[7]
1
D2
Reset
State
Type
Description
I
Power-on reset input
I
GPIO port B
RXD[2]
I
UART 2 receive data input
D3
VDDIO
Pad power
Digital I/O power, 3.3V
D18
VSSIO
Pad ground
I/O ground
D19
nBATCHG
D20
A[7]
1
Low
E1
PB[4]
1
E2
TXD[2]
E3
WRITE/nSDRAS
E18
‡
Input
I
Battery changed sense input
O
System byte address
Input
I
GPIO port B
1
High
O
UART 2 transmit data output
1
Low
O
Transfer direction / SDRAM RAS signal output
nMEDCHG/nBROM
I
Media change interrupt input / internal ROM boot enable
E19
nEXTPWR
I
External power supply sense input
E20
D[9]
1
Low
F1
PB[3]
1
Input
F2
PB[6]
1
Input
F3
TDI
with p/u*
F18
D[7]
1
Low
I/O
Data I/O
F19
A[8]
1
Low
O
System byte address
F20
D[10]
1
Low
I/O
Data I/O
G1
PB[1]
1
Input
G2
PB[2]
1
Input
G3
PB[5]
1
Input
G18
D[8]
1
Input
G19
A[9]
1
G20
D[11]
H1
‡
I/O
Data I/O
‡
I/O
GPIO port B
‡
I/O
I
GPIO port B
JTAG data input
‡
I/O
‡
I/O
GPIO port B
‡
I/O
GPIO port B
‡
I/O
Data I/O
Low
O
System byte address
1
Low
I/O
Data I/O
PA[7]
1
Input
‡
I/O
GPIO port A
H[2]
TDO
1
Input
‡
O
JTAG data out
H[3]
PB[0]
1
Input
‡
I/O
GPIO port B
H[18]
A[10]
1
Low
O
System byte address
H19
D[12]
1
Low
I/O
Data I/O
H20
A[12]
1
Low
O
System byte address
J1
PA[4]
1
Input
I/O
GPIO port A
DS507F1
‡
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
33
EP7309
High-Performance, Low-Power System on Chip
Table 20. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
†
Strength
Reset
State
Type
Description
‡
I/O
GPIO port A
Input
‡
I/O
GPIO port A
1
Low
O
System byte address
D[13]
1
Low
I/O
Data I/O
J20
A[13]/DRA[14]
1
Low
O
System byte address / SDRAM address
K1
PA[1]
1
Input
K2
PA[2]
1
Input
K3
VDDIO
K18
D[14]
1
Low
I/O
Data I/O
K19
A[14]/DRA[13]
1
Low
O
System byte address / SDRAM address
K20
D[15]
1
Low
I/O
Data I/O
L1
TXD[1]
1
High
O
UART 1 transmit data out
L2
LEDDRV
1
Low
O
IR LED drive
L3
PA[3]
1
Input
I/O
GPIO port A
L18
VDDIO
L19
D[16]
1
Low
I/O
Data I/O
L20
A[16]/DRA[11]
1
Low
O
System byte address / SDRAM address
M1
RXD[1]
I
UART 1 receive data input
M2
CTS
I
UART 1 clear to send input
M3
PA[0]
1
Input
I/O
M18
A[15]/DRA[12]
1
Low
O
System byte address / SDRAM address
M19
A[17]/DRA[10]
1
Low
O
System byte address / SDRAM address
M20
nTRST
I
JTAG async reset input
N1
DSR
I
UART 1 data set ready input
N2
nTEST[1]
I
Test mode select input
N3
PHDIN
I
Photodiode input
N18
D[17]
1
Low
I/O
Data I/O
N19
D[19]
1
Low
I/O
Data I/O
N20
A[18]/DRA[9]
1
Low
O
System byte address / SDRAM address
P1
EINT[3]
I
External interrupt
P2
nEINT[2]
I
External interrupt input
P3
DCD
I
UART 1 data carrier detect
P18
D[18]
1
Low
I/O
Data I/O
P19
A[20]/DRA[7]
1
Low
O
System byte address / SDRAM address
J2
PA[5]
1
Input
J3
PA[6]
1
J18
A[11]
J19
34
‡
I/O
GPIO port A
‡
I/O
GPIO port A
Pad power
‡
Pad power
‡
With p/u*
Digital I/O power, 3.3V
Digital I/O power, 3.3V
GPIO port A
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Table 20. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
†
Strength
Type
Low
I/O
Description
P20
D[20]
R1
nEXTFIQ
R2
PE[2]/CLKSEL
R3
nTEST[0]
R18
A[19]/DRA[8]
1
Low
O
System byte address / SDRAM address
R19
D[22]
1
Low
I/O
Data I/O
R20
A[21]/DRA[6]
1
Low
O
System byte address / SDRAM address
T1
PE[1]/BOOTSEL[1]
1
Input
T2
PE[0]/BOOTSEL[0]
1
Input
T3
nEINT[1]
T18
D[21]
1
Low
I/O
Data I/O
T19
D[23]
1
Low
I/O
Data I/O
T20
A[22]/DRA[5]
1
Low
O
System byte address / SDRAM address
U1
VSSRTC
RTC ground
U2
RTCOUT
O
Real time clock oscillator output
U3
RTCIN
I/O
Real time clock oscillator input
U18
HALFWORD
1
Low
O
Halfword access select output
U19
D[24]
1
Low
I/O
Data I/O
U20
A[23]/DRA[4]
1
Low
O
System byte address / SDRAM address
V1
VDDRTC
RTC power
Real time clock power, 2.5V
V2
VSSIO
Pad ground
I/O ground
V3
VSSIO
Pad ground
I/O ground
V4
PD[7]/SDQM[1]
1
Low
I/O
GPIO port D / SDRAM byte lane mask
V5
PD[4]
1
Low
I/O
GPIO port D
V6
PD[2]
1
Low
I/O
GPIO port D
V7
SSICLK
1
Input
I/O
DAI/CODEC/SSI2 serial clock
V8
SSIRXDA
I/O
DAI/CODEC/SSI2 serial data input
V9
nADCCS
O
SSI1 ADC chip select
V10
VDDIO
Pad power
Digital I/O power, 3.3V
V11
ADCCLK
1
Low
O
SSI1 ADC serial clock
V12
COL[7]
1
High
O
Keyboard scanner column drive
V13
COL[4]
1
High
O
Keyboard scanner column drive
V14
TCLK
I
JTAG clock
V15
BUZ
1
Low
O
Buzzer drive output
V16
D[29]
1
Low
I/O
Data I/O
DS507F1
1
Reset
State
I
1
‡
Input
With p/u*
I/O
External fast interrupt input
GPIO port E / clock input mode select
I
Test mode select input
‡
I/O
GPIO port E / boot mode select
‡
I/O
GPIO port E / boot mode select
I
1
Data I/O
‡
High
External interrupt input
Real time clock ground
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
35
EP7309
High-Performance, Low-Power System on Chip
Table 20. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
†
Strength
Type
Low
O
Description
V17
A[26]/DRA[1]
V18
VDDIO
Pad power
Digital I/O power,
3.3 V
V19
VDDIO
Pad power
Digital I/O power,
3.3 V
V20
A[24]/DRA[3]
W1
VSSIO
Pad ground
I/O ground
W2
VSSIO
Pad ground
I/O ground
W3
VSSIO
Pad ground
I/O ground
W4
PD[6]/SDQM[0]
W5
TMS
with p/u*
W6
PD[1]
1
Low
I/O
GPIO port D
W7
SSITXFR
1
Low
I/O
DAI/CODEC/SSI2 frame sync
W8
SSIRXFR
1
Input
I/O
DAI/CODEC/SSI2 frame sync
W9
VSSCORE
W10
DRIVE[1]
2
High /
Low
I/O
PWM drive output
W11
ADCOUT
1
Low
O
SSI1 ADC serial data output
W12
FB[0]
I
PWM feedback input
W13
COL[5]
1
High
O
Keyboard scanner column drive
W14
COL[2]
1
High
O
Keyboard scanner column drive
W15
COL[0]
1
High
O
Keyboard scanner column drive
W16
D[30]
1
Low
I/O
Data I/O
W17
A[27]/DRA[0]
2
Low
O
System byte address / SDRAM address
W18
D[26]
1
Low
I/O
Data I/O
W19
VDDIO
W20
D[25]
Y1
VSSIO
Pad ground
I/O ground
Y2
VSSIO
Pad ground
I/O ground
Y3
VSSIO
Pad ground
I/O ground
Y4
PD[5]
1
Low
I/O
GPIO port D
Y5
PD[3]
1
Low
I/O
GPIO port D
Y6
PD[0]/LEDFLSH
1
Low
I/O
GPIO port D / LED blinker output
Y7
SSITXDA
1
Low
O
DAI/CODEC/SSI2 serial data output
Y8
ADCIN
I
SSI1 ADC serial input
Y9
VDDCORE
Y10
DRIVE[0]
36
2
Reset
State
‘
1
Low
Low
O
I/O
I
‡
Core Ground
Pad power
1
Low
I/O
Core power
2
‡
Input
I/O
System byte address / SDRAM address
System byte address / SDRAM address
GPIO port D / SDRAM byte lane mask
JTAG mode select
Core Ground
Digital I/O power, 3.3V
Data I/O
Digital core power, 2.5V
PWM drive output
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Table 20. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
†
Strength
Type
Low
O
SSI1 ADC sample clock
I
PWM feedback input
Description
Y11
SMPCLK
Y12
FB[1]
Y13
COL[6]
1
High
O
Keyboard scanner column drive
Y14
COL[3]
1
High
O
Keyboard scanner column drive
Y15
COL[1]
1
High
O
Keyboard scanner column drive
Y16
D[31]
1
Low
I/O
Data I/O
Y17
D[28]
1
Low
I/O
Data I/O
Y18
D[27]
1
Low
I/O
Data I/O
Y19
A[25]/DRA[2]
2
Low
O
System byte address / SDRAM address
Y20
1
Reset
State
VDDIO
Pad power
Digital I/O power, 3.3V
*“With p/u” means with internal pull-up of 100 KOhms on the pin.
†
Strength 1 = 4 ma
Strength 2 = 12 ma
‡
Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
37
EP7309
High-Performance, Low-Power System on Chip
256-Ball PBGA Package Characteristics
256-Ball PBGA Package Specifications
0.85 (0.034)
±0.05 (.002)
17.00 (0.669)
±0.20 (.008)
Pin 1 Corner
D1
0.40 (0.016)
±0.05 (.002)
15.00 (0.590)
±0.20 (.008)
30° TYP
Pin 1 Indicator
17.00 (0.669)
±0.20 (.008)
E1
15.00 (0.590)
±0.20 (.008)
2 Layer
0.36 (0.014)
±0.09 (0.004)
TOP VIEW
SIDE VIEW
D
17.00 (0.669)
1.00 (0.040)
REF
E
16 15 14 13 12 11 10 9 8 7
6 5
1.00 (0.040)
REF
4 3 2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1.00 (0.040)
0.50
R
3 Places
Pin 1 Corner
1.00 (0.040)
17.00 (0.669)
BOTTOM VIEW
JEDEC #: MO-151
Ball Diameter: 0.50 mm ± 0.10 mm
17 ¥ 17 ¥ 1.61 mm body
Figure 14. 256-Ball PBGA Package
Note:
38
1) For pin locations see Table 21.
2) Dimensions are in millimeters (inches), and controlling dimension is millimeter
3) Before beginning any new EP7309 design, contact Cirrus Logic for the latest package information.
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
256-Ball PBGA Pinout (Top View))
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VDDIO
nCS[4]
nCS[1]
N/C
N/C
DD[1]
M
VDDIO
D[0]
D[2]
A[3]
VDDIO
A[6]
B
nCS[5]
VDDIO
nCS[3]
nMOE
VDDIO
N/C
DD[2]
CL[1]
VDDCORE
D[1]
A[2]
A[4]
A[5]
WAKEUP
VDDIO
nURESET B
C
VDDIO
EXPCLK
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
nPOR
nEXTPWR C
D
WRITE
EXPRDY
VSSIO
VDDIO
nCS[2]
nMWE
N/C
CL[2]
VSSRTC
D[4]
nPWRFL
MOSCIN
VDDIO
VSSIO
D[7]
D[8]
D
E
RXD[2]
PB[7]
TDI
WORD
VSSIO
nCS[0]
N/C
FRM
A[0]
D[5]
VSSOSC
VSSIO
nMEDCHG/
nBROM
VDDIO
D[9]
D[10]
E
F
PB[5]
PB[3]
VSSIO
TXD[2]
RUN/
CLKEN
VSSIO
N/C
DD[3]
A[1]
D[6]
VSSRTC
BATOK
nBATCHG
VSSIO
D[11]
VDDIO
F
G
PB[1]
VDDIO
TDO
PB[4]
PB[6]
VSSRTC
VSSRTC
DD[0]
D[3]
VSSRTC
A[7]
A[8]
A[9]
VSSIO
D[12]
D[13]
G
H
PA[7]
PA[5]
VSSIO
PA[4]
PA[6]
PB[0]
PB[2]
VSSRTC
VSSRTC
A[10]
A[11]
A[12]
A[13]
VSSIO
D[14]
D[15]
H
J
PA[3]
PA[1]
VSSIO
PA[2]
PA[0]
TXD[1]
CTS
VSSRTC
VSSRTC
A[17]
A[16]
A[15]
A[14]
nTRST
D[16]
D[17]
J
PHDIN
VSSIO
DCD
nTEST[1]
EINT[3]
VSSRTC
ADCIN
COL[4]
TCLK
D[20]
D[19]
D[18]
VSSIO
VDDIO
VDDIO
K
DSR
VDDIO
nEINT[1]
PE[2]/
CLKSEL
VSSRTC
COL[6]
D[31]
VSSRTC
A[22]
A[21]
VSSIO
A[18]
A[19]
L
nEINT[2]
VDDIO
PE[0]/
BOOTSEL[0]
TMS
VDDIO
SSITXFR
DRIVE[1]
FB[0]
COL[0]
D[27]
VSSIO
A[23]
VDDIO
A[20]
D[21]
M
VDDIO
PD[5]
PD[2]
SSIRXDA
ADCCLK
SMPCLK
COL[2]
D[29]
D[26]
HALFWORD
VSSIO
D[22]
D[23]
N
K LEDDRV
L
RXD[1]
M nTEST[0]
N nEXTFIQ
PE[1]/
VSSIO
BOOTSEL[1]
P VSSRTC
R
RTCIN
T VDDRTC
PD[0]/
VSSRTC
LEDFLSH
14
15
16
MOSCOUT VDDOSC
VSSIO
A
RTCOUT
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
D[24]
VDDIO
P
VDDIO
PD[4]
PD[1]
SSITXDA
nADCCS
VDDIO
ADCOUT
COL[7]
COL[3]
COL[1]
D[30]
A[27]
A[25]
VDDIO
A[24]
R
PD[7]
PD[6]
PD[3]
SSICLK
FB[1]
COL[5]
VDDIO
BUZ
D[28]
A[26]
D[25]
VSSIO
T
SSIRXFR VDDCORE DRIVE[0]
256-Ball PBGA Ball Listing
The list is ordered by ball location.
Table 21. 256-Ball PBGA Ball Listing (Continued)
Table 21. 256-Ball PBGA Ball Listing
Ball Location
Name
Type
A1
VDDIO
Pad power
Ball Location
Name
Type
Description
A12
VDDIO
Pad power
A13
A[6]
O
System byte address
A14
MOSCOUT
O
Main oscillator out
A15
VDDOSC
Oscillator
power
A16
VSSIO
Description
Digital I/O power, 3.3V
Digital I/O power, 3.3V
A2
nCS[4]
O
Chip select out
A3
nCS[1]
O
Chip select out
Oscillator power in, 2.5V
A4
N/C
O
A5
N/C
O
A6
DD[1]
O
LCD serial display data
B1
nCS[5]
O
A7
M
O
LCD AC bias drive
B2
VDDIO
Pad power
A8
VDDIO
Pad power
Digital I/O power, 3.3V
B3
nCS[3]
O
Chip select out
A9
D[0]
I/O
Data I/O
B4
nMOE
O
ROM, expansion OP enable
A10
D[2]
I/O
Data I/O
B5
VDDIO
Pad power
A11
A[3]
O
System byte address
B6
N/C
O
DS507F1
Pad ground I/O ground
Chip select out
I/O ground
Digital I/O power, 3.3V
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
39
EP7309
High-Performance, Low-Power System on Chip
Table 21. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
B7
DD[2]
O
LCD serial display data
E7
N/C
O
B8
CL[1]
O
LCD line clock
E8
FRM
O
LCD frame synchronization pulse
Description
B9
VDDCORE
B10
D[1]
I/O
Data I/O
B11
A[2]
O
System byte address
B12
A[4]
O
System byte address
B13
A[5]
O
System byte address
B14
WAKEUP
I
B15
VDDIO
Pad power
B16
nURESET
I
C1
VDDIO
C2
EXPCLK
C3
VSSIO
C4
Ball Location
Core power Digital core power, 2.5V
Name
Type
Description
E9
A[0]
O
System byte address
E10
D[5]
I/O
Data I/O
E11
VSSOSC
Oscillator
ground
E12
VSSIO
System wake up input
E13
nMEDCHG/nBROM
I
VDDIO
Pad power
PLL ground
Pad ground I/O ground
Media change interrupt input / internal
rom boot enable
Digital I/O power, 3.3V
E14
User reset input
E15
D[9]
I/O
Data I/O
Pad power
Digital I/O power, 3.3V
E16
D[10]
I/O
Data I/O
I
Expansion clock input
F1
PB[5]
I
GPIO port B
Pad ground I/O ground
F2
PB[3]
I
GPIO port B
VDDIO
Pad power
F3
VSSIO
C5
VSSIO
Pad ground I/O ground
F4
TXD[2]
O
UART 2 transmit data output
C6
VSSIO
Pad ground I/O ground
F5
RUN/CLKEN
O
Run output / clock enable output
C7
VSSIO
Pad ground I/O ground
F6
VSSIO
C8
VDDIO
Pad power
F7
N/C
O
C9
VSSIO
Pad ground I/O ground
F8
DD[3]
O
LCD serial display data
C10
VSSIO
Pad ground I/O ground
F9
A[1]
O
System byte address
C11
VSSIO
Pad ground I/O ground
F10
D[6]
I/O
Data I/O
C12
VDDIO
Pad power
F11
VSSRTC
C13
VSSIO
Pad ground I/O ground
F12
BATOK
I
Battery ok input
C14
VSSIO
Pad ground I/O ground
F13
nBATCHG
I
Battery changed sense input
C15
nPOR
I
Power-on reset input
F14
VSSIO
C16
nEXTPWR
I
External power supply sense input
F15
D[11]
I/O
D1
WRITE
O
Transfer direction
F16
VDDIO
Pad power
D2
EXPRDY
I
Expansion port ready input
D3
VSSIO
Pad ground I/O ground
D4
VDDIO
Pad power
Digital I/O power, 3.3V
Digital I/O power, 3.3V
Digital I/O power, 3.3V
Digital I/O power, 3.3V
D5
nCS[2]
O
Chip select out
D6
nMWE
O
ROM, expansion write enable
D7
N/C
D8
CL[2]
D9
VSSRTC
D10
D[4]
D11
nPWRFL
O
O
LCD pixel clock out
Core ground Real time clock ground
I/O
I
Data I/O
Power fail sense input
D12
MOSCIN
I
D13
VDDIO
Pad power
D14
VSSIO
Pad ground I/O ground
D15
D[7]
I/O
Main oscillator input
Digital I/O power, 3.3V
Data I/O
D16
D[8]
I/O
E1
RXD[2]
I
UART 2 receive data input
E2
PB[7]
I
GPIO port B
E3
E4
40
Type
Table 21. 256-Ball PBGA Ball Listing (Continued)
TDI
WORD
E5
VSSIO
E6
nCS[0]
I
O
Data I/O
JTAG data input
Word access select output
Pad ground I/O ground
O
Chip select out
Digital I/O power, 3.3V
Pad ground I/O ground
Pad ground I/O ground
RTC ground Real time clock ground
Pad ground I/O ground
Data I/O
Digital I/O power, 3.3V
GPIO port B / CL-PS6700 interface
signal
G1
PB[1]/PRDY[2]
I
G2
VDDIO
Pad power
G3
TDO
O
G4
PB[4]
I
GPIO port B
G5
PB[6]
I
GPIO port B
G6
VSSRTC
Core ground Real time clock ground
G7
VSSRTC
RTC ground Real time clock ground
G8
DD[0]
O
LCD serial display data
G9
D[3]
I/O
Data I/O
G10
VSSRTC
G11
A[7]
O
System byte address
G12
A[8]
O
System byte address
G13
A[9]
O
System byte address
G14
VSSIO
G15
D[12]
I/O
Data I/O
G16
D[13]
I/O
Data I/O
H1
PA[7]
I
GPIO port A
H2
PA[5]
I
GPIO port A
H3
VSSIO
H4
PA[4]
I
GPIO port A
H5
PA[6]
I
GPIO port A
Digital I/O power, 3.3V
JTAG data out
RTC ground Real time clock ground
Pad ground I/O ground
Pad ground I/O ground
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Table 21. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
H6
PB[0]/PRDY[1]
I
H7
PB[2]
H8
VSSRTC
H9
VSSRTC
I
Description
O
System byte address
O
System byte address
H12
A[12]
O
System byte address
O
VSSIO
H15
D[14]
I/O
Data I/O
H16
D[15]
I/O
Data I/O
PA[1]
J3
VSSIO
J4
PA[2]
J5
PA[0]
I
I
I
I
UART 1 transmit data out
UART 1 clear to send input
J8
VSSRTC
O
O
System byte address
A[15]
O
System byte address
O
I
D[16]
I/O
Data I/O
D[17]
I/O
Data I/O
PHDIN
K3
VSSIO
K4
DCD
K5
K6
nTEST[1]
EINT[3]
K7
VSSRTC
K8
ADCIN
K9
COL[4]
O
I
I
I
System byte address
O
System byte address
L14
VSSIO
L15
A[18]
O
System byte address
L16
A[19]
O
System byte address
M1
nTEST[0]
I
Test mode select input
M2
nEINT[2]
I
External interrupt input
M3
VDDIO
Pad power
Digital I/O power, 3.3V
M4
PE[0]/BOOTSEL[0]
I
M5
TMS
I
M6
VDDIO
Pad power
M7
SSITXFR
I/O
M8
DRIVE[1]
I/O
M9
FB[0]
I
M10
COL[0]
O
Keyboard scanner column drive
M11
D[27]
I/O
Data I/O
M12
VSSIO
M13
A[23]
O
M14
VDDIO
Pad power
M15
A[20]
O
System byte address
M16
D[21]
I/O
Data I/O
N1
nEXTFIQ
I
External fast interrupt input
N2
PE[1]/BOOTSEL[1]
I
GPIO port E / boot mode select
N3
VSSIO
Pad ground I/O ground
N4
VDDIO
Pad power
N5
PD[5]
I/O
N6
PD[2]
I/O
GPIO port D
N7
SSIRXDA
I/O
DAI/CODEC/SSI2 serial data input
N8
ADCCLK
O
SSI1 ADC serial clock
N9
SMPCLK
O
SSI1 ADC sample clock
N10
COL[2]
O
Keyboard scanner column drive
N11
D[29]
I/O
Data I/O
N12
D[26]
I/O
Data I/O
N13
HALFWORD
O
Halfword access select output
N14
VSSIO
N15
D[22]
Pad ground I/O ground
GPIO port E / Boot mode select
JTAG mode select
Digital I/O power, 3.3V
DAI/CODEC/SSI2 frame sync
PWM drive output
PWM feedback input
Pad ground I/O ground
System byte address
Digital I/O power, 3.3V
I
Digital I/O power, 3.3V
GPIO port D
Test mode select input
External interrupt
RTC ground Real time clock ground
I
O
SSI1 ADC serial input
Keyboard scanner column drive
I
I/O
Data I/O
K12
D[19]
I/O
Data I/O
I/O
JTAG clock
Data I/O
K14
VSSIO
Pad ground I/O ground
K15
VDDIO
Pad power
Digital I/O power, 3.3V
K16
VDDIO
Pad power
Digital I/O power, 3.3V
L1
RXD[1]
I
UART 1 receive data input
L2
DSR
I
UART 1 data set ready input
L3
VDDIO
Pad power
Digital I/O power, 3.3V
L4
nEINT[1]
I
External interrupt input
DS507F1
O
A[21]
UART 1 data carrier detect
D[20]
PE[2]/CLKSEL
A[22]
L13
Pad ground I/O ground
TCLK
L5
L12
RTC ground Real time clock ground
Photodiode input
K11
D[18]
VSSRTC
IR LED drivet
K10
K13
L11
JTAG async reset input
J16
K2
Data I/O
System byte address
J15
LEDDRV
I/O
System byte address
A[16]
K1
Keyboard scanner column drive
D[31]
RTC ground Real time clock ground
J12
nTRST
O
L10
Core ground Real time clock ground
RTC ground Real time clock ground
J11
J14
COL[6]
GPIO port A
I
A[14]
VSSRTC
L9
GPIO port D / LED blinker output
GPIO port A
O
J13
L8
I/O
Pad ground I/O ground
CTS
A[17]
RTC ground Real time clock ground
GPIO port A
TXD[1]
VSSRTC
PD[0]/LEDFLSH
GPIO port A
J7
J9
VSSRTC
L7
Pad ground I/O ground
J6
J10
L6
System byte address
H14
J2
Description
RTC ground Real time clock ground
A[11]
PA[3]
Type
RTC ground Real time clock ground
A[10]
J1
Name
GPIO port B
H11
A[13]
Ball Location
GPIO port B / CL-PS6700 interface
signal
H10
H13
Table 21. 256-Ball PBGA Ball Listing (Continued)
I
Pad ground I/O ground
I/O
Data I/O
I/O
Data I/O
N16
D[23]
P1
VSSRTC
P2
RTCOUT
P3
VSSIO
Pad ground I/O ground
P4
VSSIO
Pad ground I/O ground
P5
VDDIO
Pad power
RTC ground Real time clock ground
O
Real time clock oscillator output
Digital I/O power, 3.3V
GPIO port E / clock input mode select
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
41
EP7309
High-Performance, Low-Power System on Chip
Table 21. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
P6
VSSIO
Pad ground I/O ground
P7
VSSIO
Pad ground I/O ground
P8
VDDIO
Pad power
P9
VSSIO
Pad ground I/O ground
P10
VDDIO
Pad power
P11
VSSIO
Pad ground I/O ground
P12
VSSIO
Pad ground I/O ground
P13
VDDIO
Pad power
P14
VSSIO
Pad ground I/O ground
P15
D[24]
I/O
P16
VDDIO
Pad power
R1
RTCIN
I/O
R2
VDDIO
Pad power
R3
PD[4]
I/O
GPIO port D
R4
PD[1]
I/O
GPIO port D
R5
SSITXDA
O
DAI/CODEC/SSI2 serial data output
R6
nADCCS
O
SSI1 ADC chip select
R7
VDDIO
Pad power
Digital I/O power, 3.3V
R8
ADCOUT
O
SSI1 ADC serial data output
R9
COL[7]
O
Keyboard scanner column drive
R10
COL[3]
O
Keyboard scanner column drive
R11
COL[1]
O
Keyboard scanner column drive
R12
D[30]
I/O
Data I/O
R13
A[27]
O
System byte address
System byte address
42
Type
R14
A[25]
O
R15
VDDIO
Pad power
Description
Digital I/O power, 3.3V
Digital I/O power, 3.3V
Digital I/O power
Data I/O
Digital I/O power, 3.3V
Real time clock oscillator input
Digital I/O power, 3.3V
Digital I/O power, 3.3V
R16
A[24]
O
T1
VDDRTC
RTC power
System byte address
T2
PD[7]
I/O
GPIO port D
T3
PD[6]
I/O
GPIO port D
T4
PD[3]
I/O
GPIO port D
T5
SSICLK
I/O
DAI/CODEC/SSI2 serial clock
–
DAI/CODEC/SSI2 frame sync
Real time clock power, 2.5V
T6
SSIRXFR
T7
VDDCORE
T8
DRIVE[0]
I/O
T9
FB[1]
I
PWM feedback input
Keyboard scanner column drive
Core power Core power, 2.5V
T10
COL[5]
O
T11
VDDIO
Pad power
PWM drive output
Digital I/O power, 3.3V
T12
BUZ
O
Buzzer drive output
T13
D[28]
I/O
Data I/O
T14
A[26]
O
System byte address
T15
D[25]
I/O
Data I/O
T16
VSSIO
Pad ground I/O ground
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
JTAG Boundary Scan Signal Ordering
Table 22. JTAG Boundary Scan Signal Ordering
DS507F1
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball
Signal
Type
Position
1
B3
B1
nCS[5]
O
1
4
A2
C2
EXPCLK
I/O
3
5
B1
E4
WORD
O
6
6
E3
D1
WRITE
O
8
7
C1
F5
RUN/CLKEN
O
10
8
C2
D2
EXPRDY
I
13
9
E2
F4
TXD2
O
14
10
D2
E1
RXD2
I
16
13
F3
E2
PB[7]
I/O
17
14
D1
G5
PB[6]
I/O
20
15
F2
F1
PB[5]
I/O
23
16
G3
G4
PB[4]
I/O
26
17
E1
F2
PB[3]
I/O
29
18
F1
H7
PB[2]
I/O
32
19
G2
G1
PB[1]/PRDY2
I/O
35
20
G1
H6
PB[0]/PRDY1
I/O
38
23
H3
H1
PA[7]
I/O
41
24
H1
H5
PA[6]
I/O
44
25
J3
H2
PA[5]
I/O
47
26
J2
H4
PA[4]
I/O
50
27
J1
J1
PA[3]
I/O
53
28
L3
J4
PA[2]
I/O
56
29
K2
J2
PA[1]
I/O
59
30
K1
J5
PA[0]
I/O
62
31
M3
K1
LEDDRV
O
65
32
L2
J6
TXD1
O
67
34
L1
K2
PHDIN
I
69
35
N3
J7
CTS
I
70
36
M2
L1
RXD1
I
71
37
M1
K4
DCD
I
72
38
P3
L2
DSR
I
73
39
N1
K5
nTEST1
I
74
40
N2
M1
nTEST0
I
75
41
R3
K6
EINT3
I
76
42
P1
M2
nEINT2
I
77
43
P2
L4
nEINT1
I
78
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
43
EP7309
High-Performance, Low-Power System on Chip
Table 22. JTAG Boundary Scan Signal Ordering (Continued)
44
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball
Signal
Type
Position
44
T3
N1
nEXTFIQ
I
79
45
R1
L5
PE[2]/CLKSEL
I/O
80
46
R2
N2
PE[1]/BOOTSEL1
I/O
83
47
T1
M4
PE[0]/BOOTSEL0
I/O
86
53
T2
T2
PD[7]
I/O
89
54
V4
T3
PD[6]
I/O
92
55
W4
N5
PD[5]
I/O
95
56
Y4
R3
PD[4]
I/O
98
59
V5
T4
PD[3]
I/O
101
60
W5
N6
PD[2]
I/O
104
61
Y5
R4
PD[1]
I/O
107
62
V6
L7
PD[0]/LEDFLSH
O
110
68
W6
T6
SSIRXFR
I/O
122
69
Y6
K8
ADCIN
I
125
70
W8
R6
nADCCS
O
126
75
Y8
M8
DRIVE1
I/O
128
76
V9
T8
DRIVE0
I/O
131
77
W10
N8
ADCCLK
O
134
78
Y10
R8
ADCOUT
O
136
79
V11
N9
SMPCLK
O
138
80
W11
T9
FB1
I
140
82
Y11
M9
FB0
I
141
83
Y12
R9
COL7
O
142
84
W12
L9
COL6
O
144
85
V12
T10
COL5
O
146
86
Y13
K9
COL4
O
148
87
W13
R10
COL3
O
150
88
V13
N10
COL2
O
152
91
Y14
R11
COL1
O
154
92
W14
M10
COL0
O
156
93
A1
T12
BUZ
O
158
94
V14
L10
D[31]
I/O
160
95
Y15
R12
D[30]
I/O
163
96
W15
N11
D[29]
I/O
166
97
V15
T13
D[28]
I/O
169
99
Y16
R13
A[27]
Out
172
100
W16
M11
D[27]
I/O
174
101
V16
T14
A[26]
O
177
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Table 22. JTAG Boundary Scan Signal Ordering (Continued)
DS507F1
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball
Signal
Type
Position
102
Y17
N12
D[26]
I/O
179
103
W17
R14
A[25]
O
182
104
Y18
T15
D[25]
I/O
184
105
V17
N13
HALFWORD
O
187
106
W18
R16
A[24]
O
189
109
Y19
P15
D[24]
I/O
191
110
W20
M13
A[23]
O
194
111
U18
N16
D[23]
I/O
196
112
V20
L12
A[22]
O
199
113
U19
N15
D[22]
I/O
201
114
U20
L13
A[21]
O
204
115
T19
M16
D[21]
I/O
206
117
T20
M15
A[20]
O
209
118
R19
K11
D[20]
I/O
211
119
R20
L16
A[19]
O
214
120
T18
K12
D[19]
I/O
216
121
P19
L15
A[18]
O
219
122
P20
K13
D[18]
I/O
221
126
R18
J10
A[17]
O
224
127
N19
J16
D[17]
I/O
226
128
N20
J11
A[16]
O
229
129
P18
J15
D[16]
I/O
231
130
M19
J12
A[15]
O
234
131
N18
H16
D[15]
I/O
236
132
L20
J13
A[14]
O
239
133
L19
H15
D[14]
I/O
241
134
M18
H13
A[13]
O
244
135
K20
G16
D[13]
I/O
246
136
K19
H12
A[12]
O
249
137
K18
G15
D[12]
I/O
251
138
J20
H11
A[11]
O
254
141
J19
F15
D[11]
I/O
256
142
H20
H10
A[10]
O
259
143
H19
E16
D[10]
I/O
261
144
J18
G13
A[9]
O
264
145
K3
E15
D[9]
I/O
266
146
Y3
G12
A[8]
O
269
147
G20
D16
D[8]
I/O
271
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
45
EP7309
High-Performance, Low-Power System on Chip
Table 22. JTAG Boundary Scan Signal Ordering (Continued)
46
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball
Signal
Type
Position
148
H18
G11
A[7]
O
274
150
F20
D15
D[7]
I/O
276
151
G19
F13
nBATCHG
I
279
152
E20
C16
nEXTPWR
I
280
153
F19
F12
BATOK
I
281
154
G18
C15
nPOR
I
282
155
D20
E13
nMEDCHG/nBROM
I
283
156
F18
B16
nURESET
I
284
161
D19
B14
WAKEUP
I
285
162
E19
D11
nPWRFL
I
286
163
C19
A13
A[6]
O
287
164
C20
F10
D[6]
I/O
289
165
E18
B13
A[5]
O
292
166
B20
E10
D[5]
I/O
294
169
B16
B12
A[4]
O
297
170
A16
D10
D[4]
I/O
299
171
C15
A11
A[3]
O
302
172
B15
G9
D[3]
I/O
304
173
A15
B11
A[2]
O
307
175
C14
A10
D[2]
I/O
309
176
B14
F9
A[1]
O
312
177
A14
B10
D[1]
I/O
314
178
C13
E9
A[0]
O
317
179
B13
A9
D[0]
I/O
319
184
A13
D8
CL2
O
322
185
C12
B8
CL1
O
324
186
B12
E8
FRM
O
326
187
A12
A7
M
O
328
188
C11
F8
DD[3]
I/O
330
189
B11
B7
DD[2]
I/O
333
191
B10
A6
DD[1]
I/O
336
192
A10
G8
DD[0]
I/O
339
193
A9
B6
N/C
O
342
194
B9
D7
N/C
O
344
195
C9
A5
N/C
I/O
346
196
A8
E7
N/C
I/O
349
199
B8
F7
N/C
I/O
352
200
C8
A4
N/C
I/O
355
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Table 22. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball
Signal
Type
Position
201
A7
D6
nMWE
O
358
202
B7
B4
nMOE
O
360
204
C7
E6
nCS[0]
O
362
205
A6
A3
nCS[1]
O
364
206
B6
D5
nCS[2]
O
366
207
C6
B3
nCS[3]
O
368
208
A5
A2
nCS[4]
O
370
1) See EP7309 Users’ Manual for pin naming / functionality.
2) For each pad, the JTAG connection ordering is input,
output, then enable as applicable.
DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
47
EP7309
High-Performance, Low-Power System on Chip
CONVENTIONS
Table 23. Acronyms and Abbreviations (Continued)
Acronym/
Abbreviation
This section presents acronyms, abbreviations, units of
measurement, and conventions used in this data sheet.
Acronyms and Abbreviations
Table 23 lists abbreviations and acronyms used in this data
sheet.
Table 23. Acronyms and Abbreviations
Acronym/
Abbreviation
Definition
TAP
test access port
TLB
translation lookaside buffer
UART
universal asynchronous receiver
Units of Measurement
Table 24. Unit of Measurement
Definition
Symbol
Unit of Measure
A/D
analog-to-digital
ADC
analog-to-digital converter
°C
degree Celsius
CODEC
coder / decoder
fs
sample frequency
D/A
digital-to-analog
Hz
hertz (cycle per second)
DMA
direct-memory access
kbps
kilobits per second
EPB
embedded peripheral bus
KB
kilobyte (1,024 bytes)
FCS
frame check sequence
kHz
kilohertz
FIFO
first in / first out
kΩ
kilohm
FIQ
fast interrupt request
Mbps
megabits (1,048,576 bits) per second
GPIO
general purpose I/O
MB
megabyte (1,048,576 bytes)
ICT
in circuit test
MBps
megabytes per second
IR
infrared
MHz
megahertz (1,000 kilohertz)
IRQ
standard interrupt request
µA
microampere
IrDA
Infrared Data Association
µF
microfarad
JTAG
Joint Test Action Group
µW
microwatt
LCD
liquid crystal display
µs
microsecond (1,000 nanoseconds)
LED
light-emitting diode
mA
milliampere
LQFP
low profile quad flat pack
mW
milliwatt
LSB
least significant bit
ms
millisecond (1,000 microseconds)
MIPS
millions of instructions per second
ns
nanosecond
MMU
memory management unit
V
volt
MSB
most significant bit
W
watt
PBGA
plastic ball grid array
PCB
printed circuit board
PDA
personal digital assistant
PLL
phase locked loop
p/u
pull-up resistor
RISC
reduced instruction set computer
RTC
Real-Time Clock
SIR
slow (9600–115.2 kbps) infrared
SRAM
static random access memory
SSI
synchronous serial interface
48
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
General Conventions
Pin Description Conventions
Hexadecimal numbers are presented with all letters in
uppercase and a lowercase “h” appended or with a 0x at the
beginning. For example, 0x14 and 03CAh are hexadecimal
numbers. Binary numbers are enclosed in single quotation
marks when in text (for example, ‘11’ designates a binary
number). Numbers not indicated by an “h”, 0x or quotation
marks are decimal.
Abbreviations used for signal directions are listed in Table 25.
Registers are referred to by acronym, with bits listed in
brackets separated by a colon (:) (for example, CODR[7:0]),
and are described in the EP7309 User’s Manual. The use of
“TBD” indicates values that are “to be determined,” “n/a”
designates “not available,” and “n/c” indicates a pin that is a
“no connect.”
DS507F1
Table 25. Pin Description Conventions
Abbreviation
Direction
I
Input
O
Output
I/O
Input or Output
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
49
EP7309
High-Performance, Low-Power System on Chip
Ordering Information
Model
EP7309-CB
EP7309-CBZ (Lead Free)
EP7309-CV
EP7309-CVZ (Lead Free)
EP7309-IB
EP7309-IBZ (Lead Free)
EP7309-IR
Package
Temperature
256-pin BGA, 17mm X 17mm
0 to +70 °C
208-pin LQFP.
256-pin BGA, 17mm X 17mm
-40 to +85 °C.
204-pin BGA, 13mm X 13mm.
Environmental, Manufacturing, & Handling Information
Model Number
Peak Reflow Temp
EP7309-CB
225 °C
EP7309-CBZ (Lead Free)
260 °C
EP7309-CV
225 °C
EP7309-CVZ (Lead Free)
260 °C
EP7309-IB
225 °C
EP7309-IBZ (Lead Free)
260 °C
EP7309-IR
225 °C
MSL Rating*
Max Floor Life
3
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
50
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Revision History
Revision
Date
Changes
PP1
NOV 2003
First preliminary release.
F1
AUG 2005
Updated SDRAM timing. Added MSL data.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
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SPI is a trademark of Motorola, Inc.
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DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
51