PA79 PA79 P r o d u c t IInnnnoovvaa t i o n FFr roomm Power Operational Amplifier FEATURES DESCRIPTION The PA79 is a high voltage, high speed, low idle current op-amp capable of delivering up to 200mA peak output current. Due to the dynamic biasing of the input stage, it can achieve slew rates over 350V/µs, while only consuming less than 1mA of idle current. External phase compensation allows great flexibility for the user to optimize bandwidth and stability. The output stage is protected with user selected current limit resistor. For the selection of this current limiting resistor, pay close attention to the SOA curves for each package type. Proper heatsinking is required for maximum reliability. ♦ A Unique (Patent Pending) Technique for Very Low Quiescent Current ♦ Over 350 V/µs Slew Rate ♦ Wide Supply Voltage ♦ Single Supply: 20V To 350V ♦ Split Supplies: ± 10V To ± 175V ♦ Output Current – Per Amplifier – 150mA Cont.; 200mA Pk ♦ Up to 26 Watt Dissipation Capability (Dual) ♦ Over 200 kHz Power Bandwidth APPLICATIONS ♦ Piezoelectric Positioning and Actuation ♦ Electrostatic Deflection ♦ Deformable Mirror Actuators ♦ Chemical and Biological Stimulators BLOCK DIAGRAM ACTIVE LOAD VOUT+ BUFFER V+ V– CLASS AB INPUT STAGE ACTIVE LOAD VOUT– CURRENT LIMIT VOUT 20–Pin PSOP PACKAGE STYLE DK PA79U http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2009 (All Rights Reserved) JJUL 20091 APEX − PA79UREVB PA79 P r o d u c t I n n o v a t i o nF r o m Characteristics and Specifications Absolute Maximum Ratings Max Units SUPPLY VOLTAGE, +VS to −VS Parameter Symbol Min 350 V OUTPUT CURRENT, peak (200ms), within SOA 200 mA POWER DISSIPATION, internal, DC Single 14 W POWER DISSIPATION, internal, DC Dual 26 W INPUT VOLTAGE, differential −15 15 V INPUT VOLTAGE, common mode −VS +VS V 150 °C TEMPERATURE, junction (Note 2) TEMPERATURE RANGE, storage −55 125 °C OPERATING TEMPERATURE, case −40 125 °C Specifications Parameter Test Conditions Min Typ Max 8 40 Units INPUT OFFSET VOLTAGE -40 OFFSET VOLTAGE vs. temperature 0 to 125°C (Case Temperature) -63 OFFSET VOLTAGE vs. supply mV µV/°C 32 µV/V BIAS CURRENT, initial 8.5 200 pA OFFSET CURRENT, initial 12 400 pA INPUT RESISTANCE, DC 10 Ω 8 COMMON MODE VOLTAGE RANGE, pos. +VS - 2 V COMMON MODE VOLTAGE RANGE, neg. -VS + 5.5 V COMMON MODE REJECTION, DC NOISE 90 700KHz NOISE, VO NOISE 118 dB 418 µV RMS 500 nV/√Hz 120 dB 1 MHz 50 º V GAIN OPEN LOOP @ 1Hz 89 GAIN BANDWIDTH PRODUCT @ 1MHz PHASE MARGIN Full temperature range OUTPUT VOLTAGE SWING IO = 10mA |VS| - 2 VOLTAGE SWING IO = 100mA |VS| - 8.6 VOLTAGE SWING IO = 150mA |VS| - 10 V 350 V/µS 1 µS CURRENT, continuous, DC |VS| - 12 150 SLEW RATE Package Tab connected to GND SETTLING TIME, to 0.1% 5V Step (No Compensation) 100 V mA POWER BANDWIDTH, 300VP-P +VS = 160V, −VS = -160V 200 kHz OUTPUT RESISTANCE, No load RCL = 6.2Ω 44 Ω POWER SUPPLY VOLTAGE CURRENT, quiescent 2 (Note 5) ±150V Supply ±10 ±150 ±175 V 0.2 0.7 2.5 mA PA79U PA79 P r o d u c t I n n o v a t i o nF r o m Parameter Test Conditions Min Typ Max Units THERMAL RESISTANCE, DC, junction to case, Dual Full temperature range (Note 8) 5.5 RESISTANCE, DC, junction to case, Single Full temperature range 8.3 RESISTANCE, DC, junction to air, Dual Full temperature range 25 RESISTANCE, DC, junction to air, Single Full temperature range ºC/W 9.1 ºC/W ºC/W 19.1 TEMPERATURE RANGE, case ºC/W -40 125 ºC NOTES: 1. Unless otherwise noted: TC = 25°C, DC input specifications are ± value given, power supply voltage is typical rating. 2. Long term operation at the maximum junction temperature will result in reduced product life. Derate power dissipation to achieve high MTTF. 3. +VS and –VS denote the positive and negative supply voltages of the output stage. 4. Rating applies if output current alternates between both output transistors at a rate faster than 60Hz. 5. Supply current increases with signal frequency. See graph on page 4. Applies to each amplifier. 6. Rating applies when the heatslug of the DK package is soldered to a minimum of 1 square inch foil area of a printed circuit board. 7. Rating applies with the JEDEC conditions outlined in the Heatsinksing section of this datasheet. 8. Rating applies when power dissipation is equal in two amplifiers. EXTERNAL CONNECTIONS -IN (A) +IN (A) CR- (A) CR+ (A) CC+ (A) -VS (B) -IN (B) +IN (B) CR+ (B) CR- (B) 1 – +A 20 PA79DK 20 PIN PSOP – +B 10 11 -VS (A) CC- (A) VOUT (A) IL (A) +VS (A) VOUT (B) IL (B) CC- (B) +VS (B) CC+ (B) NOTES: 1. The package heat slug needs to be connected to a stable reference such as gnd for high slew rates. Please refer to special considerations section for details. 2. Supply bypassing required for –VS and +VS. 3. For CC and RC values refer to power supply biasing section. 4. Dimple and ESD triangle denotes pin 1. Typical AppLICATION Circuit The PA79 is ideally suited for driving continuous drop ink jet printers, in both piezo actuation and deflection applications. The high voltage of the amplifier creates an electrostatic field on the deflection plates to control the position of the ink droplets. The rate at which droplets can be printed is directly related to the rate at which the amplifier can drive the plate to a different electrostatic field strength. CF RF RFS +175V +175V CC RL -IN CC+ VIN RC +VS CR+ PA79 (A) +IN -VS CC- -175V RCL RCL RC CL ILIM OUT CR- CC PA79U RIS CFS OUT VOUT 660VPP RC ILIM CC CR+ +VS CC+ -IN PA79 (B) CR- RC CC CC- +IN -VS RN CN -175V 3 PA79 P r o d u c t I n n o v a t i o nF r o m GAIN = -50 250 CURRENT LIMIT, ILIM (mA) 300 GAIN = -100 200 150 100 50 0 1 NO COMPENSATION 100 10 FREQUENCY, (KHz) POWER SUPPLY REJECTION (dB) POWER SUPPLY REJECTION -VS 80 60 +VS 40 20 0 100 1K FREQUENCY, (Hz) 80 10K 140 120 100 80 60 +VS 40 20 –VS 0 0 1000 100 CURRENT LIMIT 160 50 RESISTOR VALUE (Ω) OUTPUT VOLTAGE SWING 12 10 -VS SIDE DROP 8 6 +VS SIDE DROP 4 2 0 OPEN LOOP GAIN 4 80 15 20 0 ONE AMPLIFIER LOADED 10 5 0 0 25 50 75 100 125 CASE TEMPERATURE, TC (°C) 140 120 100 80 60 40 20 0 1 10 100 1K 10K 100K FREQUENCY (Hz) CC = 2.7pF 60 CC = 22pF 33pF PIN 3 TO GND -20 100K Ω +VS TO PIN 3 RC=3.3K Ω -40 10K 100K 1M FREQUENCY (Hz) 20 CC = 22pF CC = 10pF 100 PHASE (°) GAIN (dB) 40 TWO AMPLIFIERS LOADED 25 PHASE RESPONSE 120 CC = 2.7pF CC = 10pF POWER DERATING 30 COMMON MODE REJECTION 0 50 100 150 200 PEAK TO PEAK LOAD CURRENT (mA) NO COMPENSATION 60 100 COMMON MODE REJECTION (dB) POWER RESPONSE VOLTAGE DROP FROM SUPPLY (V) OUTPUT VOLTAGE, (V) 350 INTERNAL POWER DISSIPATION, P (W) TYPICAL PERFORMANCE GRAPHS 40 20 0 NO COMPENSATION -20 -40 -60 10M 33pF PIN 3 TO GND 100K Ω +VS TO PIN 3 Rc = 3.3K Ω -80 10K 100K 1M FREQUENCY (Hz) 10M PA79U PA79 P r o d u c t I n n o v a t i o nF r o m SMALL SIGNAL OPEN LOOP GAIN 100 RC = 3.3K, CC = 2.2pF 40 CS = 68pF PIN = -40dBm RBIAS = OPEN RS = 48.7Ω VS = ±50V 20 0 1 180 45 RC = 3.3K, CC = 22pF 35 RC = 3.3K, CC = 10pF GAIN,dB PHASE, ° 60 0 CS = 68pF -30 PIN = -40dBm = OPEN R -60 RBIAS = 48.7Ω S -90 1 RC = 3.3K, CC = 5pF RC = 3.3K, CC = 2.2pF 120 RC = 3.3K, CC = 22pF FREQUENCY, KHz 1K 10K -5 10 CC = 1pF CC = 2.2pF CC = 5pF CC = 10pF CC = 22pF 100 FREQUENCY, KHz 10K 1K SMALL SIGNAL GAIN vs. COMPENSATION, VO = 5VP-P CC = 0pF 25 15 RC = 3.3K, CC = 5pF RC = 3.3K, CC = 2.2pF CC = 1pF 5 A V = +26 RBIAS = 100K RF = 35.7K RG = 1.5K RL = 50K VS = ±50V -5 -15 RC = 3.3K, CC = 1pF -25 RC = OPEN, CC = 0pF 10 100 FREQUENCY, KHz A V = +26 RBIAS = 100K RC = 3.3K RF = 35.7K RG = 1.5K RL = 50K VS = ±50V 5 35 RC = 3.3K, CC = 10pF 60 CS = 68pF 0 PIN = -40dBm -30 RBIAS = 100K R = 48.7Ω -60 V S = ±50V S -90 1 15 -35 1000 90 30 100 CC = 0pF -25 RC = OPEN, CC = 0pF SMALL SIGNAL OPEN LOOP PHASE 150 50 VP-P SMALL SIGNAL GAIN vs. COMPENSATION, VO = 500mVP-P -15 RC = 3.3K, CC = 1pF 10 100 FREQUENCY, KHz 10 5 VP-P 25 90 180 -25 1000 SMALL SIGNAL OPEN LOOP PHASE, VO = 250mVP-P 30 A V = +51 RBIAS = 100K RC = OPEN RF = 75K RG = 1.5K RL = 50K VS = ±50V 5 -15 RC = 3.3K, CC = 22pF 10 100 FREQUENCY, KHz 120 500 mVP-P 15 -5 RC = 3.3K, CC = 10pF 150 PHASE, ° 25 RC = 3.3K, CC = 5pF GAIN, dB 60 -20 35 RC = 3.3K, CC = 1pF GAIN,dB GAIN, Db 80 GAIN vs. INPUT/OUTPUT SIGNAL LEVEL 45 RC = OPEN, CC = 0pF -35 1000 35 10 CC = 2.2pF CC = 5pF CC = 10pF CC = 22pF 100 FREQUENCY, KHz 1K 10K LARGE SIGNAL GAIN vs. COMPENSATION, VO = 50VP-P CC = 0pF 25 GAIN,dB 15 CC = 1pF 5 -15 -25 -35 PA79U CC = 2.2pF A V = +26 RBIAS = 100K RF = 35.7K RG = 1.5K RL = 50K VS = ±50V -5 10 CC = 5pF CC = 10pF CC = 22pF 100 FREQUENCY, KHz 1K 10K 5 PA79 SR+ SR, V/µs 600 A V = +101 CL = 8pF RF = 25K RG = 250Ω RL = 50K VS = ±150V 400 200 0 2 4 6 8 10 12 PEAK-TO-PEAK INPUT VOLTAGE 14 SR+/SR- (25% -75%) 1000 OUTPUT VOLTAGE, V SRSR, V/µs 600 A V = +51 CL = 8pF RF = 75K RG = 1.5K RL = 50K VS = ±150V 400 200 0 2 4 6 8 10 12 PEAK-TO-PEAK INPUT VOLTAGE 14 SR+/SR- (25% - 75%) 1000 A V = +26 C = 8pF 800 RL = 35.6K F RG = 1.5K R = 50K 600 L VS = ±150V SR, V/µs SR+ SR- -2 0 2 4 TIME, µs 6 8 10 TRANSIENT RESPONSE 1.5 A V = +26 CC = 2.2pF 1 CL = 8pF RC = 3.3K 0.5 RF = 35.7K RG = 1.5K 0 RL = 50K 2VP-P 20 input2 10 -1.2 12 0 -10 -0.5 -20 -1 -2 0 2 4 TIME, µs 6 8 -1.5 12 10 TRANSIENT RESPONSE 10VP-P input10 50 8 A V = +26 CC = 2.2pF CL = 8pF RC = 3.3K RF = 35.7K RG = 1.5K RL = 50K 0 6 4 2 0 -2 -50 -4 2 4 6 8 10 12 PEAK-TO-PEAK INPUT VOLTAGE 14 16 RISE AND FALL TIME (10% - 90%) 0.6 TF 0.4 A V = +51 CL = 8pF RF = 75K RG = 1.5K RL = 50K VS = ±150V TR 2 4 6 8 10 12 PEAK-TO-PEAK INPUT VOLTAGE -2 0 2 4 6 TIME, µs 8 10 -8 12 PULSE RESPONSE vs. CC AND RC 0.2 0 -150 -4 -6 14 16 150 Out - 0pF 120 input 90 60 Out - 1pF & 3.3K 30 0 -30 -60 Out - 5pF & 3.3K -90 -120 -150 -2 -1 0 1 2 3 4 TIME, µs A V = +51 CC = 68pF CL = 330pF RC = 48Ω RF = 75K RG = 1.5K RL = OPEN VS = ±150V 5 6 7 3.0 2.4 1.8 1.2 0.6 0 -0.6 -1.2 -1.8 -2.4 -3.0 INPUT VOLTAGE, V 0 0.8 Time, µs -0.8 -100 1 6 -10 150 200 0 -0.4 100 400 0 -5 -30 -4 16 OUTPUT VOLTAGE, V 0 input1 0 30 SR+ 800 5 -15 -4 16 1VP-P OUTPUT VOLTAGE, V 0 10 1.2 A V = +26 CC = 2.2pF 0.8 CL = 8pF RC = 3.3K 0.4 RF = 35.7K RG = 1.5K 0 RL = 50K INPUT VOLTAGE, V OUTPUT VOLTAGE, V SR- 800 TRANSIENT RESPONSE 15 INPUT VOLTAGE, V SR+/SR- (25% - 75%) 1000 INPUT VOLTAGE, V P r o d u c t I n n o v a t i o nF r o m 8 PA79U PA79 P r o d u c t I n n o v a t i o nF r o m PULSE RESPONSE vs. CAP LOAD 300pf, 3VP-P 200pf, 3VP-P 100pf, 3VP-P 0.1 0.05 A V = -50 RF = 75K RG = 1.5K RL = 50K VS = ±150V 4 6 8 10 12 14 16 18 20 22 24 26 28 30 TIME, µs -0.05 -1 A V = -50 RF = 75K RG = 1.5K RL = 50K VS = ±150V CL = 8pF 2 4 6 100 0 -100 8 10 12 14 16 18 20 22 24 26 28 30 TIME, µs -4 6 INPUT 4 OUTPUT 2 0 -2 -2 0 2 4 TIME, µs 6 8 10 -6 12 7 8 9 IS vs. VIN 18 A V = +51 CL = 8pF CS = 68pF RF = 75K RG = 1.5K RL = 50K RS = 48.7Ω VS = ±150V 16 14 10 8 6 4 2 0 8 10 12 14 16 18 20 22 24 26 28 30 TIME, µs 0 30 25 IS, mA 20 15 10 5 0 10 PA79U 6 5 -4 -300 -6 IS, mA OUTPUT, V A V = -50 RF = 75K RG = 1.5K RL = 50K VS = ±150V 6 4 -200 12 4 2 3 TIME,µs A V = +51 CC = OPEN CL = 8pF RC = OPEN RF = 75K RG = 1.5K RL = 50K VS = ±150V 200 300pF, 1VP-P 200pF, 1VP-P 100pF, 1VP-P 2 1 OVERDRIVE RECOVERY 300 OUTPUT VOLTAGE, V OUTPUT, V 300pF, 2VP-P 200pF, 2VP-P 100pF, 2VP-P 0 INPUT VOLTAGE, V 2 0 PULSE RESPONSE vs. CAP LOAD 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -6 -4 -2 0 A V = +51 CL = 8pF RF = 75K RG = 1.5K RL = 50K VS = ±150V 0.15 PULSE RESPONSE vs. CAP LOAD 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -6 -4 -2 0 PULSE RESPONSE 0.2 IS, A OUTPUT, V 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -6 -4 -2 0 1 2 3 4 5 6 VIN, VP-P (100KHz sine wave) SUPPLY CURRENT vs. FREQUENCY A V = +51 CL = 8pF CS = 68pF RF = 75K RG = 1.5K RL = 50K RS = 48.7Ω VS = ±150V VIN = 6VP VIN = 3VP 100 Frequency, (KHz sine wave) 1000 7 GENERAL Please read Application note 1 “General operating considerations” which covers stability, power supplies, heat sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www. cirrus.com for design tools that help automate tasks such as calculations for stability, internal power dissipation, and current limit. There you will also find a complete application notes library, technical seminar workbook, and evaluation kits. P r o d u c t I n n o v a t i o nF r o m RF = 75K 1000 RG = 1.5K RL = 50K 800 VS = ±150V CL = 8pF SR+(A V = -25) SR-(A V = -25) SR+(A V = +26) SR-(A V = +26) 600 400 200 0 Theory of Operation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PEAK TO PEAK INPUT VOLTAGE SR+/SR- (25%-75%) 1600 R = 75K 1400 RF = 1.5K G 1200 RL = 50K VS = ±150V 1000 C = 8pF L V/µs The PA79 is designed specifically as a high speed pulse amplifier. In order to achieve high slew rates with low idle current, the internal design is quite different from traditional voltage feedback amplifiers. Basic op amp behaviors like high input impedance and high open loop gain still apply. But there are some notable differences, such as signal dependent supply current, bandwidth and output impedance, among others. The impact of these differences varies depending on application performance requirements and circumstances. These different behaviors are ideal for some applications but can make designs more challenging in other circumstances. SR+/SR- (25%-75%) 1200 SR+/SR- V/µs PA79 800 600 SR+(A V = -50) SR-(A V = -50) SR+(A V = +51) SR-(A V = +51) 400 200 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 INPUT VOLTAGE, VOLTS PEAK-TO-PEAK Supply Current and Bypass Capacitance A traditional voltage feedback amplifier relies on fixed current sources in each stage to drive the parasitic capacitances of the next stage. These currents combine to define the idle or quiescent current of the amplifier. By design, these fixed currents are often the limiting parameter for slew rate and bandwidth of the amplifier. Amplifiers which are high voltage and have fast slew rates typically have high idle currents and dissipate notable power with no signal applied to the load. At the heart of the PA79 design is a signal dependent current source which strikes a new balance between supply current and dynamic performance. With small input signals, the supply current of the PA79 is very low, idling at less than 1 mA. With large transient input signals, the supply currents increase dramatically to allow the amplifier stages to respond quickly. The Pulse Response plot in the typical performance section of this datasheet describes the dynamic nature of the supply current with various input transients. Choosing proper bypass capacitance requires careful consideration of the dynamic supply currents. High frequency ceramic capacitors of 0.1µF or more should be placed as close as possible to the amplifier supply pins. The inductance of the routing from the supply pins to these ceramic capacitors will limit the supply of peak current during transients, thus reducing the slew rate of the PA79. The high frequency capacitance should be supplemented by additional bypass capacitance not more than a few centimeters from the amplifier. This additional bypass can be a slower capacitor technology, such as electrolytic, and is necessary to keep the supplies stable during sustained output currents. Generally, a few microfarad is sufficient. Small Signal Performance The small signal performance plots in the typical performance section of this datasheet describe the behavior when the dynamic current sources described previously are near the idle state. The selection of compensation capacitor directly affects the open loop gain and phase performance. Depending on the configuration of the amplifier, these plots show that the phase margin can diminish to very low levels when left uncompensated. This is due to the amount of bias current in the input stage when the part is in 8 PA79U P r o d u c t I n n o v a t i o nF r o m PA79 standby. An increase in the idle current in the output stage of the amplifier will improve phase margin for small signals although will increase the overall supply current. Current can be injected into the output stage by adding a resistor, RBIAS, between CC- and VS+. The size of RBIAS will depend upon the application but 500µA (50V V+ supply/100K) of added bias current shows significant improvement in the small signal phase plots. Adding this resistor has little to no impact on small signal gain or large signal performance as under these conditions the current in the input stage is elevated over its idle value. It should also be noted that connecting a resistor to the upper supply only injects a fixed current and if the upper supply is fixed and well bypassed. If the application includes variable or adjustable supplies, a current source diode could also be used. These two terminal components combine a JFET and resistor connected within the package to behave like a current source. As a second stability measure, the PA79 is externally compensated and performance can be optimized to the application. Unlike the RBIAS technique, external phase compensation maintains the low idle current but does affect the large signal response of the amplifier. Refer to the small and large signal response plots as a guide in making the tradeoffs between bandwidth and stability. Due to the unique design of the PA79, two symmetric compensation networks are required. The compensation capacitor Cc must be rated for a working voltage of the full operating supply voltage (+VS to –VS). NPO capacitors are recommended to maintain the desired level of compensation over temperature. The PA79 requires an external 33pF capacitor between CC- and –VS to prevent oscillations in the falling edge of the output. This capacitor should be rated for the full supply voltage (+VS to –VS). Large Signal Performance As the amplitude of the input signal increases, the internal dynamic current sources increase the operation bandwidth of the amplifier. This unique performance is apparent in its slew rate, pulse response, and large signal performance plots. Recall the previous discussion about the relationships between signal amplitude, supply current, and slew rate. As the amplitude of the input amplitude increases from 1VP-P to 15VP-P, the slew rate increases from 50V/ µs to well over 350V/µs. Notice the knee in the Rise and Fall times plot, at approximately 6VP-P input voltage. Beyond this point the output becomes clipped by the supply rails and the amplifier is no longer operating in a closed loop fashion. The rise and fall times become faster as the dynamic current sources are providing maximum current for slewing. The result of this amplifier architecture is that it slews fast, but allows good control of overshoot for large input signals. This can be seen clearly in the large signal Transient Response plots. Heatsinking and Safe Operating Area The MOSFET output stage of the PA79 is not limited by second breakdown considerations as in bipolar output stages. Only thermal considerations of the package and current handling capabilities limit the Safe Operating Area. The SOA plots include power dissipation limitations which are dependent upon case temperature. Keep in mind that the dynamic current sources which drive high slew rates can increase the operating temperature of the amplifier during periods of repeated slewing. The plot of supply current vs. input signal amplitude for a 100 kHz signal provides an indication of the supply current with repeated slewing conditions. This application dependent condition must be considered carefully. The output stage is self-protected against transient flyback by the parasitic body diodes of the output stage. However, for protection against sustained high energy flyback, external, fast recovery diodes must be used. Current Limit For proper operation, the current limit resistor, RLIM, must be connected as shown in the external connections diagram. For maximum reliability and protection, the largest resistor value should be used. The minimum practical value for RLIM is about 12Ω. However, refer to the SOA curves for each package type to assist in selecting the optimum value for RLIM in the intended application. Current limit may not protect against short circuit conditions with supply voltages over 200V. PA79U 9 PA79 P r o d u c t I n n o v a t i o nF r o m Layout Considerations The PA79 is built on a dielectrically isolated process and the package tab is therefore not electrically connected to the amplifier. For high speed operation, the package tab should be connected to a stable reference to reduce capacitive coupling between amplifier nodes and the floating tab. It is often convenient to directly connect the tab to GND or one of the supply rails, but an AC connection through a 1µF capacitor to GND is also sufficient if a DC connection is undesirable Care should be taken to position the RC / CC compensation networks close to the amplifier compensation pins. Long loops in these paths pick up noise and increase the likelihood of LC interactions and oscillations. The PA79DK package has a large exposed integrated copper heatslug to which the monolithic amplifier is directly attached. The solder connection of the heat slug to a 1 square inch foil area on the printed circuit board will result in improved thermal performance of 25ºC/W. In order to improve the thermal performance, multiple metal layers in the printed circuit board are recommended. This may be adequate heatsinking but the large number of variables involved suggest temperature measurements be made on the top of the package. Do not allow the temperature to exceed 85ºC. The junction to ambient thermal resistance of the DK package can achieve a 19.1ºC/W rating by using the PCB conditions outlined in JEDEC standard: (JESD51–5): PCB Conditions: PCB Layers = 4L, Copper, FR–4 PCB Dimensions = 101.6 x 114.3mm PCB Thickness = 1.6mm Conditions: Power dissipation = 2 watts Ambient Temperature = 55ºC MOISTURE SENSITIVITY The PA79DK has been qualified according to JEDEC 22-A-113-D, MSL 3. The following conditions were used: IR reflow for Pb-free assembly profile where: package thickness is greater than 2.5mm, package volume is greater than 350mm2, TP = 245°C. ELECTROSTATIC DISCHARGE Like many high performance MOSFET amplifiers, the PA79 very sensitive to damage due to electrostatic discharge (ESD). Failure to follow proper ESD handling procedures could have results ranging from reduced operating performance to catastrophic damage. Minimum proper handling includes the use of grounded wrist or shoe straps, grounded work surfaces. Ionizers directed at the work in progress can neutralize the charge build up in the work environment and are strongly recommended. 10 PA79U