SA09
SA09
P r o d u c t IInnnnoovvaa t i o n FFr roomm
Pulse Width Modulation Amplifiers
FEATURES
DESCRIPTION
The SA09 amplifier is a 40 volt, 500kHz PWM amplifier. The full bridge output circuit provides 5 amps of
continuous drive current for applications as diverse as
high fidelity audio and brush type motors. Clock output
and input pins can be used for synchronization with
other amplifiers or an externally generated clock. Direct
access to the pwm input is provided for connection to
digital motion control circuits. Protection circuits guard
against thermal overloads as well as shorts to supply
or ground. The current limit is programmable with one
or two external resistors depending on the application.
A shutdown input disables all output bridge drivers.
The 18 pin steel package is hermetically sealed.
♦ 500kHz SWITCHING
♦ FULL BRIDGE OUTPUT 5-40V (80V P-P)
♦ 5A OUTPUT
♦ 1 IN2 FOOTPRINT
♦ FAULT PROTECTION
♦ SHUTDOWN CONTROL
♦ SYNCHRONIZABLE CLOCK
♦ HERMETIC PACKAGE
APPLICATIONS
♦ HIGH FIDELITY AUDIO AMPLIFIER
♦ BRUSH TYPE MOTOR CONTROL
♦ VIBRATION CANCELLING AMPLIFIER
BLOCK DIAGRAM
AND TYPICAL APPLICATION CONNECTIONS HIGH FIDELITY AUDIO
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SA09U http://www.cirrus.com
Copyright
© Cirrus Logic, Inc. 2009
(All Rights Reserved)
JAN 2009
APEX − SA09REVA
SA09
P r o d u c t I n n o v a t i o nF r o m
EXTERNAL CONNECTIONS
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Case tied to Pin 7. Allow no current in case. Bypassing of supplies is required. If +PWM > RAMP then A OUT > B OUT.
1. Characteristics and Specifications
Absolute Maximum Ratings
Parameter
Symbol
Max
Units
SUPPLY VOLTAGE, +Vs to GND, 10mS surge
60
V
SUPPLY VOLTAGE, +VCC to GND
16
V
OUTPUT CURRENT, peak
7.5
A
POWER DISSIPATION, internal
Min
(Note 3)
TEMPERATURE, pin solder, 10s
TEMPERATURE, junction
(Note 1)
80
W
300
°C
150
°C
TEMPERATURE, storage
−65
150
°C
OPERATING TEMPERATURE RANGE, case
−55
125
°C
INPUTS
−0.4
+5.4
V
CAUTION
The SA09 is constructed from MOSFET transistors. ESD handling procedures must be observed.
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not
crush, machine, or subject to temperatures in excess of 850°C to avoid generating toxic fumes.
SA09U
SA09
P r o d u c t I n n o v a t i o nF r o m
Specifications
Min
Typ
Max
Units
CLOCK OUT
Parameter
Test Conditions
0.98
1
1.02
MHz
CLOCK OUT, high level
4.7
5.3
V
0.2
V
5.012
V
(Note 1)
CLOCK OUT, low level
0
LOAD ≤ 5mA
5V OUT
4.988
5
OUTPUT
EFFICIENCY, 5A output
VS = 40V
SWITCHING FREQUENCY
CURRENT, continuous
CURRENT, peak
(Note 4)
RDS(ON)
(Note 4)
100 ms, 10% duty cycle
94
%
500
kHz
5
A
7
A
0.55
Ω
16
V
40
V
POWER SUPPLY
VOLTAGE, VCC
Full temperature range
10
VOLTAGE, VS
Full temperature range
5
CURRENT, VCC
Switching
50
mA
CURRENT, VS
Switching, no load
90
mA
INPUTS
12
(Note 4)
ILIM /SHDN, trip point
90
110
mV
–PWM, +PWM, low level
0
0.8
V
–PWM, +PWM, high level
2.7
VCC
V
CLOCK IN, low level
0
0.3
V
CLOCK IN, high level
3
5.6
V
3.5
°C/W
THERMAL
(Note 2)
RESISTANCE, junction to case
Full temperature range
RESISTANCE, junction to air
Full temperature range
TEMPERATURE RANGE, case
Meets full range specifications
15
-25
°C/W
85
°C
NOTES:
1. All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken
at typical supply voltages and TC = 25°C.
2. Long term operation at the maximum junction temperature will result in reduced product life. Derate
internal power dissipation to achieve high MTTF. For guidance, refer to the heatsink datasheet.
3. 40W in each of the two active output transistors on at any one time.
4. Min max values guaranteed but not tested.
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Please read Application Note 30 on "PWM Basics". Refer to Application
Note 1 "General Operating Considerations" for helpful information regarding power supplies, heat sinking and mounting. Visit www.apexmicrotech.
com for design tools that help automate pwm filter design and heat sink
selection. The "Application Notes" and "Technical Seminar" sections contain a wealth of information on specific types of applications. Information
on package outlines, heat sinks, mounting hardware and other accessories
are located in the "Packages and Accessories" section. Evaluation Kits are
available for most Apex product models, consult the "Evaluation Kit" section
for details. For the most current version of all Apex product data sheets, visit
www.apexmicrotech.com.
CLOCK CIRCUIT AND RAMP GENERATOR
The clock frequency is internally set to a frequency of approximately 1MHz.
The CLK OUT pin will normally be tied to the CLK IN pin. The clock is divided by two and applied to an RC network
which produces a ramp signal at the RAMP pin. An external clock signal can be applied to the CLK IN pin for synchronization purposes. If a clock frequency lower than 1MHz is chosen an external capacitor must be tied to the
RAMP pin. This capacitor, which parallels an internal capacitor, must be selected so that the ramp oscillates 2.5
volts p-p with the lower peak 1.25 volts above ground.
BYPASSING
Adequate bypassing of the power supplies is required for proper operation. Failure to do so can cause erratic and
low efficiency operation as well as excessive ringing at the outputs. The Vs supply should be bypassed with at least
a 1µF ceramic capacitor in parallel with another low ESR capacitor of at least 10µF per amp of output current. Capacitor types rated for switching applications are the only types that should be considered. The bypass capacitors
must be physically connected directly to the power supply pins. Even one inch of lead length will cause excessive
ringing at the outputs. This is due to the very fast switching times and the inductance of the lead connection. The
bypassing requirements of the VCC supply are less stringent, but still necessary. A 0.1µF to 0.47µF ceramic capacitor
connected directly to the VCC pin will suffice.
NOISE FILTERING
Switching noise can enter the SA09 through the external error amp to +PWM connection. A wise precaution is to low
pass filter this connection. Adjust the pass band of the filter to 10 times the bandwidth required by the application.
Keep the resistor value to 100 ohms or less since this resistor becomes part of the hysteresis circuit on the pwm
comparator.
PCB LAYOUT
The designer needs to appreciate that the SA09 combines in one circuit both high speed high power switching and
low level analog signals. Certain layout rules of thumb must be considered when a circuit board layout is designed
using the SA09:
1. Bypassing of the power supplies is critical. Capacitors must be connected directly to the power supply pins with
very short lead lengths (well under 1 inch). Ceramic chip capacitors are best.
2. Make all ground connections with a star pattern at pin 7.
3. Beware of capacitive coupling between output connections and signal inputs through the parasitic capacitance
between layers in multilayer PCB designs.
4. Do not run small signal traces between the pins of the output section (pins 11-16).
5. Do not allow high currents to flow into the ground plane.
6. Separate switching and analog grounds and connect the two only at pin 7 as part of the star pattern.
SA09U SA09
P r o d u c t I n n o v a t i o nF r o m
CURRENT LIMIT
There are two load current sensing pins, I SENSE A and I SENSE B. The two pins can be shorted in the voltage
mode connection but both must be used in the current mode connection (see figures A and B). It is recommended
that RLIMIT resistors be non-inductive. Load current flows in the I SENSE pins. To avoid errors due to lead lengths
connect the I LIMIT/SHDN pin directly to the RLIMIT resistors (through the filter network and shutdown divider resistor)
and connect the RLIMIT resistors directly to the GND pin. Do not connect RLIMIT sense resistors to the ground plane.
Switching noise spikes will invariably be found at the I SENSE pins. The noise spikes could trip the current limit
threshold which is only 100 mV. RFILTER and CFILTER should be adjusted so as to reduce the switching noise well below 100 mV to prevent false current limiting. The sum of the DC level plus the noise peak will determine the current
limiting value. As in most switching circuits it may be difficult to determine the true noise amplitude without careful
attention to grounding of the oscilloscope probe. Use the shortest possible ground lead for the probe and connect
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exactly at the GND terminal of the amplifier. Suggested starting values are CFILTER = 0.001uF, RFILTER = 5k .
0
The required value of RLIMIT in voltage mode may be calculated by:
RLIMIT = 0.1 V / ILIMIT
where RLIMIT is the required resistor value, and ILIMIT is the maximum desired current. In current mode the required
value of each RLIMIT is 2 times this value since the sense voltage is divided down by 2 (see Figure B). If RSHDN is used
it will further divide down the sense voltage. The shutdown divider network will also have an effect on the filtering
circuit.
SHUTDOWN
The shutdown circuitry makes use of the internal current limiting circuitry. The two functions may be externally
combined in voltage and current modes as shown below in Figures A and B. The RLIMIT resistors will normally be
very low values and can be considered zero for this application. In Figure A, RSHDN and 1K form a voltage divider for
the shutdown signal. After a suitable noise filter is designed for the current limit, adjust the value of RSHDN to give a
minimum 110 mV of shutdown signal at the I LIMIT/SHDN pin when the shutdown signal is high. Note that CFILTER will
filter both the current limit noise spikes and the shutdown signal. Shutdown and current limit operate on each cycle
of the internal switching rate. As long as the shutdown signal is high the output will be disabled.
PROTECTION CIRCUITS
Circuits monitor the temperature and load on each of the bridge output transistors. On each cycle should any fault
condition be detected all output transistors in the bridge are shut off. Faults protected against are: shorts across
the outputs, shorts to ground, and over temperature conditions. Should any of these faults be detected, the output
transistors will be latched off *. In addition there is a built in dead time during which all the output transistors are off.
SA09U
SA09
P r o d u c t I n n o v a t i o nF r o m
The dead time removes the possibility of a momentary conduction path through the upper and lower transistors of
each half bridge during the switching interval. Noise or flyback may be observed at the outputs during this time due
to the high impedance of the outputs in the off state. This will vary with the nature of the load.
* To restart the SA09 remove the fault and recycle VCC or, alternatively, toggle the I LIMIT/SHDN (pin16) with a shut
down pulse.
Contacting Cirrus Logic Support
For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America.
For inquiries via email, please contact [email protected].
International customers can also request support by contacting their local Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE
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SA09U