TI DRV8837DSGR

DRV8837
www.ti.com
SLVSBA4A – JUNE 2012 – REVISED AUGUST 2012
LOW-VOLTAGE H-BRIDGE IC
Check for Samples: DRV8837
FEATURES
DESCRIPTION
•
The DRV8837 provides an integrated motor-driver
solution for cameras, consumer products, toys, and
other low-voltage or battery-powered motion-control
applications. The device has one H-bridge driver, and
can drive one dc motor or one winding of a stepper
motor, as well as other devices like solenoids. The
output driver block consists of N-channel power
MOSFETs configured as an H-bridge to drive the
motor winding. An internal charge pump generates
needed gate-drive voltages.
1
2
•
•
•
•
•
•
•
H-Bridge Motor Driver
– Drives a DC Motor or One Winding of a
Stepper Motor or Other Loads
– Low MOSFET On-Resistance: HS + LS
280 mΩ
1.8-A Maximum Drive Current
1.8-V to 11-V Motor-Operating Supply-Voltage
Range
Separate Motor and Logic Supply Pins
PWM (IN/IN) Interface
Low-Power Sleep Mode With 120-nA Maximum
Combined Supply Current
Dedicated SLEEP Pin
2-mm × 2-mm 8-Pin WSON Package
APPLICATIONS
•
•
•
•
•
•
Cameras
DSLR Lenses
Consumer Products
Toys
Robotics
Medical Devices
The DRV8837 can supply up to 1.8 A of output
current. It operates on a motor power-supply voltage
from 1.8 V to 11 V, and a device power-supply
voltage of 1.8 V to 7 V.
The DRV8837 has a PWM (IN/IN) input interface,
which is compatible with industry-standard devices.
There are internal shutdown functions for overcurrent
protection, short-circuit protection, undervoltage
lockout and overtemperature.
The DRV8837 package is an 8-pin 2-mm × 2-mm
WSON PowerPAD™ package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
DRV8837
SLVSBA4A – JUNE 2012 – REVISED AUGUST 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
ORDERABLE PART NUMBER
PACKAGE
TOPSIDE MARKING
SHIPPING
DRV8837DSGR
WSON – DSG
837
Reel of 3000
DRV8837DSGT
WSON – DSG
837
Reel of 250
For the most-current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
FUNCTIONAL BLOCK DIAGRAM
1.8 to 11 V
VM
VM
VM
Drives DC Motor or
½ Stepper
Gate
Drive
Charge
Pump
OCP
OUT1
1.8 to 7 V
Step
Motor
VCC
DCM
VM
VCC
Logic
Gate
Drive
OCP
OUT2
IN1
IN2
OverTemp
Osc
SLEEP
GND
B0479-01
Figure 1. Functional Block Diagram
2
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DRV8837
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DRV8837
DSG Package
(Top View)
VM
1
OUT1
2
OUT2
3
GND
4
Thermal
Pad
(GND)
8
VCC
7
SLEEP
6
IN1
5
IN2
P0145-01
PIN DESCRIPTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
EXTERNAL COMPONENTS OR CONNECTIONS
Power and Ground
GND
4
–
Device ground
VCC
8
–
Device supply
Bypass to GND with a 0.1-μF 6.3-V ceramic capacitor.
VM
1
–
Motor supply
Bypass to GND with a 0.1-μF 16-V ceramic capacitor.
IN1
6
I
Input 1
Logic-high sets OUT1 high
Internal pulldown resistor
IN2
5
I
Input 2
Logic-high sets OUT2 high
Internal pulldown resistor
SLEEP
7
I
Sleep mode input
Logic-low puts device in low-power sleep mode
Logic-high for normal operation
Internal pulldown resistor
OUT1
2
O
Output 1
OUT2
3
O
Output 2
Control
Output
Connect to motor winding
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1) (2)
VALUE
UNIT
VM
Power supply voltage range
–0.3 to 12
V
VCC
Power supply voltage range
–0.3 V to 7
V
Digital pin voltage range
–0.5 V to 7
V
Peak motor drive output current
Internally limited
A
TJ
Operating virtual junction temperature range
–40 to 150
ºC
Tstg
Storage temperature range
–60 to 150
ºC
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
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DRV8837
SLVSBA4A – JUNE 2012 – REVISED AUGUST 2012
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THERMAL INFORMATION
DRV8837
THERMAL METRIC (1)
DSG
UNIT
8 PINS
Junction-to-ambient thermal resistance (2)
θJA
(3)
60.9
°C/W
θJCtop
Junction-to-case (top) thermal resistance
71.4
°C/W
θJB
Junction-to-board thermal resistance (4)
32.2
°C/W
ψJT
Junction-to-top characterization parameter (5)
1.6
°C/W
32.8
°C/W
9.8
°C/W
(6)
ψJB
Junction-to-board characterization parameter
θJCbot
Junction-to-case (bottom) thermal resistance (7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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SLVSBA4A – JUNE 2012 – REVISED AUGUST 2012
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Device power supply voltage range
1.8
7
V
VM
Motor power-supply voltage range
1.8
11
V
IOUT
H-bridge output current (1)
0
1.8
A
fPWM
Externally applied PWM frequency
0
250
kHz
VIN
Logic-level input voltage
0
5.5
V
TYP
MAX
UNIT
VM = 5 V, VCC = 3 V, no PWM
40
100
µA
VM = 5 V, VCC = 3 V, 50-kHz PWM
0.8
1.5
mA
(1)
Power dissipation and thermal limits must be observed.
ELECTRICAL CHARACTERISTICS
TA = 25°C, VM = 5 V, VCC = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Power Supplies
IVM
VM operating supply current
IVMQ
VM sleep-mode supply current
IVCC
VCC operating supply current
IVCQ
VCC sleep-mode supply current
VUVLO
VCC undervoltage lockout voltage
VM = 5 V, VCC = 3 V, SLEEP = 0 V
30
95
nA
VM = 5 V, VCC = 3 V, no PWM
300
500
µA
VM = 5 V, VCC = 3 V, 50-kHz PWM
0.7
1.5
mA
VM = 5 V, VCC = 3 V, SLEEP = 0 V
5
25
nA
VCC rising
1.8
VCC falling
1.7
V
Logic-Level Inputs
VIL
Input low voltage
VIH
Input high voltage
0.25 VCC
0.38 VCC
0.46 VCC
VHYS
Input hysteresis
0.08 VCC
IIL
Input low current
VIN = 0 V
IIH
Input high current
VIN = 3.3 V
RPD
Pulldown resistance
V
0.5 VCC
V
V
–5
5
µA
50
µA
100
kΩ
H-Bridge FETs
rds(on)
HS + LS FET on-resistance
VCC = 3 V, VM = 5 V, IO = 800 mA,
TJ = 25°C
IOFF
Off-state leakage current
VOUT = 0 V
280
330
mΩ
±200
nA
Protection Circuits
IOCP
Overcurrent protection trip level
tOCR
OCP retry time
tTSD
Thermal shutdown temperature
1.9
3.5
1
Die temperature
150
A
ms
160
180
ºC
TIMING REQUIREMENTS
TA = 25°C, VM = 5 V, VCC = 3 V, RL = 20 Ω
MIN
MAX
UNIT
1
t1
Output enable time
120
ns
2
t2
Output disable time
120
ns
3
t3
Delay time, INx high to OUTx high
120
ns
4
t4
Delay time, INx low to OUTx low
120
ns
5
t5
Output rise time
50
150
ns
6
t6
Output fall time
50
150
ns
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DRV8837
SLVSBA4A – JUNE 2012 – REVISED AUGUST 2012
www.ti.com
IN1
IN2
t1
t2
t4
Z
OUT1
Z
t3
OUT2
Z
Z
DRV8837
80%
80%
OUTx
20%
20%
t5
t6
T0542-01
Figure 2. Input/Output Timing
FUNCTIONAL DESCRIPTION
Bridge Control
The DRV8837 is controlled using a PWM input interface, also called an IN/IN interface. Each output is controlled
by a corresponding input pin.
The following table shows the logic for the DRV8837:
IN1
IN2
OUT1
OUT2
0
0
Z
Z
Function (DC Motor)
Coast
0
1
L
H
Reverse
1
0
H
L
Forward
1
1
L
L
Brake
Sleep Mode
If the nSLEEP pin is brought to a logic-low state, the DRV8837 enters a low-power sleep mode. In this state, all
unnecessary internal circuitry is powered down.
Power Supplies and Input Pins
The input pins may be driven within their recommended operating conditions with or without the VCC and/or VM
power supplies present. No leakage current path exists to the supply. There is a weak pulldown resistor
(approximately 100 kΩ) to ground on each input pin.
6
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SLVSBA4A – JUNE 2012 – REVISED AUGUST 2012
VCC and VM may be applied and removed in any order. When VCC is removed, the device enters a low-power
state and draws very little current from VM. If the supply voltage is between 1.8 V and 7 V, VCC and VM may be
connected together.
Protection Circuits
The DRV8837 is fully protected against undervoltage, overcurrent, and overtemperature events.
OVERCURRENT PROTECTION (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If
this analog current limit persists for longer than the OCP time, all FETs in the H-bridge are disabled. After
approximately 1 ms, the bridge is re-enabled automatically.
Overcurrent conditions on both high- and low-side devices, that is, a short to ground, supply, or across the
motor winding all result in an overcurrent shutdown.
THERMAL SHUTDOWN (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge are disabled. Once the die temperature
has fallen to a safe level, operation automatically resumes.
UNDERVOLTAGE LOCKOUT (UVLO)
If at any time the voltage on the VCC pin falls below the undervoltage lockout threshold voltage, all circuitry
in the device is disabled and internal logic is reset. Operation resumes when VCC rises above the UVLO
threshold.
THERMAL INFORMATION
Thermal Protection
The DRV8837 has thermal shutdown (TSD) as described in the Protection Circuits section. If the die temperature
exceeds approximately 150°C, the device is disabled until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation,
insufficient heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8837 is dominated by the power dissipated in the output FET resistance, or rDS(on).
Average power dissipation can be roughly estimated by:
PTOT = r DS(on) ´ (IOUT(RMS) )2
(1)
where PTOT is the total power dissipation, rDS(on) is the resistance of the HS plus LS FETs, and IOUT(RMS) is the
rms or dc output current being supplied to the load.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that rDS(on) increases with temperature, so as the device heats, the power dissipation increases.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DRV8837DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
837
DRV8837DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
837
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DRV8837DSGR
WSON
DSG
8
3000
330.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
DRV8837DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8837DSGR
WSON
DSG
8
3000
367.0
367.0
35.0
DRV8837DSGT
WSON
DSG
8
250
210.0
185.0
35.0
Pack Materials-Page 2
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