DRV8805 www.ti.com SLVSAW3C – JULY 2011 – REVISED MARCH 2012 UNIPOLAR STEPPER MOTOR DRIVER IC Check for Samples: DRV8805 FEATURES 1 • 2 • • • 4-Channel Protected Low-Side Driver – Four NMOS FETs With Overcurrent Protection – Integrated Inductive Catch Diodes Indexer/Translator for Unipolar Stepper Motors – Simple Step/Direction Interface – Three Step Modes (2-Phase Full-Step, 1-2Phase Half-Step, 1-Phase Wave Drive) DW Package: 1.5-A (Single Channel On) / 800-mA (Four Channels On) Maximum Drive Current per Channel (at 25°C) PWP Package: 2-A (Single Channel On) / 1-A (Four Channels On) Maximum Drive Current per Channel (at 25°C, With Proper PCB Heatsinking) • • 8.2-V to 60-V Operating Supply Voltage Range Thermally Enhanced Surface Mount Package APPLICATIONS • • Gaming Machines General Unipolar Stepper Motor Drivers DESCRIPTION The DRV8805 provides an integrated solution for driving unipolar stepper motors. It includes four low side drivers with overcurrent protection and provides built-in diodes to clamp turn-off transients generated by the motor windings. Indexer logic to control a unipolar stepper motor using a simple step/direction interface is also integrated. Three stepping modes are supported: 2 phase (full-step), 1-2 phase (half-step), and 1-phase (wave drive). In the SOIC (DW) package, the DRV8805 can supply up to 1.5-A (one channel on) or 800-mA (all channels on) continuous output current per channel, at 25°C. In the HTSSOP (PWP) package, it can supply up to 2-A (one channel on) or 1-A (four channels on) continuous output current per channel, at 25°C with proper PCB heatsinking. Internal shutdown functions are provided for over current protection, short circuit protection, under voltage lockout and overtemperature and faults are indicated by a fault output pin. The DRV8805 is available in a 20-pin thermally-enhanced SOIC package and a 16-pin HTSSOP package (Ecofriendly: RoHS & no Sb/Br). ORDERING INFORMATION (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Reel of 2000 DRV8805DWR DRV8805 Tube of 25 DRV8805DW DRV8805 Reel of 2000 DRV8805PWPR DRV8805 Tube of 90 DRV8805PWP DRV8805 PACKAGE (2) (SOIC) - DW (HTSSOP) - PWP (1) (2) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2012, Texas Instruments Incorporated DRV8805 SLVSAW3C – JULY 2011 – REVISED MARCH 2012 www.ti.com DEVICE INFORMATION Functional Block Diagram 8.2V – 60V Internal Reference Regs UVLO VM nENBL LS Gate Drive OCP & Gate Drive STEP 8.2V – 60V Optional Zener Int. VCC VCLAMP OUT1 Winding 1 DIR SM0 SM1 Control Logic RESET nFAULT 3.3V OCP & Gate Drive OUT2 Winding 2 OCP & Gate Drive OUT3 OCP & Gate Drive OUT4 Winding 3 nHOME Thermal Shut down Winding 4 Unipolar Stepper GND (multiple pins) 2 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8805 DRV8805 www.ti.com SLVSAW3C – JULY 2011 – REVISED MARCH 2012 Table 1. TERMINAL FUNCTIONS PIN (HTSSOP) I/O (1) 5, 6, 7, 14, 15, 16 5, 12, PPAD - Device ground All pins must be connected to GND. 1 1 - Device power supply Connect to motor supply (8.2 V - 60 V). nENBL 10 8 I Enable input Active low enables outputs – internal pulldown RESET 11 9 I Reset input Active-high reset input initializes internal logic – internal pulldown STEP 18 14 I Step input Rising edge advances motor to next step – internal pulldown DIR 17 13 I Direction input Level controls direction of rotation – internal pulldown SM0 13 11 SM1 12 10 I Step mode Sets step mode – see step modes section for details – internal pulldowns nFAULT 20 16 OD Fault Logic low when in fault condition (overtemp, overcurrent) nHOME 19 15 OD Home Logic low when indexer is at home position – weak internal pullup to 3.3 V OUT1 3 3 O Output 1 Connect to load 1 OUT2 4 4 O Output 2 Connect to load 2 OUT3 8 6 O Output 3 Connect to load 3 OUT4 9 7 O Output 4 Connect to load 4 VCLAMP 2 2 - Output clamp voltage Connect to VM supply, or zener diode to VM supply NAME PIN (SOIC) EXTERNAL COMPONENTS OR CONNECTIONS DESCRIPTION POWER AND GROUND GND VM CONTROL STATUS OUTPUT (1) Directions: I = input, O = output, OD = open-drain output DW (WIDE SOIC) PACKAGE (TOP VIEW) VM VCLAMP OUT1 OUT2 GND GND GND OUT3 OUT4 nENBL 1 20 2 19 3 18 4 17 5 6 16 15 7 14 8 13 9 12 10 11 nFAULT nHOME STEP DIR GND GND GND SM0 SM1 RESET PWP (HTSSOP) PACKAGE (TOP SIDE) VM VCLAMP OUT1 OUT2 GND OUT3 OUT4 nENBL 1 16 2 15 3 14 13 4 5 GND 12 6 11 7 10 8 9 nFAULT nHOME STEP DIR GND SM0 SM1 RESET Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8805 3 DRV8805 SLVSAW3C – JULY 2011 – REVISED MARCH 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE UNIT VM Power supply voltage range –0.3 to 65 V VOUTx Output voltage range –0.3 to 65 V VCLAMP Clamp voltage range –0.3 to 65 V nHOME, nFAULT Output current 20 mA Peak clamp diode current 2 A DC or RMS clamp diode current 1 A Digital input pin voltage range –0.5 to 7 V Digital output pin voltage range –0.5 to 7 V Internally limited A nHOME, nFAULT Peak motor drive output current, t < 1 μS Continuous total power dissipation See Dissipation Ratings table TJ Operating virtual junction temperature range –40 to 150 °C Tstg Storage temperature range –60 to 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. THERMAL INFORMATION DRV8805 THERMAL METRIC DRV8805 DW PWP 20 PINS 16 PINS θJA Junction-to-ambient thermal resistance (1) 67.7 39.6 θJCtop Junction-to-case (top) thermal resistance (2) 32.9 24.6 35.4 20.3 8.2 0.7 (3) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (4) ψJB Junction-to-board characterization parameter (5) 34.9 20.1 (6) N/A 2.3 θJCbot (1) (2) (3) (4) (5) (6) 4 Junction-to-case (bottom) thermal resistance UNITS °C/W The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8805 DRV8805 www.ti.com SLVSAW3C – JULY 2011 – REVISED MARCH 2012 RECOMMENDED OPERATING CONDITIONS MIN VM Power supply voltage range VCLAMP Output clamp voltage range (1) IOUT (1) (2) NOM MAX UNIT 8.2 60 V 0 60 V Continuous output current, single channel on, TA = 25°C, SOIC package (2) 1.5 Continuous output current, four channels on, TA = 25°C, SOIC package (2) 0.8 Continuous output current, single channel on, TA = 25°C, HTSSOP package (2) 1.5 Continuous output current, four channels on, TA = 25°C, HTSSOP package (2) 0.8 A VCLAMP is used only to supply the clamp diodes. It is not a power supply input. Power dissipation and thermal limits must be observed. ELECTRICAL CHARACTERISTICS TA = 25°C, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.6 2.1 mA 8.2 V 0.7 V POWER SUPPLIES IVM VM operating supply current VM = 24 V VUVLO VM undervoltage lockout voltage VM rising LOGIC-LEVEL INPUTS (SCHMITT TRIGGER INPUTS WITH HYSTERESIS) VIL Input low voltage 0.6 VIH Input high voltage VHYS Input hysteresis IIL Input low current VIN = 0 IIH Input high current VIN = 3.3 V RPD Pulldown resistance 2 V 0.45 –20 V 20 μA 100 μA 100 kΩ nFAULT OUTPUT (OPEN-DRAIN OUTPUT) VOL Output low voltage IO = 5 mA IOH Output high leakage current VO = 3.3 V 0.5 V 1 μA 0.5 V 1 µA nHOME OUTPUT (OPEN-DRAIN OUTPUT WITH WEAK INTERNAL PULLUP) VOL Output low voltage IO = 5 mA VOH Output high voltage IO = 100 µA, VM = 24 V IOH Output high leakage current VO = 3.3 V 3.3 V LOW-SIDE FETS RDS(ON) FET on resistance IOFF Off-state leakage current VM = 24 V, IO = 700 mA, TJ = 25°C 0.5 VM = 24 V, IO = 700 mA, TJ = 85°C 0.75 0.8 Ω 50 μA –50 50 μA –50 HIGH-SIDE DIODES VF Diode forward voltage VM = 24 V, IO = 700 mA, TJ = 25°C IOFF Off-state leakage current VM = 24 V, TJ = 25°C 1.2 V tR Rise time VM = 24 V, IO = 700 mA, Resistive load 50 300 ns tF Fall time VM = 24 V, IO = 700 mA, Resistive load 50 300 ns 2.3 3.8 A OUTPUTS PROTECTION CIRCUITS IOCP Overcurrent protection trip level tOCP Overcurrent protection deglitch time 3.5 µs tRETRY Overcurrent protection retry time 1.2 ms tTSD Thermal shutdown temperature (1) Die temperature (1) 150 160 180 °C Not production tested. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8805 5 DRV8805 SLVSAW3C – JULY 2011 – REVISED MARCH 2012 www.ti.com TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) (1) NO. (1) PARAMETER DESCRIPTION MIN MAX UNIT 250 kHz 1 fSTEP Step frequency 2 tWH(STEP) Pulse duration, STEP high 1.9 µs 3 tWL(STEP) Pulse duration, STEP low 1.9 µs 4 tSU(STEP) Setup time, DIR, SMx to STEP rising 1 µs 5 tH(STEP) Hold time, DIR, SMx to STEP rising 1 6 tOE(ENABLE) Enable time, nENBL to output low 7 tPD(L-H) Propagation delay time, STEP to OUTx, low to high 8 tPD(H-L) Propagation delay time, STEP to OUTx, high to low - tRESET RESET pulse width µs 50 ns 500 ns 500 20 ns µs Not production tested. nENBL 1 2 3 STEP STEP DIR, SMx OUTx 4 5 7 6 8 Figure 1. DRV8805 Timing Requirements 6 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8805 DRV8805 www.ti.com SLVSAW3C – JULY 2011 – REVISED MARCH 2012 FUNCTIONAL DESCRIPTION Output Drivers The DRV8805 contains four protected low-side drivers. Each output has an integrated clamp diode connected to a common pin, VCLAMP. VCLAMP can be connected to the main power supply voltage, VM. It can also be connected to a zener or TVS diode to VM, allowing the switch voltage to exceed the main supply voltage VM. This connection can be beneficial when driving loads that require very fast current decay, such as unipolar stepper motors. In all cases, the voltage on the outputs must not be allowed to exceed the maximum output voltage specification. Indexer Operation The DRV8805 integrates an indexer to allow motor control with a simple step and direction interface. Logically, the indexer is shown in Figure 2. nENBL OUT1 RESET RESET STEP CLK DIR OUT2 DIR Counter 3.3V Lookup Table (translator) nHOME OUT3 SM0 OUT4 SM1 Figure 2. Indexer Operation Step Modes The SM0 and SM1 pins select the stepping mode of the translator as shown in Table 2. Table 2. Step Modes SM1 SM0 MODE 0 0 2-phase drive (full step) 0 1 1-2 phase drive (half step) 1 0 1-phase excitation (wave drive) 1 1 Reserved In all modes, during a fault condition, the STEP input will be ignored. See the Protection Circuits section below. The sequence of the outputs is shown in Table 3 through Table 5. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8805 7 DRV8805 SLVSAW3C – JULY 2011 – REVISED MARCH 2012 www.ti.com Table 3. 2-Phase Excitation (Full-Step) Function Step RESET DIR STEP nHOME OUT1 OUT2 OUT3 Reset 1 1 X X 0 ON OFF OFF OUT4 ON CW 2 0 1 ↑ 1 ON ON OFF OFF CW 3 0 1 ↑ 1 OFF ON ON OFF CW 4 0 1 ↑ 1 OFF OFF ON ON CW to home 1 0 1 ↑ 0 ON OFF OFF ON CCW 4 0 0 ↑ 1 OFF OFF ON ON CCW 3 0 0 ↑ 1 OFF ON ON OFF OFF CCW 2 0 0 ↑ 1 ON ON OFF CCW to home 1 0 0 ↑ 0 ON OFF OFF ON Hold X 0 X ↑ no chg no chg no chg no chg no chg Table 4. 1-2-Phase Excitation (Half-Step) Function Step RESET DIR STEP nHOME OUT1 OUT2 OUT3 OUT4 Reset 1 1 X X 0 ON OFF OFF OFF CW 2 0 1 ↑ 1 ON ON OFF OFF CW 3 0 1 ↑ 1 OFF ON OFF OFF CW 4 0 1 ↑ 1 OFF ON ON OFF CW 5 0 1 ↑ 1 OFF OFF ON OFF CW 6 0 1 ↑ 1 OFF OFF ON ON CW 7 0 1 ↑ 1 OFF OFF OFF ON CW 8 0 1 ↑ 1 ON OFF OFF ON CW to home 1 0 1 ↑ 0 ON OFF OFF OFF CCW 8 0 0 ↑ 1 ON OFF OFF ON CCW 7 0 0 ↑ 1 OFF OFF OFF ON CCW 6 0 0 ↑ 1 OFF OFF ON ON CCW 5 0 0 ↑ 1 OFF OFF ON OFF CCW 4 0 0 ↑ 1 OFF ON ON OFF CCW 3 0 0 ↑ 1 OFF ON OFF OFF CCW 2 0 0 ↑ 1 ON ON OFF OFF CCW to home 1 0 0 ↑ 0 ON OFF OFF OFF Hold X 0 X ↑ no chg no chg no chg no chg no chg Table 5. 1-Phase Excitation (Wave Drive) 8 Function Step RESET DIR STEP nHOME OUT1 OUT2 OUT3 OUT4 Reset 1 1 X X 0 ON OFF OFF OFF CW 2 0 1 ↑ 1 OFF ON OFF OFF CW 3 0 1 ↑ 1 OFF OFF ON OFF CW 4 0 1 ↑ 1 OFF OFF OFF ON CW to home 1 0 1 ↑ 0 ON OFF OFF OFF CCW 4 0 0 ↑ 1 OFF OFF OFF ON CCW 3 0 0 ↑ 1 OFF OFF ON OFF CCW 2 0 0 ↑ 1 OFF ON OFF OFF CCW to home 1 0 0 ↑ 0 ON OFF OFF OFF Hold X 0 X ↑ no chg no chg no chg no chg no chg Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8805 DRV8805 www.ti.com SLVSAW3C – JULY 2011 – REVISED MARCH 2012 nENBL and RESET Operation The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. nENBL does not affect the operation of the serial interface logic. Note that nENBL has an internal pulldown. The RESET pin, when driven active high, resets the internal logic. The indexer is reset to the home state. All inputs are ignored while RESET is active. Note that RESET has an internal pulldown. An internal power-up reset is also provided, so it is not required to drive RESET at power-up. Protection Circuits The DRV8805 is fully protected against undervoltage, overcurrent and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the tOCP deglitch time (approximately 3.5 µs), the driver will be disabled and the nFAULT pin will be driven low. The driver will remain disabled for the tRETRY retry time (approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either RESET pin is activated or VM is removed and re-applied. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low. The STEP input will be ignored. Once the die temperature has fallen to a safe level, operation will automatically resume. Undervoltage Lockout (UVLO) If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, and internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8805 9 DRV8805 SLVSAW3C – JULY 2011 – REVISED MARCH 2012 www.ti.com THERMAL INFORMATION Thermal Protection The DRV8805 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the DRV8805 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation of each FET when running a static load can be roughly estimated by Equation 1: P = RDS(ON) · (IOUT)2 (1) where P is the power dissipation of one FET, RDS(ON) is the resistance of each FET, and IOUT is equal to the average current drawn by the load. Note that at start-up and fault conditions this current is much higher than normal running current; these peak currents and their duration also need to be taken into consideration. When driving more than one load simultaneously, the power in all active output stages must be summed. The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. Heatsinking The DRV8805DW package uses a standard SOIC outline, but has the center pins internally fused to the die pad in order to more efficiently remove heat from the device. The two center leads on each side of the package should be connected together to as large a copper area on the PCB as is possible to remove heat from the device. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. In general, the more copper area that can be provided, the more power can be dissipated. The DRV8805PWP package uses an HTSSOP package with an exposed PowerPAD™. The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI Application Report SLMA002, "PowerPAD Thermally Enhanced Package" and TI Application Brief SLMA004, "PowerPAD Made Easy", available at www.ti.com. 10 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8805 PACKAGE OPTION ADDENDUM www.ti.com 13-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) DRV8805DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV8805DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV8805PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8805PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DRV8805DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 DRV8805PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8805DWR SOIC DW 20 2000 367.0 367.0 45.0 DRV8805PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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