SCG4000 V3.0 Series Synchronous Clock Generators PLL 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com Bulletin Page Revision Date Issued By SG031 1 of 12 01 30 JULY 02 MBatts Application Features The Connor-Winfield SCG4000 Series provides high precision phase lock loop frequency translation for the telecommunication applications. SCG4000 Series is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, phase locked, synchronization for TDM, PDH, SONET and SDH network equipment. The SCG4000 Series provides a jitter filtered, wander following output signal sychronized to a superior Stratum or peer input reference signal. • 3.3V High Precision PLL • Tri-State Capability • Active Alarms • Guaranteed Free Run ±20ppm • 1 sec. Acquisition Time General Description The SCG4000 Series is a digital phase locked loop generating a LVPECL outputs from an intrinsically low jitter voltage controlled crystal oscillator. The LVPECL outputs may be disabled. The jitter attenuated internal reference, divided down from the output frequency, is also output to a pin. The SCG4000 Series can lock to one of four possible reference frequencies from 8 to 64 kHz, which is selectable using two input select pins. A filtered reference output signal is available at the same frequency. The unit has an acquisition time of about 1 second and it is tolerant of different reference duty cycles. Further features include alarm outputs for Loss-ofReference (LOR) and Loss-of-Lock (LOL). During the LOR alarm, the SCG4000 will also enter a Free Run state, which will guarantee a 20 ppm accurate output. Additionally the Free Run mode may be entered manually. The alarms and reference output may be put into the tri-state high impedance condition for external testing purposes. The maximum package dimensions are 1” x 1.025” x .450” on a 6 layer FR4 board with castellated pins. Parts are assembled using high temperature solder to withstand 63/37 alloy, 180° C surface mount reflow processes. Functional Block Diagram Figure 1 SC G 4 000 S e rie s B loc k D iagram LO L Alarm Output (P in 11) ALARM D ETE C TIO N LO R Alarm O utput (P in 12) Force Free R un (P in 13) Q (P in 18) D IV ID E R R eference Input (P in 4) AN ALO G FILTE R D PFD FRE E R U N CO NTROL VCXO Differential LVP E C L Outputs QN (P in 16) D IV ID E R CM OS Reference Output (P in 7) Select A (P in 5) Select B (P in 6) VC X O Enable (P in 1) Model Comparison Table Table 1 Model Input Ref Freq Max Duty Cycle CMOS Reference Output (Pin #7) LVPECL Oscillator Output (Pin #16 & 18) Notes Basic Model SCG4000 8-64 kHz 40/60 = Input Ref Freq. 125.0 MHz, 155.52 MHz SCG4010 19.44 MHz 40/60 19.44 MHz 125.0 MHz, 155.52 MHz SCG4030 8-64 kHz 45/55 = Input Ref Freq. 125.0 MHz, 155.52 MHz Tighter Duty Cycle *Features which differentiate a model from the base model (SCG4000) are highlighted in boldface, color and in the notes column. Data Sheet #: SG031 Page 2 of 16 Rev: 01 Date: 07/30/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Absolute Maximum Rating Table 2 All SCG4000 Models Symbol Parameter Minimum Nominal Maximum Units 3.6 Volts Notes Vcc Power Supply Voltage 3.0 V1 Input Voltage -0.5 5.5 Volts Ts Storage Temperature -65 150 deg. C Maximum Units Notes 1.0 Operating Specifications Table 3 All SCG4000 Models Symbol Parameter Minimum Nominal Vcc Power Supply Voltage 3.135 3.3 3.465 Volts Icc Power Supply Current - 230 280 mA To Temperature Range 0 - 70 °C Ffr Free Run Accuracy -20 - 20 ppm Fcap Capture/pull-in range -25 - 25 ppm Fbw Jitter Filter Bandwidth - - 10 Hz Tjtol Input Jitter Tolerance - - 31.25 1.0 µs µs Taq Acquisition Time - 1 - s 2.0 Trf Output Rise and Fall Time (20% 80%) 100 225 350 ps 3.0 SCG4000, SCG4030 SCG4010 Features Table 4 All SCG4000 Models Parameter Specifications Notes Alarms LOR, LOL Status on seperate CMOS Outputs TDEV 70 ps (typical) MTIE 800 ps (typical) Static Offset ± 26 ns Maximum 4.0 Dynamic Offset ± 20 ns Maximum 5.0 VCXO Output Logic Type LVPECL Reference Output Logic Type CMOS Package FR4 SM 1.0" x 1.025" x 0.45" CMOS Input And Output Characteristics Table 5 All SCG4000 Models Symbol Parameter Minimum Maximum Units VIH High Level Input Voltage 2 5.5 V VIL Low Level Input Voltage 0 0.8 V TIO I/O to Output Valid 10 nS CO Output Capacitance 10 pF VHO High Level Output Voltage loh = 04mA VIO Low Level Output Voltage lo1 = 8mA TIR Input Reference Signal Pulse Width NOTES: 1.0: 2.0: 3.0: 4.0: 5.0: Nominal 2.4 Notes Vcc Min. 0.4 12.5 Vcc Max. nS Requires external regulation and filter (22uF, 330 pF) From a 20 ppm offset in reference frequency 50Ω load biased to 1.3V Offset between Reference Input and Reference Output @ room temp. Offset change between Reference Input and Reference Output over temperature range from room temperature. Data Sheet #: SG031 © Copyright 2002 The Connor-Winfield Corp. Page 3 of 16 Rev: 01 Date: 07/30/02 All Rights Reserved Specifications subject to change without notice LVPECL Output Characteristics Table 6 All SCG4000 Models Symbol Parameter Minimum Nominal Maximum Units VOH High Level PECL Voltage 2.27 2.34 2.42 V VOL Low Level PECL Voltage 1.49 1.51 CL Output Capacitance TSKEW Differential Output Skew 1.68 V 10 pF 50 Notes ps Output Jitter Specifications Table 7 All SCG4000 Models Jitter BW 10 Hz - 20 MHz SONET Jitter BW 12 kHz - 20 MHz Frequency (MHz) pS (RMS) m UI pS (RMS) m UI 125.00 6(typical) 0.750 (typical) 1 (max), 0.3 (typical) 0.125(max) 155.52 6(typical) 0.933 (typical) 1 (max), 0.4 (typical) 0.156 (max) Output Programming Table 8 Alarm Status All SCG4000 Models Table 9 All SCG4000 Models Tristate Free Run Output LOL Output LOR Output Alarm Output 0 0 Locked to reference selected (default) 0 0 No alarm 1 X Hi-Z Tristate condition 1 0 Loss-of-Lock 0 1 Free run at nominal frequency X 1 Loss-of-Reference Pin Description Table 10 Pin # All SCG4000 Models Connection Description 1 Enable/Disable Enable = 0, Disable = 1 for VCXO Ouputs, Default = 0 (for No Connect) 2 TCK JTAG pin that is used only by Connor-Winfield for programming. Do not connect 3 TDO JTAG pin that is used only by Connor-Winfield for programming. Do not connect 4 Reference In CMOS Reference Frequency Input 5 Select A Reference Frequency Select Pin, Default = 0 (for No Connect) 6 Select B Reference Frequency Select Pin, Default = 0 (for No Connect) 7 Reference Out Filtered Reference Output 8 Ground Power Ground 9 Tri-State Enable CMOS Output Tri-State enable (Hi-Z =1, Default = 0) 10 VCC 3.3V Supply Voltage. 11 Loss of Lock LOL Alarm Output 12 Loss of Reference LOR Alarm Output 13 Free Run Force output frequency to Free Run (FR = 1, Default = 0) 14 TDI JTAG pin that is used only by Connor-Winfield for programming. Do not connect 15 TMS JTAG pin that is used only by Connor-Winfield for programming. Do not connect 16 VCXO Out VCXO differential LVPECL Output 17 Signal Ground VCXO output ground (Shield) 18 VCXO Out VCXO differential LVPECL Output Data Sheet #: SG031 Page 4 of 16 Rev: 01 Date: 07/30/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Maximum Package Dimensions Figure 2 Recommended Footprint and Keepout Area Dimensions Figure 3 Keep Out Area Data Sheet #: SG031 © Copyright 2002 The Connor-Winfield Corp. Page 5 of 16 Rev: 01 Date: 07/30/02 All Rights Reserved Specifications subject to change without notice Tape and Reel Dimensions Figure 4 Solder Profile Figure 5 250 200 Temp (C˚) 150 100 50 0 1 2 3 4 5 6 Time(minutes) Recommended Reflow Profile Peak Temp:217C˚ MaxRiseSlope:1.5 C˚/Sec Time Above150C˚:100Sec Data Sheet #: SG031 Page 6 of 16 Rev: 01 Date: 07/30/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Typical Application Figure 6 Typical Application of Connor-Winfield’s SCG4000 Series Timing Products BITS System Signal Line Cards Input Select Timing Card #1 S A A CW’s SCG 4000 MUX B C B CW’s STM/MSTM module Y MUX Y S Clock out RCV Timing Card #2 S A B C A MUX CW’s STM/MSTM module Y MUX B Y CW’s SCG 4000 Clock out RCV S System Select Typical System Test Set-up Figure 7 GPS or LORAN Timing Source This device supplies system time information. It can be thought of as supplying "absolute time" reference information Sample M T IE D a ta fo r ST M -S 3/M ST M - S3 1.0E-6 Possible Choices Include Stanford Research Model: FS700 Truetime Model XXX T ypical respo nse - 3000 seco nd tes t - Jitter applied (2 UI @ 10 H z) re f date AP R 22 1998 kdh M TIE (s 100.0E-9 10 MHz MTIE 10.0E-9 1244-5.2 Mas k (A ) 1244-5.2 Mas k (B) 1244-5.6 Mas k G R253-5. 4. 4. 3.2 1.0E-9 100 .0E- 3 1.0E+0 10.0E+0 10 0.0E+0 Obs erva tion Tim e (s ) 1.0E+3 10.0 E+3 C o pyright 1998 Co nno r-Winfield a ll righ ts reserv ed Target System Under Test Clock or BITS logic level clock input (TTL, CMOS, etc.) Arbitrary Waveform Generator [Noise Source] Sample Wande r G e ne ra tion ( T D EV) for S T M /M ST M -S 3 1.0E - 6 Typ ical respo nse - 3000 sec ond test - Jitter applied (2 UI @ 10 Hz) ref date A PR 22 1998 kdh 10 0.0E - 9 1 0.0E - 9 TDEV (se c DS-1 Line Card OC-48 Line Card OC-3 Line Card . . . . ... OC-12 Line Card MTIE, TDEV, Wander Transfer, and Wander Generation Plots Line Card Noise Modulation Input 10 MHz External Reference Input Standards Compliance Documents DS1 rate RZ (1.544 MHz), E1 rate RZ or 8 kHz clock RZ with noise modulation Timing Card Arbitrary Waveform Generator Timing Card External Reference Input TDEV G R1244-Fig5.1 1.0E - 9 G R1244-Fig5-3 100 .0E - 12 1 0.0E - 3 100.0E- 3 1.0E +0 10.0E +0 Inte g r atio n Time (s e c) 1.0E + 3 Time-stamped ensemble based on absolute time reference (10MHz input) 10 MHz DS1 rate [1.544 MHz] BITS Bipolar 100.0E +0 C o pyright 1998 Co nno r-W infield a lll rights re served Phase Error data output DS-1, OC-3, OC-12 electrical or optical signals 10 MHz Tektronix SJ300E External Reference Input HP53310A Modulation Analyzer / Time Interval Analyzer Wander Analyzer data (IEEE-488) External Reference Input IEEE-488 Controller Platform for software HP 53305A Phase Analyzer HP E1748A Sync Measurement Tektronix Wander Analyzer TEKTRONIX SJ300E Data Sheet #: SG031 © Copyright 2002 The Connor-Winfield Corp. Page 7 of 16 Rev: 01 Date: 07/30/02 All Rights Reserved Specifications subject to change without notice Alarm Timing Diagram Figure 8 LOR Output Start-up Region 4 LOL Output 2 1 Phase Detector 1 3 External Reference Internal Reference 2 2 2 2 2 2 2 2 2 2 2 2 2 2 LOR Output LOL Output Phase Detector 5 1 1 1 3 1 1 3 External Reference Internal Reference 2 2 2 1 2 3 4 5 Start-up Region 2 2 2 2 19.44 MHz &77.76 MHz Reference Input Units < 1 µsec 2 2 2 2 2 < 31.25 µsec 31.25 µsec > 1 µsec > 31.25 µsec Minimum pulse width = 2 µsec 2 8 kHz Reference Input Units 1 µsec LOR is active when LOL is active 2 125 µsec wide range Minimum pulse width = 62.5 µsec During Start-up, The LOL Alarm will pulse during the first second of operation Data Sheet #: SG031 Page 8 of 16 Rev: 01 Date: 07/30/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice SCG4000 Series Typical MTIE Figure 9 MTIE 1 .0 E -9 1 0 0 .0 E -1 2 1 .0 E -3 1 0 .0 E -3 1 0 0 .0 E -3 1 .0 E + 0 1 0 .0 E + 0 1 0 0 .0 E + 0 O b s e rv a tio n W in d o w (T a u ) SCG4000 Series Typical TDEV Figure 10 TDEV 1 0 0 .0 E -1 2 1 0 .0 E -1 2 1 .0 E -3 1 0 .0 E -3 1 0 0 .0 E -3 1 .0 E +0 1 0 .0 E + 0 Tau Data Sheet #: SG031 © Copyright 2002 The Connor-Winfield Corp. Page 9 of 16 Rev: 01 Date: 07/30/02 All Rights Reserved Specifications subject to change without notice SCG4000 The SCG4000 is Connor-Winfield’s base model for the SCG4000 Series product line. The SCG4000 can lock to one of four input reference frequencies from 8 to 64 kHz which is selectable using two input control pins. SCG4000 Individual Features: • Four selectable References: 8, 16, 32, and 64 kHz. • LVPECL Oscillator Output: 125.0 MHz or 155.52 MHz • CMOS reference output frequency equals input reference frequency. Input Reference Selection Table 11 Input Sel A (Pin #5) SCG4000 Input Sel B (Pin #6) Reference Frequency (Pin #8) 0 0 8 kHz (default) 1 0 16 kHz 0 1 32 kHz 1 1 64 kHz Reference and Output Availability Table 12 Input Reference (Pin #4) 8 kHz 8 kHz 16 kHz 32 kHz 64 kHz SCG4000 LVPECL Oscillator Output (Pin #16 & #18) CMOS Reference Output (Pin #7) 125.0 MHz 155.52 MHz 8 kHz 8 kHz 16 kHz 32 kHz 64 kHz Ordering Information SCG4000-125.0M SCG4000-155.52M Data Sheet #: SG031 Page 10 of 16 Rev: 01 Date: 07/30/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice SCG4010 The SCG4010 only accepts a 19.44 MHz input while providing a phase locked LVPECL output. Also provided is a phase locked 19.44 MHz CMOS reference output. SCG4010 Individual Features: • Input Reference: 19.44 MHz • LVPECL Oscillator Output: 125.0 MHZ or 155.52 MHz • CMOS Reference Output: 19.44 MHz Input Reference Selection Table 13 SCG4010 Input Sel A (Pin #5) Input Sel B (Pin #6) X X Reference Frequency (Pin #8) 19.44 MHz (default) Note: X= Don’t Care Reference and Output Availability Table 14 SCG4010 Input Reference (Pin #4) LVPECL Oscillator Output (Pin #16 & #18) CMOS Reference Output (Pin #7) 19.44 MHz 125.0 MHz, 155.52 MHz 19.44 MHz Ordering Information SCG4010-125.0M SCG4010-155.52M Data Sheet #: SG031 © Copyright 2002 The Connor-Winfield Corp. Page 11 of 16 Rev: 01 Date: 07/30/02 All Rights Reserved Specifications subject to change without notice SCG4030 The SCG 4030 is similar to the SCG4000 except the SCG4030 offers a duty cycle of 45/ 55 for applications that require a tighter duty cycle. The SCG4030 can lock to one of four input reference frequencies from 8 to 64 kHz which is selectable using two input control pins. SCG4030 Individual Features: • Four selectable References: 8, 16, 32, and 64 kHz. • 45/55 Duty cycle • LVPECL Oscillator Output: 125.0MHz or 155.52 MHz • CMOS reference output frequency equals input reference frequency. Input Reference Selection Table 15 Input Sel A (Pin #5) SCG4030 Input Sel B (Pin #6) Reference Frequency (Pin #8) 0 0 8 kHz (default) 1 0 16 kHz 0 1 32 kHz 1 1 64 kHz Reference and Output Availability Table 16 Input Reference (Pin #4) 8 kHz 8 kHz 16 kHz 32 kHz 64 kHz SCG4030 LVPECL Oscillator Output (Pin #16 & #18) CMOS Reference Output (Pin #7) 125.0 MHz 8 kHz 8 kHz 16 kHz 32 kHz 64 kHz 155.52 MHz Ordering Information SCG4030-125.0M SCG4030-155.52M Data Sheet #: SG031 Page 12 of 16 Rev: 01 Date: 07/30/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Data Sheet #: SG031 © Copyright 2002 The Connor-Winfield Corp. Page 13 of 16 Rev: 01 Date: 07/30/02 All Rights Reserved Specifications subject to change without notice Data Sheet #: SG031 Page 14 of 16 Rev: 01 Date: 07/30/02 © Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Data Sheet #: SG031 © Copyright 2002 The Connor-Winfield Corp. Page 15 of 16 Rev: 01 Date: 07/30/02 All Rights Reserved Specifications subject to change without notice 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com Revision Revision Date Note 00 6/14/02 Final Product Release 01 7/30/02 Advanced to V3.0