STC4130 Synchronous Clock for SETS Data Sheet Description Features The STC4130 is a ROHS compatible, integrated, single chip solution for the synchronous clock in SDH and SONET network elements. The device is fully compliant with ITU-T G.812 Type III, G.813, and Telcordia GR1244, and GR253. • For SDH SETS and SSU • For SONET Stratum 3E, 3, 4E, 4 and SMC • Complies with ITU-T G.812 Type III , G.813, Telcordia GR1244, and GR253 • Supports Master/Slave operation with the SyncLinkTM cross-couple data link for master/ slave redundant applications • Accepts 12 individual clock reference inputs • Reference clock inputs are automatically frequency detected • Supports manual or automatic reference selection • T0 and T4 have independent reference lists and priority tables for automatic reference selection • 8 synchronized output clocks • Output/input phase skew is adjustable in slave mode, in 0.1nS steps up to 200nS • Hit-less reference and master/slave switching • Phase rebuild on re-lock and reference switches • Better than 0.1 ppb holdover accuracy • Programmable bandwidth, from 90mHz to 107Hz, for both T0 and T4 DPLL • Supports SPI or parallel bus interface • IEEE 1149.1 JTAG boundary scan • Available in TQ100 ROHS package The STC4130 accepts 12 reference inputs and generates 8 independent synchronized output clocks. Reference input frequencies are automatically detected, and inputs are individually monitored for quality. Active reference selection may be manual or automatic. All reference switches are hitless. Synchronized outputs may be programmed for a wide variety of SONET and SDH frequencies. Two independent clock generators provide the standardized T0 and T4 functions. Each clock generator includes a DPLL (Digital Phase-Locked Loop), which may operate in the Freerun, Synchronized, and Holdover modes. Both clock generators support master/ slave operation for redundant applications. ConnorWinfield’s proprietary SyncLinkTM Cross-couple data link provides master/slave phase information and state data to ensure seamless side switches. A standard SPI serial bus interface or parallel bus provide access to the STC4130’s comprehensive, yet simple to use internal control and status registers. The device operates with an external OCXO or TCXO as its MCLK at either 10 or 20 MHz. Functional Specification T0_Master_Slave T0_Xsync_In Phase Detector LVDS 155.52 MHz Digital Filter 19.44/38.88/77.76 MHz 19.44/38.88/77.76 MHz To Clock Generator T0 Active Ref Selector Reference Clk 12 8 KHz 64 KHz 1.544 MHz 2.048 MHz 19.44 MHz 38.88 MHz 77.76 MHz Activity & Frequency Offset Monitor 44.736 MHz/34.368 MHz T0_Xsync_Out Phase Detector 10MHz/ 20MHz Serial/Parallel Bus Interface 2 KHz 1.544/3.088/6.176/12.352/24.704 MHz 2.048/4.096/8.192/16.384/32.768 MHZ T4 Active Ref Selector T4_Xsync_In T4_Master_Slave OCXO TCXO STC4130 8 KHz Digital Filter Control & Status Registers T4 Clock Generator 1.544 MHz/2.048 MHz T4_Xsync_Out IEE 1194.1 JTAG Figure 1: Functional Block Diagram Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 1 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Table of Contents Description 1 Features 1 STC4130 Pin Diagram (Top View) 3 STC4130 Pin Description 4 Absolute Maximum Ratings 6 Operating Conditions and Electrical Characteristics 6 Register Map 7 General Description 9 Detailed Description 10 Chip Master Clock Input 10 Reference Input Monitoring and Qualification 10 DPLL Active Reference Selection 11 Manual Reference Selection Mode 11 Automatic Reference Selection Mode 11 Digital Phase Locked Loop General Description 11 Free Run 12 Synchronized 12 Holdover 12 DPLL Operating Mode Details 12 Free Run Mode 12 Holdover Mode 13 Output Clocks 14 Master/Slave Operation 15 Processor Interface Descriptions 17 SPI Bus Mode 17 Serial Bus Timing 18 Motorola Bus 19 Intel Bus 21 Multiplex Bus Mode 24 Register Descriptions and Operation 26 General Register Operation 26 Multibyte register reads 26 Multibyte register writes 26 Clearing bits in the Interrupt Status Register 26 Default Register Settings 26 Application Notes 40 Mechanical Dimensions 42 Ordering Information 42 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 2 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet TMS TDI Vdd33 TDO Vss CLK0_N CLK0_P Vdd18 CLK1 Vss CLK2 Vdd33 CLK3 Vss CLK4 Avdd18 Vdd33 Test_Pin Vss TRST TCK Vdd18 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Avss MCLK MCLK_FRQ_SEL STC4130 Pin Diagram (Top View) Avdd18 Ref1 Vss Ref2 Ref3 Vdd33 Test_Pin Ref4 Vdd18 Ref5 Test_Pin Ref6 Vss Ref7 Vss Ref8 Ref9 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 STC4130 (TQ100 Package) See Pg. 42 for Mechanical Dimensions Avss CLK5 Vdd18 CLK6 Vss T0_XSYNC_OUT Vdd33 CLK7 Vss T4_XSYNC_OUT Vdd18 BUS_MODE1 BUS_MODE0 Vss BUS_A6 BUS_A5 Vdd33 BUS_A4 BUS_A3 Vss BUS_A2 BUS_A1 Vdd18 BUS_A0 BUS_RDY BUS_AD7 Vdd33 BUS_CS BUS_ALE Vdd18 BUS_WRB Vss BUS_RDB BUS_AD0 BUS_AD1 Vss BUS_AD2 BUS_AD3 Vdd18 BUS_AD4 BUS_AD5 Vss BUS_AD6 RESET Vdd33 BUS_INTR T4_XSYNC_IN Vdd18 T4_MS Vss 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Vdd18 Ref10 Vss Ref11 Vdd33 Ref12 T0_MS T0_XSYNC_IN 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 Note: Pins labeled “Test Pin” must be grounded. Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 3 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet STC4130 Pin Description Table 1: Pin Description Pin # I/O1 Vdd33 6,22,31, 44,59, 69,80, 89,97 I 3.3V power input Vdd18 9,18,27, 38,47,53, 65,73,84, 92 I 1.8V power input Vss 3,13,15, 20,29,35, 41,49,56, 62,67,71, 78,82,87, 95 Pin Name AVdd18 Description Digital ground 1, 76 1.8V analog power input Avss 75, 100 Analog ground TRST 94 I JTAG reset TCK 93 I JTAG clock TMS 91 I JTAG mode selection TDI 90 I JTAG data input TDO 88 O JTAG data output RESET 30 I Active low to reset the chip MCLK 99 I Master clock input, 10 MHZ or 20 MHz MCLK_FRQ_SEL 98 I Master clock frequency select, 0 = 10 MHz or 1 = 20 MHz BUS_MODE0 63 I Bus mode selection, 00: SPI, 01: Motorola, 10: Intel, 11: Multiplex BUS_MODE1 64 I Bus mode selection, 00: SPI, 01: Motorola, 10: Intel, 11: Multiplex BUS_CS 45 I Parallel bus or SPI Chip select BUS_ALE 46 I Parallel bus address latch or SPI clock input BUS_WRB 48 I Parallel bus write or SPI data input BUS_RDB 50 I Parallel bus read or read/write input BUS_RDY 51 O Parallel bus ready output or SPI data output BUS_A6 61 I Bus Address bit 6 BUS_A5 60 I Bus Address bit 5 BUS_A4 58 I Bus Address bit 4 BUS_A3 57 I Bus Address bit 3 BUS_A2 55 I Bus Address bit 2 BUS_A1 54 I Bus Address bit 1 BUS_A0 52 I Bus Address bit 0 BUS_AD7 43 I/O Parallel bus address/data bit7 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 4 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Table 1: Pin Description Pin # I/O1 BUS_AD6 42 I/O Parallel bus address/data bit6 BUS_AD5 40 I/O Parallel bus address/data bit5 BUS_AD4 39 I/O Parallel bus address/data bit4 BUS_AD3 37 I/O Parallel bus address/data bit3 BUS_AD2 36 I/O Parallel bus address/data bit2 BUS_AD1 34 I/O Parallel bus address/data bit1 BUS_AD0 33 I/O Parallel bus address/data bit0 BUS_INTR 32 O Interrupt REF1 2 I Reference input 1 REF2 4 I Reference input 2 REF3 5 I Reference input 3 REF4 8 I Reference input 4 REF5 10 I Reference input 5 REF6 12 I Reference input 6 REF7 14 I Reference input 7 REF8 16 I Reference input 8 REF9 17 I Reference input 9 REF10 19 I Reference input 10 REF11 21 I Reference input 11 REF12 23 I Reference input 12 T0_M/S 24 I Select master or slave mode for T0, 1: Master, 0: Slave T4_M/S 28 I Select master or slave mode for T4, 1: Master, 0: Slave T0_XSYNC_IN 25 I Cross-couple SyncLinkTM data link input fot T0 for master/slave redundant applications T0_XSYNC_OUT 70 O Cross-couple SyncLinkTM data link output fot T0 for master/slave redundant applications T4_XSYNC_IN 26 I Cross-couple SyncLinkTM data link input fot T4 for master/slave redundant applications T4_XSYNC_OUT 66 O Cross-couple SyncLinkTM data link output fot T4 for master/slave redundant applications CLK0_P 85 O 155.52 MHz LVDS output CLK0_N 86 O 155.52 MHz LVDS output CLK1 83 O 19.44/38.88/77.76 MHz CLK2 81 O 19.44/38.88/77.76 MHz CLK3 79 O 8 KHz frame pulse or 50% duty cycle clock CLK4 77 O 2 KHz frame pulse or 50% duty cycle clock CLK5 74 O 44.736/34.368 MHz CLK6 72 O 1.544/3.088/6.176/12.352/24.704/2.048/4.098/8.192/16.384/32.768 MHZ CLK7 68 O 1.544/2.048 MHz 7,11,96 I Test pin, must be grounded for normal operation Pin Name Test_Pin Description Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 5 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Absolute Maximum Ratings Table 2: Absolute Maximum Ratings Symbol Parameter Min. Max Units Notes Vdd33 Logic power supply voltage, 3.3V -0.5 4.5 volts 1 Vdd18 Logic power supply voltage, 1.8V -0.5 2.5 volts 1 VIN Logic input voltage, rel. to GND -0.5 5.5 volts 1 TSTG Storage Temperature -65 150 C 1 Note 1: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Operating Conditions and Electrical Characteristics Table 3: Recommended Operating Conditions and Electrical Characteristics Symbol Parameter Min. Nominal Max. Units Notes Vdd33 3.3V digital power supply voltage 3.0 3.3 3.6 Volts Vdd18 1.8V digital power supply voltage 1.65 1.8 1.95 Volts VIH (3.3V) High level input voltage 2.0 5.5 Volts 2 VIL (3.3V) Low level input voltage -0.3 0.8 Volts 2 VOH (3.3V) High level output voltage (IOH = -12mA) Vcc - 0.4 Vcc Volts 2 VOL (3.3V) Low level output voltage (IOL =12mA) 0 0.4 Volts 2 CIN Input capacitance TRIP Input reference signal positive pulse width 10 nS TRIN Input reference signal negative pulse width 10 nS TA Operating Ambient Temperature Range 0 Icc (Vcc) 8 pF 70 ¶ 3.3V digital supply current 80 mA Icc (Vcc) 1.8V supply current 240 mA Pd Device power dissipation C 3 W Note 2: LVCMOS 3.3 compatible Note 3: For Industrial Temperature Range (-40° to 85), Use part number STC4130-I Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 6 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Register Map Table 4: Register Map Addr Reg Name Bits Type Description 0x00 Chip_ID 15-0 R Chip ID, 0x4130 0x02 Chip_Rev 7-0 R Chip revision number 0x01 0x03 Chip_Sub_Rev 7-0 R Chip sub-revision 0x01 0x04 T0_T4_MS_Sts 1-0 R 0x05 T0_Slave_Phase_Adj 11-0 R/W Adjust T0 slave phase from 0 ~ 409.5 nS in 0.1 nS steps 0x07 T4_Slave_Phase_Adj 11-0 R/W Adjust T4 slave phase from 0 ~ 409.5 nS in 0.1 nS steps 0x09 Fill_Rate 3-0 R/W Leaky bucket fill rate, 1 ~ 16 mS 0x0a Leak_Rate 3-0 R/W Leaky bucket leak rate, 1/nth of fill rate, n = 1 ~ 16 0x0b Bucket_Size 5-0 R/W Leaky bucket size, 0 ~ 63 Indicates master/slave state 0x0c Assert_Threshold 5-0 R/W Leaky bucket alarm assert threshold, 0 ~ 63 0x0d De_Assert_Threshold 5-0 R/W Leaky bucket alarm de-assert threshold, 0 ~ 63 0x0e Freerun_Cal 10-0 R/W Freerun calibration of the TCXO, - 102.4 ~ + 102.3 ppm 0x10 Disqualification_Range 9-0 R/W Reference disqualification range, 0 ~ 102.3 ppm 0x12 Qualification_Range 9-0 R/W Reference qualification range, 0 ~ 102.3 ppm 0x14 Qualification_Timer 5-0 R/W Reference qualification timer, 0 ~ 63 S 0x15 Ref_Selector 3-0 R/W Determines which reference data is shown in register 0x16 0x16 Ref_Frq_Offset 14-0 R 0x18 Refs_Activity 13-0 R Reference and cross reference activity 0x1a Refs_Qual 11-0 R Reference 1 ~ 12 qualification 0x1c T0_Control_Mode 5-0 R/W OOP -Follow/Don’t Follow, Manual/Auto, Revertive, HO_Usage, PhaseAlignMode 0x1d T0_Bandwidth 4-0 R/W Bandwidth selection 0x1e T0_Auto_Active_Ref 3-0 R 0x1f T0_Manual_Active_Ref 3-0 R/W 0x20 Reserved 31-0 R Reserved 0x24 T0_Long_Term_Accu_History 31-0 R Long term Accumulated History for T0 relative to the TCXO Reference frequency and frequency offset are shown in bits 14-12 and 11-0 Indicates automatically selected reference Selects the active reference in manual mode 0x28 T0_Short_Term_Accu_History 31-0 R 0x2c T0_User_Accu_History 31-0 R/W User Holdover data for T0 relative to the TCXO Short term Accumulated History for T0 relative to the TCXO 0x30 T0_HO_BW_Ramp 7-0 R/W Bits7-4, Long term history accumuation bandwidth: 9.7, 4.9, 2.4, 1.2, 0.61, 0.03 mHz Bits3-2, Short term history accumulation bandwidth: 2.5, 1.24, 0.62, 0.31 mHz Bit21:0, Ramp control: none, 1, 1.5, 2 ppm/S 0x31 T0_Priority_Table 47-0 R/W REF1-12 selection priority for automatic mode, 4 bits/reference 0x37 T0_PLL_Status 7-0 R LTH Avail, LTH Complete, OOP, LOL, LOS, Sync 0x38 T0_Accu_Flush 0-0 W 0: Flush current history, 1: Flush all histories 0x39 T4_Control_Mode 5-0 R/W OOP -Follow/Don’t Follow, Manual/Auto, Revertive, HO_Usage, PhaseAlignMode 0x3a T4_Bandwidth 4-0 R/W 0x3b T4_Auto_Active_Ref 3-0 R Bandwidth selection 0x3c T4_Manual_Active_Ref 3-0 R/W 0x3d Reserved 31-0 R Reserved 0x41 T4_Long_Term_Accu_History 31-0 R Long term Accumulated History for T4 relative to the TCXO Indicates automatically selected reference Selects the active reference in manual mode Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 7 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Table 4: Register Map Addr Bits Type 0x45 T4_Short_Term_Accu_History Reg Name 31-0 R Description 0x49 T4_User_Accu_History 31-0 R/W User Holdover data for T4 relative to the TCXO 0x4d T4_HO_BW_Ramp 7-0 R/W Bits7-4, Long term history accumuation bandwidth: 9.7, 4.9, 2.4, 1.2, 0.61, 0.03 mHz Bits3-2, Short term history accumulation bandwidth: 2.5, 1.24, 0.62, 0.31 mHz Bit21:0, Ramp control: none, 1, 1.5, 2 ppm/S 0x4e T4_Priority_Table 47-0 R/W REF1-12 selection priority for automatic mode, 4 bits/reference 0x54 T4_PLL_Status 7-0 R Short term Accumulated History for T4 relative to the TCXO LTH Avail, LTH Complete, OOP, LOL, LOS, Sync 0x55 T4_Accu_Flush 0-0 W 0x56 CLK0_Sel 0-0 R/W 155.52 MHz clock enable/disable for CLK0 0: Flush current history, 1: Flush all histories 0x57 CLK1_Sel 1-0 R/W 19.44MHz/38.88MHz/77.76MHz or disable select for CLK1 0x58 CLK2_Sel 1-0 R/W 19.44MHz/38.88MHz/77.76MHz or disable select for CLK2 0x59 CLK3_Sel 5-0 R/W 8KHz output 50% duty cycle or pulse width selection for CLK3 0x5a CLK4_Sel 5-0 R/W 2KHz output 50% duty cycle or pulse width selection for CLK4 0x5b CLK5_Sel 1-0 R/W DS3/E3 select for CLK5 0x5c CLK6_Sel 3-0 R/W DS1 x n / E1 x n selector for CLK6 0x5d CLK7_Sel 1-0 R/W Ds1/E1 selector for CLK7 0x5e Intr_Event 9-0 R/W Interrupt event 0x60 Intr_Enable 9-0 R/W Interrupt enable Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 8 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet General Description The STC4130 is an integrated single chip solution for the synchronous clock in SDH and SONET network elements. It’s highly integrated design implements all of the necessary reference selection, monitoring, digital filtering, synthesis, and control functions. An external OCXO or TCXO at either 10 or 20 MHz completes a system level solution (see Functional Block Diagram, Figure 1). The STC4130 includes two independent DPLLs (Digital Phase-Locked Loop) implementing the timing functions of T0 and T4. Each may select one of 12 reference inputs as its active reference. T0 provides 7 of the chip’s 8 clock outputs while T4 provides one clock output. Both T0 and T4 provide a cross reference output for master/slave applications. Reference frequencies are autodected and may each be 8KHz, 64KHz, 1.544MHz, 2.048MHz, 19.44MHz, 38.88MHz, or 77.76MHz. Each reference input is continuously monitored for activity and frequency offset. Activity monitoring is implemented with a leaky bucket accumulator with programmable fill and leak rates. Frequency offset is determined relative to the digitally calibrated external OCXO/TCXO. A reference is designated as “qualified” if it is active and its frequency is within the programmed frequency offset range for a pre-programmed time. Active references may be selected manually or automatically, individually selectable for T0 and T4. In manual mode, the active reference is selected under application control, independant of it’s qualification status. In automatic mode, the active reference is selected according to revertivity status, and each reference’s priority and qualification. Reference priorities are individually programmable. T0 and T4 each have their own priority tables. While a current active reference is qualified, revertivity determines whether a higher priority qualified reference should be selected as the new active reference. If revertivity is enabled, the highest priority qualified reference will always be selected as the active reference. If revertivity is not enabled, a new or returning qualified reference of higher priority will not be selected until the current active reference is disqualified. each include a DPLL, which may operate in the Freerun, Synchronized, and Holdover modes. Both clock generators support master/slave operation for redundant applications. T0 generates ConnorWinfield’s proprietary SyncLinkTM Cross-couple data link, which provides master/slave phase information and state data to ensure seamless side switches. T4 provides an 8KHz cross-couple signal. The slave output clock phase is user adjustable. The T0 and T4 clock generators may each be in freerun, synchronized, or holdover modes. In freerun, the clock outputs are simply determined by the accuracy of the digitally calibrated OCXO/TCXO. In synchronized mode, the chip phase locks to the selected input reference. Phase lock may be selected as arbitrary or zero phase offset between the reference and clock outputs. All reference switches are performed in a hitless manner, and frequency ramp controls ensure smooth output signal transitions. When references are switched, the device will minimize phase transitions in the output clocks. While synchronized, a frequency history is accumulated. In holdover mode, the chip outputs are synthesized according to this or a user supplied history. The Digital Phase Locked Loop which provides the critical filtering and frequency/phase control functions is implemented with Connor-Winfield’s NOVA Kernel - a set of well-proven algorithms and control that meet or exceed all requirements and lead the industry in critical jitter and accuracy performance parameters. Filter bandwidth may be user configured. The device generates 8 independent synchronized output clocks. The first is at 155.52MHZ. The second and third clocks may be programmed at 19.44/38.88/ 77.76MHZ. The fourth and fifth are at 8kHz and 2kHz. The sixth is programmable at 1, 2, 4, 8, or 16 x T1 or E1. The seventh is programmable at either DS3 or E3. The eighth is programmable at either T1 or E1. Control functions are provided either via a standard SPI serial bus interface or 8-bit parallel bus register interfaces. These provide access to the STC4130’s comprehensive, yet simple to use internal control and status registers. Parallel bus operation is supported in the Motorola mode, Intel mode, or Multiplex bus mode. The two independent clock generators, T0 and T4, Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 9 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Detailed Description de-assert threshold is written De_Assert_Threshold (0x0d). Chip Master Clock Input The device operates with an external OCXO or TCXO as its master clock, connected to the MCLK input, pin 99. This may be at either 10 MHz or 20 MHz, MCLK_FRQ_SEL pin 98 = 0 for 10 MHZ, 1 for 20 MHZ. The external TCXO or OCXO may be calibrated, (thus calibrating the freerun output frequency of the chip) by writing an offset to the Freerun_Cal register, (0x0e/0f), from -102.4 to +102.3 ppm, in .1ppm steps, in two’s complement form. (See Register Descriptions section for details regarding register references in this section.) Reference Input Monitoring and Qualification The fill rate is written to the Fill_Rate register, 0x09, and the leak rate is written to register Leak_Rate, 0x0a. The bucket size is written to register Bucket_Size (0x0b). The alarm assert threshold is written to register Assert_Threshold (0x0c), and the register Bucket size must be greater than or equal to the alarm assert threshold value, and the alarm assert threshold value must be greater than the alarm deassert value. Alarms appear in the Refs_Activity register (0x18/ 19). A “1” indicates activity, and a “0” indicates an alarm, no activity. Note that if a reference is active and returns at a different autodetected frequency, it will be become inactive immediately. Fill Rate 1mS ~ 16mS Frequency Detector Ref The STC4130 accepts 12 external reference inputs at 8kHz, 64kHz, 1.544MHz, 2.048MHz, 19.44MHz, 38.88MHz, or 77.76MHz. Input frequencies are detected automatically. The autodetected frequency of any reference may be read by selecting the reference in the Ref_Selector register (0x15) and then reading the frequency from bits 4 - 6 of register Ref_Frq_Offset (0x17). Each input is monitored and qualified for activity and frequency offset. Activity monitoring is accomplished with a leaky bucket accumulation algorithm, as shown in figure 2. The “leaky bucket” accumulator has a fill rate window that may be set from 1 to 16 ms, where any hit of signal abnormality (or multiple hits) during the window increments the bucket count by one. The leak rate is 1/nth of the fill rate, where n may be set from 1 to 16, corresponding to a leak rate window n x the fill rate window size. The leaky bucket accumulator decrements by one for each leak rate window that passes with no signal abnormality. Both windows operate in a consecutive, non-overlapping manner. The bucket accumulator has alarm assert and alarm de-assert thresholds that can each be programmed from 0 to 63. to 8KHz 64KHz 1.544MHz 2.048MHz 19.44MHz 38.88MHz 77.76MHz Pulse Monitor Leaky Bucket Accumulator Alarm Assert Threshold: 0 ~ 63 Bucket size: 0 ~ 63 Alarm De-Assert Threshold: 0 ~ 63 Leak Rate 1/nth fill rate n = 1 ~ 16 Figure 2: Activity Monitor Reference inputs are also monitored and qualified for frequency offset. A PLL qualification range may be programmed up to +/-102.3 ppm by writing to register Qualification_Range (0x12/13), and a disqualification range set up to +/-102.3 ppm, by writing to register Disqualification_Range (0x10/11). The qualification range must be set less than the disqualification range. Additionally, a qualification timer may be programmed from 0 to 63 seconds by writing to register Qualification_Timer (0x14). The PLL pull-in range is the same as the disqualification range. The actual frequency offset (relative to the calibrated OCXO/TCXO) of any reference may be read by selecting the reference in the Ref_Selector register (0x15) and then reading the offset value in bits 7 - 0/ 3 - 0 of register Ref_Frq_Offset (0x16/17). Figure 3 shows the reference qualification scheme. A reference is qualified if it has no activity alarm and is within the qualification range for more than the qualification time. An activity alarm or frequency offset Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 10 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet beyond the disqualification range will disqualify the reference. It may then be re-qualified and the activity alarm is de-asserted, if it is within the qualification range for more than the qualification time. The reference qualification status of each reference may then be read from register Refs_Qual (0x1a/ 1b). Activity Not Good Activity Alarm Asserted Activity Alarm Asserted Activity Alarm De-Asserted Within Offset Qualification Range for more than Qualification Time Activity Good Qualified Out of Disqualification Range Figure 3: Reference Qualification and Disqualification DPLL Active Reference Selection The T0 and T4 clock generators may be individually operated in either manual or automatic input reference selection mode. The mode is selected via the T0(4)_Control_Mode registers. Manual Reference Selection Mode In manual reference selection mode, the user may select the reference. Manual reference selection mode is selected by setting bit 4 of the T0_Control_Mode (0x1c) or T4_Control_Mode (0x39) register (for T0 or T4, respectively) to 0. The reference is selected by writing to bits 0 - 3 of the T0_Manual_Active_Ref (0x1f) and T4_Manual_Active_Ref (0x3c) registers. Automatic Reference Selection Mode In automatic reference selection mode, the device will select one pre-qualified reference as the active reference. Automatic reference selection mode is set by writing bit 4 of the T0_Control_Mode (0x1c) or T4_Control_Mode (0x39) register (for T0 or T4, respectively) to 1. The reference is picked according to its indicated priority in the reference priority table, Registers T0_Priority_Table (0x31~0x36) or T4_Priority_Table (0x4e ~ 0x0x53). Each reference has one entry in the table, which may be set to a value from 0 to 15. ‘0’ masks-out the reference, while 1 to 15 set the priority, where ‘1’ has the highest, and ‘15’ has the lowest priority. The highest priority prequalified reference is chosen as the active reference. The automatically selected reference for each DPLL may be read from registers T0_Auto_Active_Ref (0x1e) and T4_Auto_Active_Ref (0x3b). The pre-qualification scheme is described in the Reference Inputs Monitoring and Qualification section. When a selected active reference is disqualified, the highest priority qualified remaining reference is chosen. If multiple references share the same priority, they are ordered according to the duration of their qualification. The longer the duration, the higher the priority is set. When a reference is disqualified, and subsequently re-qualified as the highest priority candidate, it may or may not be re-selected as the active reference. This is determined by either enabling or disabling “reversion” by writing bit 3 of the T0_Control_Mode (0x1c) or T4_Control_Mode (0x39) register (for T0 or T4, respectively) to “1” for revertive or to “0” for non-revertive operation. If reversion is enabled, a qualified/re-qualified reference will be selected as the new active reference, if it is the highest priority qualified reference at that time. If reversion is disabled, the active reference will not be pre-empted by a higher priority reference until it is disqualified. Digital Phase Locked Loop General Description The STC4130 includes both a T0 and T4 clock generator. Each clock generator has a DPLL, including a phase detector and a digital filter. Each DPLL may select any of the 12 input reference clocks in master mode. In slave mode, they will Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 11 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet select the (T0/T4)_XSYNC_IN cross-couple SyncLinkTM data link(s) as the source of phase information. Freerun In master mode, the T0 and T4 clock generators may each operate in the Freerun, Synchronized, or Holdover modes: No Reference Available and HO not Available 1. Free Run In freerun mode, the CLK(0-7) clock outputs are determined directly from and have the accuracy of the digitally calibrated free running OCXO/TCXO. Reference inputs continue to be monitored for signal presence and frequency offset, but are not used to synchronize the outputs. Active Reference not available or higher priority reference is available in revertive mode Locking Frequency Locked Locked 2. Synchronized The CLK(0-7) clock outputs are phase locked to and track the selected input reference. Upon entering the Locking mode, the device begins an acquisition process that includes reference qualification and frequency slew rate limiting, if needed. Once satisfactory lock is achieved, the “Locked” state is entered, and the “SYNC” bit is set in the T(0/ 4)_DPLL_Status register. Each DPLL’s loop bandwidth may be set independently. Loop bandwidth is selectable from 90mHz to 107Hz, by writing to the T0/4_Bandwidth registers (0x1d/0x3a). Any Reference Available Synchronized Any Reference Available No Reference Available and HO Available Holdover Figure 4: Device phase lock operational mode transition in Automatic Refernce Selection/Master Mode 3. Holdover Upon entering holdover mode, the CLK(0-7) clock outputs are determined from the holdover history established for the last selected reference, or from a user supplied holdover history. Output frequency is determined by a weighted average of the holdover history, and accuracy is determined by the OCXO/ TCXO. Holdover mode may be entered manually or automatically. Automatic entry into holdover mode occurs when operating in the automatic mode, the reference is lost, and no other valid reference exists. The transfer into and out of holdover mode is designed to be smooth and free of hits. DPLL Operating Mode Details Figure 4 shows the phase lock loop states and transitions for operation with automatic reference selection in Master mode. The Freerun mode may be entered automatically, when in the Automatic Reference Selection mode (as shown in figure 4), or manually, by writing to the T(0/ 4)_Manual_Active_Ref registers. The T0 and T4 clock generators may operate in the Freerun, Synchronized, or Holdover modes, including some variants thereof: Freerun Mode The CLK(0-7) clock outputs are synthesized using the free running OCXO/TCXO, calibrated with the freerun frequency offset. The calibration offset may be programmed by the application by writing to the Freerun_Cal register, (0x0e/0f). The calibration offset may be programmed from -102.4 to +102.3 ppm, in .1ppm steps, in two’s complement form. Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 12 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Synchronized Mode The Synchronized mode may be entered automatically, when in the Automatic Reference Selection mode (as shown in figure 4), or manually, by writing to the T(0/4)_Manual_Active_Ref registers (0x1f/ 0x3c), selecting a reference as well as the operating mode. 1.24, 0.62, or 0.31 mHz by writing to the T(0/ 4)_HO_Ramp registers (0x30/ 0x4d). The short-term history is used, in the event of a reference loss in manual reference selection mode, and may be read from the T(0/4)_Short_Term_Accu_History registers (0x28-0x2b/ 0x45-ox48) Each DPLL’s loop bandwidth may be set independently. Loop bandwidth is selectable from 90mHz to 107Hz by writing to the T(0/4)_Bandwidth registers (0x1d/ 0x3a). In manual mode selection, there are two special cases of the Synchronized mode: a) “Zombie” Mode – If the selected active reference signal is lost, the DPLL output is generated according to a short-term history. b) Out of Pull-in Range Mode - If the selected reference exceeds the pull-in range as programmed by the application, the DPLL output may be programmed to stay at the pull-in range limit, or to follow the reference. This is programmed by writing to bit 5 of the T(0/4)_Control_Mode registers (0x1c/ 0x39), specifying whether to follow or not follow a reference that has exceded the pull-in range. In the “Synchronized” mode, bit 0 of the T(0/ 4)_Control_Mode registers (0x1c, 0x39) determines the output clock to input reference phase alignment mode. In “Arbitrary” mode, the clock output phase relationship relative to the reference input phase is according to the initial start-up phase. In “Phase Align” mode, the output clocks are phase aligned to the selected reference. (It should be noted that output-to-reference phase alignment is meaningfull only in those cases where the output frequency and reference are the same or related by a factor of 2n.) When locked on an external reference, two holdover histories are built, for use in Holdover mode: 1) Long-Term History – This is a long-term averaged frequency of the selected external reference, accumulated according to a single-pole low pass filtering algorithm. The 3dB point of the algorithm may be application programmed for 9.7, 4.9, 2.4, 1.2, 0.61, or 0.30 mHz, by writing to the T(0/ 4)_HO_Ramp registers (0x30/ 0x4d). Internally, an express mode is used initially to apply a lower time-constant to speed up the history accumulation process. When a long term history has been built, it is indicated as available by the LHA bit 7 of the T(0/ 4)_DPLL_Status registers (0x37/0x54). Additionally, the application may flush/rebuild this long-term history, by writing to the T(0/ 4)_Accu_Flush registers (0x38, 0x55). The long-term history is used when operating in Holdover Mode, and may be read from the T(0/4)_Long_Term_Accu_History registers (0x24-0x27/ 0x41-0x44). 2) Short-Term History – The short term history may be programmed for a -3dB point of 2.5, Additionally, when a device is operated as a slave in a master/slave pair (by tying the T(0/4)_M/S pin low), the device locks and phase align on the cross-coupled SyncLinkTM data link signal on the (T0/ T4)_XSYNC_IN input. When the device has locked on a reference, the “SYNC” bit 0 is set in the T(0/4)_DPLL_Status register (0x37/ 0x54). If synchronization is lost, the “LOL” bit 2 is set in the T(0/4)_DPLL_Status register. Holdover Mode The application may select either of two sources of frequency offset in Holdover mode, as determined by writing bit 2 of the T(0/4)_Control_Mode registers (0x1c/ 0x39): a) Device Accumulated History Holdover Mode – uses the long-term history accumulated by the device to synthesize the DPLL output This is analogous to the Freerun mode, except that the Holdover algorithms effectively supply the “frequency offset” from the holdover history. b) User Supplied History Mode – The DPLL output is synthesized according to an application supplied frequency offset, as provided in the T(0/ 4)_User_Accu_History registers (0x2c/ 0x49). To facilitate the user’s accumulation of a holdover history, the user may read the short term history of the active reference from the T(0/ 4)_Shor_Term_Accu_History registers (0x28-0x2b/ Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 13 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet 0x45-0x48). On either transition, from Synchronized to Holdover, or back from Holdover to Synchronized, an application programmable maximum slew rate of 1, 1.5, or 2 ppm/second (or no slew rate limit) is applied, as written to the T(0/4)_HO_Ramp registers (0x30/ 0x4d). ble pulse width, and may be disabled by writing to the CLK4_Sel register (0x5a), bits 0 5. Two synthesizers generate additional clocks from the T0 clock generator: • Output Clocks The clock output section includes 4 clock generations, an APLL, and four dividers, and generates nine synchronized clocks, as shown in figure 5. T0 DPLL Clk Generation Clk0 APLL Divider Divider 155.52 MHz Clk1 19.44 / 38.88 / 77.76 MHz Clk2 • One synthesizer is driven by the T4 clock generator: 19.44 / 38.88 / 77.76 MHz • Clk3 8 KHz Divider Divider Clk Generation Clk Generation T4 DPLL Clk4 Clk5 Clk6 Clk7 Clk Generation 2 KHz DS3, E3 nxDS1, nxE1 n = 1,2,4,8,16 T1, E1 Figure 5: Output Clocks The first synthesizer drives an analog PLL and generates five output clocks. It is driven from the T0 DPLL: • • • • • CLK5: Either DS3 or E3 rate, or “disabled”, programmed by writing to the CLK5_Sel register (0x5b), bits 0 - 1. CLK6: Programmable at nxDS1 or nxE1 where n=1,2,4,8,16, or may be disabled, by writing to the CLK6_Sel register (0x5c), bits 0 - 3. CLK7: Either DS1 or E1 rate, or “disabled”, programmed by writing to the CLK7_Sel register (0x5d), bits 0 - 1. When a clock output is disabled, the pin is tri-stated. In addition, the T0_Xsync_OUT and T4_Xsync_OUT outputs provide phase information and state data for master/slave operation of the T0 and T4 clock generators. Note that the CLK1, 2, 5 and 6 are phase aligned with the CLK3 (8KHz) as shown in Figure 7. CLk3 is phase aligned with CLK4 (2KHz). CLK0: 155.52 MHz (LVPECL), enabled/disabled by writing the CLK0_Sel register (0x56), bit 0. CLK1: Programmable at 19.44MHz, 38.88MHz, 77.76 MHz, and “disabled”, by writing to the CLK1_Sel register (0x57), bits 0 - 1. CLK2: Programmable at 19.44MHz, 38.88MHz, 77.76 MHz, and “disabled”, by writing to the CLK2_Sel register (0x58), bits 0 - 1. CLK3: 8kHz, 50% duty cycle or programmable pulse width, and may be disabled by writing to the CLK3_Sel register (0x59), bits 0 5. CLK4: 2kHz, 50% duty cycle or programmaData Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 14 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Master/Slave Configuration Pairs of STC4130 devices may be operated in a master/slave configuration for added reliability, as shown in Figure 6. T0 PLL T0_XSYNC_OUT T0_MS T0 PLL T0_MS T0_XSYNC_IN T4_XSYNC_OUT T4_MS T4 PLL T4 PLL T4_MS T4_XSYNC_IN STC4130 STC4130 Figure 6: Master/Slave Configuration Devices are configured for master/slave operation by cross-connecting their respective T(0/4)_Xsync_Out and/or T(0/4)_Xsync_In pins. The T(0/4)_MS pins determine the master or slave mode for each clock generator. 1=Master, 0=Slave. Thus, master/slave state is always manually controlled by the application. The master synchronizes to the selected input reference, while the slave synchronizes and phase-aligns according to data received over the T(0/4)_Xsync_Out / T(0/ 4)_Xsync_In data link from the unit in master mode. may be phase shifted from 0 to +409.5nS, in 100pS increments according to the contents of the T(0/ 4)_Slave_Phase_Adj (0x05/06, 0x07/08) registers to compensate for the path length of the T(0/ 4)_Xsync_Out to T(0/4)_Xsync_In connections. This offset may therefore be programmed to exactly compensate for the actual path length delay associated with the particular application's cross-couple traces. Thus, master/slave switches with the STC4130 devices may be accomplished with nearzero phase hits. The first time a clock generator becomes a slave, such as immediately after power-up, its output clock phase starts out arbitrary, and will quickly phasealign to the master unit. The phase skew will be eliminated (or converged to the programmed phase offset) step by step. The whole pull-in-and-lock process will complete in about 16 seconds. There is no frequency slew protection in slave mode. In slave mode, the unit's mission is to lock to and follow the master. 2KHz Master T0 Clock Generator STC4130 8KHz 38.88MHz 77.76MHz T1/E1 T3/E3 The T0 and T4 PLL’s may be operated completely independent of each other – either or both may be cross-connected as master/slave pairs across two STC4130 devices, and master/slave states may be set the same or opposite within a given device. Programmable skew 0 to 409.5 nS 2KHz Slave T0 Clock Generator STC4130 In slave mode, the operational mode is “Synchronized” and the T(0/4)_Xsync_Out data links provide phase and state information. Bits 0 and 1 of the T0_T4_MS_Sts register reflect the states of the T(0/4)_MS pins. 8KHz 38.88MHz 77.76MHz T1/E1 T3/E3 Figure 7: T0 CLK1-6 Phase Alignment and Master/ Slave skew Control Note the phase alignment of all clock outputs from the T0 clock generator with the 2KHz output. Master/Slave Operation Perfect phase alignment of the Clk(x) output clocks (between the clock generators in two devices) would require no delay on the cross-couple data link connection. To accommodate path length delays, the STC4130 provides a programmable phase skew feature. See figures 7 and 8. The slave’s Clk(x) outputs Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 15 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Master T4 Clock Generator T1/E1 STC4130 Programmable skew 0 to 409.5 nS Slave T4 Clock Generator T1/E1 STC4130 Figure 8: T4 CLK7 Master/Slave Skew Control Once a pair of clock generators has been operating in aligned master/slave mode, and a master/slave switch occurs, the clock generator that becomes master will maintain its output clock phase and frequency while a phase rebuild (to the current output clock phase) is performed on its selected reference input. Therefore, as master mode operation commences, there will be no phase or frequency hits on the clock output. Assuming the phase offset is programmed for the actual propagation delay of this cross-couple path, there will again be no phase hits on the output clock of the clock generator that has transitioned from master to slave. The data link will also provide state information that will allow the new master to lock on the same reference as the old master. Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 16 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Processor Interface Descriptions The STC4130 supports four common microprocessor control interfaces: SPI, Motorola, Intel, and multiplex parallel. The control interface mode is selected with the Bus_Mode(0/1) pins: Bus_Mode1, Bus_Mode0 Bus Mode 00 SPI 01 Motorola 10 Intel 11 Multiplex parallel The following sections describe each bus mode’s interface timing: SPI Bus Mode The SPI interface bus mode uses the BUS_CS, BUS_ALE, BUS_WRB, and BUS_RDY pins, corresponding to CS, SCLK, SDI, and SDO respectively, with timing as shown in figures 9 and 10: Serial Bus Timing CS tCSHLD tCS 1 2 3 4 5 6 7 8 A1 A0 0 9 10 11 12 13 14 15 tCSMIN tCSTRI 16 SCLK tDs tDh A6 SDI A5 tCH A4 tCL A3 A2 LSB MSB tDHLD tDRDY SDO D7 D6 D5 D4 D3 D2 D1 MSB D0 LSB Figure 9: Serial Bus Timing, Read access CS tCSMIN tCSHLD tCS 1 2 3 4 5 6 7 A1 A0 8 9 10 11 12 13 14 15 1 D7 D6 D5 D4 D3 D2 D1 LSB MSB 16 SCLK tDs SDI tDh A6 MSB A5 tCH A4 tCL A3 A2 D0 LSB Figure 10: Serial Bus Timing, Write access Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 17 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Table 5: Serial Bus Timing Symbol Description Min Max Unit tCS CS low to SCLK high 10 nS tCH SCLK high time 25 nS tCL SCLK low time 25 nS tDs Data setup time 10 nS tDh Data hold time 10 nS tDRDY Data ready 7 tDHLD Data hold 5 nS tCSHLD Chip select hold 30 nS tCSTRI Chip select to data tri-state tCSMIN Minimum delay between successive accesses 5 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. 50 Page 18 of 44 nS nS nS Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Motorola Bus In Motorola mode, the device will interface to 680xx type processors. The BUS_CS, BUS_RDB, BUS_A(6-0), BUS_AD(7-0), and BUS_RDY pins are used, corresponding to CS, R/W, A, AD, and RDY, respectively. Timing is as follows: Motorola Bus Timing tCSd tCS CS tRWs tRWh R/W tAs tAh Address A tDd1 tDd2 AD Data tRDY tRDYd1 tRDYh tRDYd2 RDY Figure 11: Motorola Bus Read Timing Table 6: Motorola Bus Read Timing Symbol Description Min Max Unit tCS CS low time 50 nS tCSd CS minimum high time between reads/writes 50 nS tRWs Read/write setup time 0 nS tRWh Read/write hold time 0 nS tAs Address setup 10 nS tAh Address hold 0 nS tDd1 Data valid delay from CS low 50 nS tDd2 Data high-z delay from CS low 10 nS tRDY1 CS low to RDY high delay 13 nS tRDY RDY high time 37 50 nS tRDYh CS hold after RDY low 0 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 19 of 44 nS Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Symbol Description tRDY2 Min RDY high-z delay after CS high Max Unit 9 nS tCSd tCS CS tRWs tRWh R/W tAs tAh Address A tDs AD tDh Data tRDY tRDYd1 tRDYh tRDYd2 RDY Figure 12: Motorola Bus Write timing Table 7: Motorola Bus Read Timing Symbol Description Min Max Unit tCS CS low time 50 nS tCSd CS minimum high time between writes/reads 50 nS tRWs Read/write setup time 0 nS tRWh Read/write hold time 0 nS tAs Address setup 10 nS tAh Address hold 0 nS tDs Data setup time before CS high 10 nS tDh Data hold time after CS high 10 nS tRDYd1 CS low to RDY high delay 13 nS tRDY RDY high time 37 nS tRDYh CS hold after RDY low 0 nS Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 20 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Symbol Description tRDYd2 Min RDY high-z delay after CS high Max Unit 7 nS Intel Bus In Intel mode, the device will interface to 80x86 type processors. The BUS_CS, BUS_WRB, BUS_RDB, BUS_A(6-0), BUS_AD(7-0), and BUS_RDY pins are used, corresponding to CS, WRB, RDB, A, AD, and RDY, respectively. Timing is as follows: CS WRB tRDB1 tRDBs tRDBh tRDB RDB tAs tAh Address A tDd1 tDd2 AD Data tRDYd2 tRDYd1 tRDY tRDYd3 tRDYh RDY Figure 13: Intel Bus Read Timing Table 8: Intel Bus Read Timing Symbol Description Min Max Unit tRDBs Read setup time 0 nS tRDB Read low time 40 nS tRDBh Read hold time 0 nS tRDB1 Time between consecutive reads 50 nS tAs Address setup 10 nS tAh Address hold 0 nS tDd1 Data valid delay from RDB high 50 nS tDd2 Data high-z delay from RDB high 10 nS CS low to RDY high delay 13 nS tRDYd1 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 21 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Symbol tRDYd2 Description Min RDB low to RDY low Max Unit 40 nS tRDY RDY low time 50 nS tRDYh RDB hold after RDY high 0 nS tRDY3 RDY high-z delay after CS high 11 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 22 of 44 nS Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet CS tWRB1 tWRBs tWRBh tWRB WRB RDB tAh tAs Address A tDs AD tDh Data tRDYd2 tRDYd1 tRDY tRDYd3 tRDYh RDY Figure 14: Intel Write Read Timing Table 9: Intel Bus Write Timing Symbol Description Min Max Unit tWRBs Write setup time 0 nS tWRB Write low time 40 nS tWRBh Write hold time 0 nS tWRB1 Time between consecutive writes 50 nS tAs Address setup 10 nS tAh Address hold 0 nS tDs Data setup time before CS high 10 nS tDh Data hold time after CS high 10 nS tRDYd1 CS low to RDY high delay 13 nS tRDYd2 RDB low to RDY low 40 nS tRDY RDY low time 50 nS tRDYh RDB hold after RDY high 0 nS tRDY3 RDY high-z delay after CS high 10 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 23 of 44 nS Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Multiplex Bus Mode In multiplex bus mode, the device can interface with microprocessors which share the address and data on the same bus signals. The BUS_ALE, BUS_CS, BUS_WRB, BUS_RDB, BUS_AD(7-0), and BUS_RDY pins are used, corresponding to ALE, CS, WRB, RDB, AD, and RDY, respectively. Multiplex Bus Timing tALE tALEd ALE tADs tADh tCSs CS WRB tCSd tRDB tCSh RDB tDh2 tDd1 AD Data Address tRDYd2 tRDYd1 tRDY tRDYh tRDYd3 RDY Figure 15: Multiplex Bus Read Timing Table 10: Multiplex Bus Read Timing Symbol Description Min Max Unit tALE ALE high time tALEd ALE falling edge to RDB low 0 nS tADs Address setup time 10 nS tADh Address hold time 10 nS 10 nS tCSs Read setup time 0 nS tRDB Read time 40 nS tCSh CS hold time 0 nS tCSd CS delay for multiple read/writes 50 tDd1 Data valid delay from RDB low 50 nS tDh2 Data high-z from RDB high 10 nS nS tRDYd1 CS low to RDY active 13 nS tRDYd2 RDB low to RDY low 40 nS tRDY RDY low time 50 nS tRDYh Read hold after RDY high 0 nS Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 24 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Symbol tRDYd3 tALE Description Min RDY high-z delay after CS high Max Unit 10 nS tALEd ALE tADs tADh tCSs CS tCSd tWRB tCSh WRB RDB tDh tDs AD Address Data tRDYd2 tRDYd1 tRDY tWRBh tRDYd3 RDY Figure 16: Multiplex Bus Write Timing Table 11: Multiplex Bus Write Timing Symbol Description Min Max Unit tALE ALE high time 10 nS tALEd ALE falling edge to RDB low 0 nS tADs Address setup time 10 nS tADh Address hold time 10 nS tCSs Write CS setup time 0 nS tWRB Write time 40 nS tCSh CS hold time 10 nS tCSd CS delay for multiple write/reads 50 nS tDs Data setup time 10 nS tDh Data hold time 10 nS tRDYd1 CS low to RDY active 13 nS tRDYd2 WRB low to RDY low 40 nS tRDY RDY low time 50 nS tWRBh WRB hold after RDY high 0 nS tRDYd3 RDY high-z delay after CS high 9 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 25 of 44 nS Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Register Descriptions and Operation General Register Operation The STC4130 device has 1, 2, and 4 byte registers. One byte registers are read and written directly. Two and four byte registers must be read and written in a specific manner and order, as follows: Multibyte register reads A multibyte register read must commence with a read of the least significant byte first. This triggers a transfer of the remaining byte(s) to a holding resgister, ensuring that the remaining data will not change with the continuing operation of the device. The remaining byte(s) may then be read in any order, and with no timing restrictions. Multibyte register writes A multibyte register write must commence with a write to the least significant byte first. Subsequent writes to the remaining byte(s)must be performed in ascending byte order, but with no timing restrictions. Multibyte register writes are temporarily stored in a holding register, and are transferred to the target register when the most significant byte is written. Clearing bits in the Interrupt Status Register Interrupt event register (Intr_Event, 0x5e~0x5f) bits are cleared by writing a “1” to the bit position to be cleared. Interrupt bit positions to be left as is are written with a “0”. Default Register Settings Chip_ID, 0x00 (R) Address Bit7 Bit6 Bit5 Bit4 0x00 0x30 0x01 0x41 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Chip_Rev, 0x02 (R) Address Bit7 Bit6 Bit5 Bit4 0x02 0x01 Chip_Sub_Rev, 0x03 (R) Address Bit7 Bit6 Bit5 Bit4 0x03 0x01 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 26 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet T0_T4_MS_Sts, 0x04 (R/W) Address Bit7 Bit6 Bit5 0x04 Bit4 Bit3 Bit2 Not used Bit1 Bit0 T4 M/S T0 M/S Bit1 Bit0 Reflects the states of the T0/T4_Master_Slave select pins. 1 = Master, 0 = slave T0_Slave_Phase_Adj, 0x05 (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 0x05 Adjust T0 slave phase from 0 ~ 409.5 nS in 0.1 nS steps, lower 8 bits 0x06 Not used Adjust T0 slave phase from 0 ~ 409.5 nS in 0.1 nS steps, upper 4 bits The T0 slave phase may be adjusted 0 to 409.5 nS relative to the cross couple input with 0.1 nS resolution. This is a 12 bit register, split across address 0x05 and 0x06. Default value: 0. T4_Slave_Phase_Adj, 0x07 (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 0x07 Adjust T4 slave phase from 0 ~ 409.5 nS in 0.1 nS steps, lower 8 bits 0x08 Not used Bit0 Adjust T4 slave phase from 0 ~ 409.5 nS in 0.1 nS steps, upper 4 bits The T4 slave phase may be adjusted 0 to 409.5 nS relative to the cross couple input with 0.1 nS resolution. This is a 12 bit register, split across address 0x07 and 0x08. Default value: 0. Fill_Rate, 0x09 (R/W) Address Bit7 0x09 Bit6 Bit5 Bit4 Bit3 Not used Bit2 Bit1 Bit0 Leaky bucket fill rate window, 0 ~ 15, Default = 0 Sets the fill rate window size for the reference activity monitor. The value can be set from 0 to 15, corresponding to 1mS to 16mS. Default value: 1. Leak_Rate, 0x0a (R/W) Address 0x0a Bit7 Bit6 Bit5 Bit4 Bit3 Not used Bit2 Bit1 Bit0 Leak rate, 1/nth of fill rate, 0 ~ 15 Sets the leak rate for the reference activity monitor to 1/nth of the fill rate, corresponding to n x the fill rate window size. Valid values from 0 to 15, corresponding to n = 1 to 16. For example, if the fill rate is set to 4mS and the leak rate is set to 3 (n = 4), the leak rate window size will be 16mS. Default value: 3. Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 27 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Bucket_Size, 0x0b (R/W) Address Bit7 0x0b Bit6 Bit5 Bit4 Bit3 Not used Bit2 Bit1 Bit0 Leaky bucket size, 0 ~ 63 Sets the leaky bucket size for the reference activity monitor. Bucket size must be greater than or equal to the alarm assert value. Invalid values will not be written to the register. Default value: 20. Assert_Threshold, 0x0c (R/W) Address Bit7 0x0c Bit6 Bit5 Not used Bit4 Bit3 Bit2 Bit1 Bit0 Leaky bucket alarm assert threshold, 0 ~ 63 Sets the leaky bucket alarm assert threshold for the reference activity monitor. The alarm assert threshold value must be greater than the de-assert threshold value and less than or equal to the bucket size value. Invalid values will not be written to the register. Default value: 15. De_Assert_Threshold, 0x0d (R/W) Address Bit7 0x0d Bit6 Bit5 Not used Bit4 Bit3 Bit2 Bit1 Bit0 Leaky bucket alarm de-assert threshold, 0 ~ 63 Sets the leaky bucket alarm de-assert threshold for the reference activity monitor. The de-assert threshold value must be less than the assert threshold value. Invalid values will not be written to the register. Default value: 10. Freerun_Cal, 0x0e (R/.W) Address Bit7 Bit6 Bit5 0x0e Bit4 Bit3 Bit2 Bit1 Bit0 Lower 8 bits 0x0f Not used Upper 3 bits Freerun TCXO/OCXO calibration, from -102.4 to +102.3 ppm, in .1ppm steps, two’s complement. Default value: 0. Disqualification_Range, 0x10 (R/W) Address Bit7 Bit6 Bit5 0x10 0x11 Bit4 Bit3 Bit2 Bit1 Bit0 Lower 8 bits Not used Upper 3 bits Reference disqualification range, from 0 to +102.3 ppm, in 0.1 ppm steps. This also sets the pull-in range, beyond which, in manual mode, a reference will either not be synchronized to or no longer will be followed (depending on the state of the OOP bits in the T0/4_Control_Mode registers). Default value: 110. Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 28 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Qualification_Range, 0x12 (R/W) Address Bit7 Bit6 Bit5 Bit4 0x12 Bit3 Bit2 Bit1 Bit0 Lower 8 bits 0x13 Not used Upper 3 bits Reference qualification range, from 0 to +102.3 ppm, in 0.1 ppm steps. Default value: 100. Qualification_Timer, 0x14 (R/W) Address Bit7 Bit6 Bit5 Bit4 0x14 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 0 ~ 63 S Reference qualification timer, from 0 to 255 S. Default value: 10. Ref_Selector, 0x15 (R/W) Address Bit7 Bit6 0x15 Bit5 Bit4 Not used 1 ~ 12 (0x1 ~ 0xc) Determines which reference data is displayed in register 0x16 and 0x17. Valid values from 1 to 12. Default value: 1. Ref_Frq_Offset, 0x16 (R) Address Bit7 Bit6 Bit5 Bit4 0x16 0x17 Bit3 Bit2 Bit1 Bit0 Lower 8 bits of frequency offset Not used Reference frequency Upper 4 bits of frequency offset Displays the frequency offset and reference frequency for the reference selected by the Ref_Selector (0x15) register. Frequency offset is from -204.8 to +204.7 ppm in 0.1 ppm steps, two’s complement. The reference frequency is determined as follows: 0x13, bits 6 ~ 4 Frequency 000 No signal 001 8 KHz 010 64 KHz 011 1.544 MHz 100 2.048 MHz 101 19.44 MHz 110 38.88 MHz 111 77.76 MHz Refs_Activity, 0x18 (R) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x18 Ref 8 Ref 7 Ref 6 Ref 5 Ref 4 Ref 3 Ref 2 Ref 1 Ref 12 Ref 11 Ref 10 Ref 9 0x19 Not used T4_Xsync_In T0_Xsync_In Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 29 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Reference activity indicator, 0 = no activity, 1 = activity. Refs_Qual, 0x1a (R) Address Bit7 Bit6 0x1a Ref 8 Ref 7 0x1b Bit5 Bit4 Bit3 Ref 6 Ref 5 Not used Bit2 Bit1 Bit0 Ref 4 Ref 3 Ref 2 Ref 1 Ref 12 Ref 11 Ref 10 Ref 9 Bit1 Bit0 Reference qualification indicator, 0 = not qualified, 1 = qualified. T0_Control_Mode, 0x1c (R/W) Address Bit7 0x1c Bit6 Not used Bit5 Bit4 Bit3 Bit2 OOP: Out of Pull-in range: 0=Follow 1=Don’t follow Manual/ Auto 0=Manual 1=Auto Revertive 0=Nonrevertive 1=Revertive Accu_Usage 0=LTH 1=User Phase Align Mode 0=Arbitrary 1=Align Mode control bits for T0. Bit 0: 0 = Arbitrary (use initial phase), 1 = Phase align Bit 2, Accu_Usage: 0 = Device calculated long term history (LTH) is used; 1 = User supplied history is used. Bit 5, OOP: In manual mode, when the selected active reference is out of the pull-in range, as specified in register Disqualification_Range, 0x10, OOP will determine if the reference is to be followed, 0 = Don’t follow, 1 = Follow. Default value: 0. T0_Bandwidth, 0x1d (R/W) Address Bit7 0x1d Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Not used Sets the T0 bandwidth: 0x1d, bits 4 ~ 0 Bandwidth, Hz 0 107 1 50 2 24 3 12 4 5.9 5 2.9 6 1.5 7 .73 8 0.37 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 30 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet 0x1d, bits 4 ~ 0 Default value: 6. Bandwidth, Hz 9 0.18 10 0.09 31 ~ 11 Reserved T0_Auto_Active_Ref, 0x1e (R) Address Bit7 Bit6 0x1e Bit5 Bit4 Bit3 Not used Bit2 Bit1 Bit0 Values from 0 - 12 Indicates the automatically selected active reference for T0, when the device is a “master”. When the device is a “slave”, the mate’s active reference is indicated. T0_Manual_Active_Ref, 0x1f (R/W) Address Bit7 Bit6 0x1f Bit5 Bit4 Bit3 Not used Bit2 Bit1 Bit0 Values from 0 - 15 Selects the active reference and the phase align mode for T0 in manual reference select mode. Bit 3 ~ Bit 0 0000 Phase Align Mode/Ref selection Freerun 0001 ~ 1100 Ref 1 ~ Ref 12 1101 ~ 1111 Holdover Default value: 0. T0_Long_Term_Accu_History, 0x24 (R) Address Bit7 Bit6 Bit5 0x24 Bit4 Bit3 Bit2 Bit1 Bit0 Bit1 Bit0 Bits 0 - 7 of 32 bit Long Term Holdover History 0x25 Bits 8 - 15 of 32 bit Long Term Holdover History 0x26 Bits 16 - 23 of 32 bit Long Term Holdover History 0x27 Bits 24 - 31 of 32 bit Long Term Holdover History Long term accumulated history for T0 relative to the TCXO. Resolution is 0.745x10-3ppb. T0_Short_Term_Accu_History, 0x28 (R) Address 0x28 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bits 0 - 7 of 32 bit Short Term Holdover History 0x29 Bits 8 - 15 of 32 bit Short Term Holdover History 0x2a Bits 16 - 23 of 32 bit Short Term Holdover History 0x2b Bits 24 - 31 of 32 bit Short Term Holdover History Short term accumulated history for T0 relative to the TCXO. Resolution is 0.745x103 ppb. Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 31 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet T0_User_Accu_History, 0x2c (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 0x2c Bits 0 - 7 of 32 bit User Holdover History 0x2d Bits 8 - 15 of 32 bit User Term Holdover History 0x2e Bits 16 - 23 of 32 bit User Term Holdover History 0x2f Bits 24 - 31 of 32 bit User Term Holdover History Bit1 Bit0 Bit1 Bit0 User accumulated history for T0 relative to the TCXO. Resolution is 0.745x10-3 ppb. Default value: 0. T0_HO_Ramp, 0x30 (R/W) Address Bit7 0x30 Not used Bit6 Bit5 Bit4 Bit3 Long term History Bandwidth Bit2 Short term History abdnwidth Ramp control Holdover bandwidth and ramp controls for T0: 0x30, bits 6 ~ 4 Long term History Bandwidth, mHz 000 9.7 mHz 001 4.9 mHz 010 2.4 mHz 011 1.2 mHz 100 0.61 mHz 101 0.30 mHz 0x30, bits 3 ~ 2 Short term History Bandwidth, mHz 00 2.5 mHz 01 1.24 mHz 10 0.62 mHz 11 0.31 mHz 0x30, bits 1 ~ 0 Ramp control, ppm/sec 00 No Control 01 1 10 1.5 11 2 Default value: 0x26 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 32 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet T0_Priority_Table, 0x31 (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 0x31 Ref 2 Priority Ref 1 Priority 0x32 Ref 4 Priority Ref 3 Priority 0x33 Ref 6 Priority Ref 5 Priority 0x34 Ref 8 Priority Ref 7 Priority 0x35 Ref 10 Priority Ref 9 Priority 0x36 Ref 12 Priority Ref 11 Priority Bit0 Reference priority for automatic reference selection mode. Lower values have higher priority: 0x31 - 0x36, 4 bits Reference Priority 0000 Disable reference 0001 ~ 1111 1 ~ 15 Default value: 0. T0_PLL_Status, 0x37 (R) Address Bit7 Bit6 0x37 LHA 1=Available 0=Not available LHC 1=Complete 0=Not complete Bit5 Bit4 Reserved Bit3 Bit2 Bit1 Bit0 OOP 1=Out of pull-in range 0=In range LOL 0=No LOL 1=LOL LOS 0=No LOS 1=LOS SYNC: 0=No Sync 1=Sync Bit3 Bit2 Bit1 Bit0 SYNC: Indicates synchronization has been achieved LOS: Loss of signal LOL: Loss of lock OOP: Out of pull-in range LHC: Long Term History Complete LHA: Long Term History Available T0_Accu_Flush, 0x38 (W) Address Bit7 Bit6 Bit5 0x38 Bit4 Not used HO flush Writing to this register will perform a flush of the accumulated history. The value of bit zero determines which histories are flushed. Bit 0 = 0, Flush T0 current history only; bit 0 = 1, flush all T0 histories. T4_Control_Mode, 0x39 (R/W) Address 0x39 Bit7 Bit6 Not used Bit5 Bit4 Bit3 Bit2 OOP: Out of Pull-in range: 0=Follow 1=Don’t follow Manual/ Auto 0=Manual 1=Auto Revertive 0=Nonrevertive 1=Revertive Accu_Usage 0=LTH 1=User Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 33 of 44 Bit1 Rev: P02 Bit0 Phase Align Mode 0=Arbitrary 1=Align Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Mode control bits for T4. Bit 0: 0 = Arbitrary (use initial phase), 1 = Phase align Bit 2, Accu_Usage: 0 = Device calculated long term history (LTH) is used; 1 = User supplied history is used. Bit 5, OOP: In manual mode, when the selected active reference is out of the pull-in range, as specified in register Disqualification_Range, 0x10, OOP will determine if the reference is to be followed, 0 = Don’t follow, 1 = Follow. Default value: 0. T4_Bandwidth, 0x3a (R/W) Address Bit7 0x3a Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit2 Bit1 Bit0 Not used Sets the T4 bandwidth: 0x1d, bits 4 ~ 0 Bandwidth, Hz 0 107 1 50 2 24 3 12 4 5.9 5 2.9 6 1.5 7 .73 8 0.37 9 0.18 10 0.09 31 ~ 11 Reserved Default value: 0. T4_Auto_Active_Ref, 0x3b (R) Address Bit7 Bit6 0x3b Bit5 Bit4 Bit3 Not used Values from 0 - 12 Indicates the automatic selected active reference for T4. T4_Manual_Active_Ref, 0x3c (R/W) Address 0x3c Bit7 Bit6 Bit5 Bit4 Bit3 Not used Bit2 Bit1 Bit0 Values from 0 - 15 Selects the active reference and the phase align mode for T4 in manual reference select mode. Bit 3 ~ Bit 0 0000 0001 ~ 1100 Phase Align Mode/Ref selection Freerun Ref 1 ~ Ref 12 Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 34 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Bit 3 ~ Bit 0 Phase Align Mode/Ref selection 1101 ~ 1111 Default value: 0. Holdover T4_Long_Term_Accu_History, 0x41 (R) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 0x41 Bits 0 - 7 of 32 bit Long Term Holdover History 0x42 Bits 8 - 15 of 32 bit Long Term Holdover History 0x43 Bits 16 - 23 of 32 bit Long Term Holdover History 0x44 Bits 24 - 31 of 32 bit Long Term Holdover History Bit1 Bit0 Bit1 Bit0 Bit1 Bit0 Bit1 Bit0 Long term accumulated history for T4 relative to the TCXO. Resolution is 0.745x10-3 ppb. T4_Short_Term_Accu_History, 0x45 (R) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 0x45 Bits 0 - 7 of 32 bit Short Term Holdover History 0x46 Bits 8 - 15 of 32 bit Short Term Holdover History 0x47 Bits 16 - 23 of 32 bit Short Term Holdover History 0x48 Bits 24 - 31 of 32 bit Short Term Holdover History Short term accumulated history for T4 relative to the TCXO. Resolution is 0.745x10-3 ppb. T4_User_Accu_History, 0x49 (R/W) Address Bit7 Bit6 Bit5 0x49 Bit4 Bit3 Bit2 Bits 0 - 7 of 32 bit User Holdover History 0x4a Bits 8 - 15 of 32 bit User Term Holdover History 0x4b Bits 16 - 23 of 32 bit User Term Holdover History 0x4c Bits 24 - 31 of 32 bit User Term Holdover History User accumulated history for T4 relative to the TCXO. Resolution is 0.745x10-3 ppb. Default value: 0. T4_HO_Ramp, 0x4d (R/W) Address Bit7 0x4d Not used Bit6 Bit5 Bit4 Bit3 Long term History bandwidth Bit2 Short term History bandwidth Ramp control Holdover bandwidth and ramp controls for T4: 0x30, bits 6 ~ 4 Long term History Bandwidth, mHz 000 9.7 mHz 001 4.9 mHz 010 2.4 mHz Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 35 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet 0x30, bits 6 ~ 4 Long term History Bandwidth, mHz 011 1.2 mHz 100 0.61 mHz 101 0.30 mHz 0x30, bits 3 ~ 2 Short term History Bandwidth, mHz 00 2.5 mHz 01 1.24 mHz 10 0.62 mHz 11 0.31 mHz 0x30, bits 1 ~ 0 Ramp control, ppm/sec 00 No Control 01 1 10 1.5 11 2 Default value: 0x24. T4_Priority_Table, 0x4e (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 0x4e Ref 2 Priority 0x4f Ref 4 Priority Ref 3 Priority 0x50 Ref 6 Priority Ref 5 Priority Bit0 Ref 1 Priority 0x51 Ref 8 Priority Ref 7 Priority 0x52 Ref 10 Priority Ref 9 Priority 0x53 Ref 12 Priority Ref 11 Priority Reference priority for automatic reference selection mode. Lower values have higher priority: 0x31 - 0x36, 4 bits Reference Priority 0000 Disable reference 0001 ~ 1111 1 ~ 15 Default value: 0. T4_PLL_Status, 0x54 (R) Address Bit7 Bit6 0x54 LHA 1=Available 0=Not available LHC 1=Complete 0=Not complete Bit5 Bit4 Reserved Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Bit3 Bit2 Bit1 Bit0 OOP 1=Out of pull-in range 0=In range LOL 0=No LOL 1=LOL LOS 0=No LOS 1=LOS SYNC: 0=No Sync 1=Sync Page 36 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet SYNC: Indicates synchronization has been achieved LOS: Loss of signal LOL: Loss of lock OOP: Out of pull-in range LHC: Long Term History Complete LHA: Long Term History Available T4_Accu_Flush, 0x55 (W) Address Bit7 Bit6 Bit5 Bit4 0x55 Bit3 Bit2 Bit1 Not used Bit0 HO flush Writing to this register will perform a flush of the accumulated history. The value of bit zero determines which histories are flushed. Bit 0 = 0, Flush T4 current history only; bit 0 = 1, flush all T4 histories. CLK0_Sel, 0x56 (R/W) Address Bit7 Bit6 Bit5 Bit4 0x56 Bit3 Bit2 Bit1 Not used Bit0 0=Disable 1=Enable Enables or disables the 155.52MHz CLK0 output. Default vale: 0. CLK1_Sel, 0x57 (R/W) Address Bit7 Bit6 0x57 Bit5 Bit4 Bit3 Bit2 Bit1 Not used Bit0 CLK1 Select Selects or disables the CLK1 output. 0x57, bits 1 ~ 0 CLK1 output 0 Disabled 1 19.44MHz 2 38.88MHz 3 77.76MHz Default value: 1. Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 37 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet CLK2_Sel, 0x58 (R/W) Address Bit7 Bit6 Bit5 0x58 Bit4 Bit3 Bit2 Bit1 Not used Bit0 CLK2 Select Selects or disables the CLK2 output. 0x58, bits 1 ~ 0 CLK2 output 0 Disabled 1 19.44MHz 2 38.88MHz 3 77.76MHz Default value: 2. CLK3_Sel, 0x59 (R/W) Address Bit7 0x59 Bit6 Bit5 Bit4 Bit3 Not used Bit2 Bit1 Bit0 CLK3 Select Selects or disables the CLK3 output, and sets the pulse width. In variable pulse width, the width may be selected from 1 to 62 times the period of the 155.52MHz output (~6.43nS to 399nS). 0x59, bits 5 ~ 0 CLK3 8KHz output 0 Disabled 1 ~ 62 Pulse width 1 to 62 cycles of 155.52MHz 63 50% duty cycle Default value: 63. CLK4_Sel, 0x5a (R/W) Address Bit7 0x5a Bit6 Bit5 Bit4 Bit3 Not used Bit2 Bit1 Bit0 CLK4 Select Selects or disables the CLK4 output, and sets the pulse width. In variable pulse width, the width may be selected from 1 to 62 times the period of the 155.52MHz output (~6.43nS to 399nS). 0x5a, bits 5 ~ 0 CLK4 2KHz output 0 Disabled 1 ~ 62 Pulse width 1 to 62 cycles of 155.52MHz 63 50% duty cycle Default value: 63. CLK5_Sel, 0x5b (R/W) Address Bit7 Bit6 0x5b Bit5 Bit4 Bit3 Bit2 Bit1 Not used Bit0 CLK2 Select Selects or disables the CLK5 output. 0x5b, bits 1 ~ 0 CLK5 output 0 Disabled Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 38 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet 0x5b, bits 1 ~ 0 CLK5 output 1 DS3 Default value: 2. 2 E3 3 Disabled CLK6_Sel, 0x5c (R/W) Address Bit7 Bit6 0x5c Bit5 Bit4 Bit3 Bit2 Not used Bit1 Bit0 CLK6 Select Selects or disables the CLK6 output. Default = 0110, 2.048MHz: 0x5c, bits 3 ~ 0 CLK6 output 0 Disabled 1 2.048MHz 2 4.096MHz 3 8.192MHz 4 16.384MHz 5 32.768MHz 9 1.544MHz 10 3.088MHz 11 6.176MHz 12 12.352Hz 13 24.704MHz Default value: 1. CLK7_Sel, 0x5d (R/W) Address Bit7 Bit6 Bit5 0x5d Bit4 Bit3 Bit2 Bit1 Not used Bit0 CLK7 Select Selects or disables the CLK7 output. 0x5d, bits 1 ~ 0 CLK7 output 0 Disabled 1 T1 2 E1 3 Disabled Default value: 2. Intr_Event, 0x5e (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x5e Event 7: T4 cross reference changed from nonactive to active Event 6: T4 cross reference changed from active to nonactive Event 5: T4 DPLL status changed Event 4: T4 active reference changed in auto selection mode Event 3: T0 cross reference changed from nonactive to active Event 2: T0 cross reference changed from active to nonactive Event 1: T0 DPLL status changed Event 0: T0 active reference changed in auto selection mode Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 39 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 0x5f Bit1 Bit0 Event 9: Any reference changed from disqualified to qualified Event 8: Any reference changed from qualified to disqualified Interrupt event, 0 = no event, 1 = event occurred. Interrupt 8 and 9 apply to the 12 reference inputs only. Interrupts are cleared by writing “1’s” to the bit positions to be cleared (See General Register Operation, Clearing bits in the Interrupt Status Register section). Intr_Enable, 0x60 (R/W) Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x60 Intr 7 Enable Intr 6 Enable Intr 5 Enable Intr 4 Enable Intr 3 Enable Intr 2 Enable Intr 1 Enable Intr 0 Enable Intr 9 Enable Intr 8 Enable 0x61 Interrupt disable/enable, 0 = disable, 1 = enable. Default value: 0. Application Notes This section describes typical application use of the STC4130 device. The General section applies to all application variations, while the remaining sections detail use depending on the level of control and automatic operation the application desires. General Power and Ground Well-planned noise-minimizing power and ground are essential to achieving the best performance of the device. The device requires 3.3 and 1.8V digital power and 1.8V analog power input. All digital I/O is at 3.3V, LVTTL compatible. The 1.8V may originate from a common source but should be individually filtered and isolated, as shown in Figure 17. Alternatively, a separate 1.8V regulator may be used for the analog 1.8 volts. R/C filter components should be chosen for minimum inductance and kept as close to the chip as possible. It is desirable to provide individual bypass capacitors, located close to the chip, for each of the digital power input leads, subject to board space and layout constraints. On power-up, it is desirable to have the 1.8V either lead or be coincident with, but not lag the application of 3.3V. Digital ground should be provided by as continuous a ground plane as possible. While the analog and digital grounds are tied together inside the chip, it is recommended that they be tied together externally at a single point close to the chip as well. Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 40 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet .1uF ceramic 3.3V 3.3V digital power inputs Vdd33 (9) MCLK 10MHz/20MHz OCXO/ TCXO STC4130 MCLK_FRQ_SEL .1uF ceramic 1.8V 1.8V digital power inputs 0=10MHz 1=20MHz Vdd18 (10) .1uF Digital ground 1.8V 5 ohm,1/4W 1.8V analog power inputs AVdd18 (2) Analog ground Vss (16) AVss (2) (x) Number of pins Figure 17: Power, Ground and Oscillator connections The external TCXO/OCXO master oscillator is connected to the MCLK pin, and the MCLK_FRQ_SEL pin is tied low for 10MHz or high for 20MHZ. Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 41 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet MECHANICAL DRAWING Figure 18: Mechanical Dimensions * Dimensions are in mm [inches] Ordering Information Part Number STC4130 STC4130-I Description Commercial Temperature Range Model Industrial Temperature Range Model Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 42 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 43 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice STC4130 Synchronous Clock for SETS Data Sheet Functional Specification Revision P00 P01 P02 Date 5/12/06 8/31/06 12/5/06 Changes Initial Release Edited TOC, pg.2 Added Mechanical Dimensions on pg.42, Added Industrial Temp Range Part Number Information furnished by Connor-Winfield is believed to be accurate and reliable. However, no responsibility is assumed by Connor-Winfield for its use, nor for any infringements of patents or other rights of third parties that my result from its use. Specifications subject to change without notice. For more information, contact: 2111 Comprehensive DR Aurora, IL. 60505, USA 630-851-4722 630-851-5040 FAX www.conwin.com Data Sheet #: TM084 © Copyright 2006 The Connor-Winfield Corp. Page 44 of 44 Rev: P02 Date: 12/5/06 All Rights Reserved Specifications subject to change without notice