Stratum 3+ Simplified Control Timing Modules STM-S3+ 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com Application The Connor-Winfield Stratum 3+ Simplified Control Timing Module can be used as a complete system clock module for any Stratum 3 timing application in which the design requires the added capabilities of a Stratum 3E level Hold Over within 5°C variation in accordance with GR-1244-CORE-1995. Connor-Winfield’s Stratum 3+ Timing module helps reduce the cost of your design by minimizing your development time and maximizing your control of the system clock with our simplified design. US Headquarters: 630-851-4722 European Headquarters: +353-62-472221 Features • 4 Operational Modes • Stratum 3 Clocking System • Stratum 3E Hold Over Accuracy ±5° • Hitless Reference Switching • 5 Active Alarms • Guaranteed Free Run • Lock Time of 100 Secs • TVL Alarm General Description Functional Block Diagram The Connor-Winfield Stratum 3+ Simplified Control Timing Module (STM-3+) meets every Stratum 3 requirement of GR-1244-CORE-1995. In addition, it also provides the enhanced Hold Over accuracy of Statum 3E specifications over ±5° C range. Control loop filters effectively attenuate any reference jitter and smooth out phase transients. The STM-3+ is designed to be controlled externally. Full external control input allows the user to select and monitor any of the four possible operating modes: • Free Run Mode (A=0, B=0 =>Free Run=1) • Normal Mode #1 (A=1, B=0 => Ref 1=1) • Normal Mode #2 (A=0, B=1 =>Ref 2=1) • Hold Over Mode (A=1, B=1 =>Hold Over=1) Table 4 illustrates the control signal inputs (A,B) and the corresponding operational modes. Real-time indication of the operational mode is indicated by unique operating mode outputs on pins 1-4. In addition, all outputs can be placed into a high impedence state when a high signal is placed on the Tri-State control pin Normal Mode #1 results in an output signal that is phase locked to the External Reference Input #1. Normal Mode #2 results in an output signal that is phase locked to External Reference Input #2. Hold Over mode results in an output signal at or near the frequency as determined by a past historical value and the holdover performance of the STM. The historical value is updated every 40 secs. In the absence of External Control Inputs, the STM enters the default Free Run mode and signals an external alarm. Free Run mode is a guaranteed ±4.6 ppm of the nominal frequency. The STM-S3+ provides an alarm pin that goes high during an alarm condition. Alarm signals are generated at the Alarm Out pin during the following conditions: • Holdover • Free Run • Loss of Lock (LOL) • Loss of Reference (LOR) • Tune-Limit (PLL_TVL) A Tune-Limit (PLL_TVL) alarm signal indicates that the Voltage Controlled OCXO tuning voltage is approaching within the 10% limit of its lock capability and LOL may soon occur. Figure 1 CNTL A 0 Free Run 1 Ref 1 PLL TVL 2 CNTL B Ref 2 Free Run 3 Hold Over Hold Over Alarm Out Ex Ref 1 PHASE 2 :1 COMPARATOR MUX Ex Ref 2 LOCK DETECT Sync_Out Stratum 3+ DAC DAC FILTERS TUNING OCXO Stratum 3 LIMIT FIFO TCXO Clock_Out MONITOR PLL TVL STM-S3+ Package Layout Figure 2 .030 (.762mm) .150 .082 (2.08mm) .040 (1.02mm) (3.810mm) .120 (3.05mm) “A-A” DETAIL “A-A” 2.40 + 0.02 (60.96mm) .192 2.000 (4.876mm) .200 (50.80mm) (5.08mm) 24 2 22 3 21 4 20 5 3.95+ 0.02 19 6 (100.330mm) 18 7 17 8 16 9 15 .445 (16.50mm) 1 23 13 PIN 1 10 .300 TYP (22) (7.62mm) 14 .650 + 0.02 11 12 (11.30mm) Bottom view Tolerance .XXX + .005 Preliminary Data Sheet #: TM021 Page 2 of 12 Rev: P03 Date: 06/27/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Absolute Maximum Rating Table 1 STM-S3+ Symbol Parameter Minimum Nominal Maximum Units Notes VCC Power Supply Voltage (Vcc to GND) -0.5 - +7.0 Volts 1.0 VIN Input Voltage -0.5 - +5.5 Volts 1.0 TSTG Storage Temperature -40.0 - +90 deg. C 1.0 Notes Recommended Operating Conditions Table 2 STM-S3+ Symbol Parameter Minimum Nominal Maximum Units VCC Power Supply Voltage (vcc to GND) 4.75 5.0 5.25 V VPOR Power-on Reset Voltage Level 4.25 4.5 V VIH High Level Input Voltage (TTL Compatible) 2.0 5.25 V VIL Low Level Input Voltage (TTL Compatible) 0.8 V TIN Input Signal Transition Time 250.0 nS CIN Input Capacitance 15.0 pF VOH High Level Output Voltage @IOH=8.0 mA, Vcc minimum VOL Low Level Output Voltage @IOH=8.0 mA, Vcc maximum THL Clock out transition time high-to-low, no load 4.0 nS TLH Clock out transition time low-to-high, no load 4.0 nS TRIP Input 8 kHz reference signal positive pulse width 30.0 TRIN Input 8 kHz reference signal Negative pulse width 30.0 TAB Mode Select Response TOP Standard Opearting temperature 0.0 2.4 V 0.4 2.0 3.0 V nS nS 2 mS 0.0 70.0 deg. C Operating Specifications Table 3 STM-S3+ Parameter Specifications Notes Frequency Range 16.384 MHz, 19.44 MHz, 38.88 MHz Supply Current 350 mA Typical, 550 mA during warmup Timing Reference Inputs GR-1244-CORE 3.2.1, R3-1 Jitter, Phase Transient and Wander Tolerances GR-1244-CORE 4.2-4.4 Wander Genration GR-1244-CORE 4.2-4.4 Free Run Accuracy Holdover Stability ±4.6 ppm (0° - 70°) ±0.039 ppm (±5°C) ±0.012 ppm Initial Offset ±0.001 ppm ±0.001 ppm Temperature ±0.035 ppm ±0.010 ppm Drift ±0.003 ppm Holdover History ±0.001 ppm 40 sec Pull-in / Hold-in Range ±4.6 ppm Lock Time < 100 sec Lock Accuracy PLL-TVL Alarm Limits 4.0 5.0 0.001 ppm 6.0 Within 10% of Tuning Range Limit, See Fig 8 Preliminary Data Sheet #: TM021 © Copyright 2001 The Connor-Winfield Corp. Page 3 of 12 Rev: P03 Date: 06/27/01 All Rights Reserved Specifications subject to change without notice Pin Assignment Typical Application Figure 3 Figure 4 +5VDC Hold Over Ex Ref 1 Ref 1 GND Ref 2 Ex Ref 2 5 Volt DC Power Supply 5 VDC Network Timing Reference Input eg. BITS Free Run GND GND N/C N/C Clock_Out N/C GND Tri-State Ref 1 Ref 2 GND Ex Ref 2 Independent Clock Free Run GND GND N/C N/C Clock_Out N/C GND N/C N/C Sync_Out N/C Loss of Reference Monitor Section Alarm Out Sync_Out CNTL A GND Tri-State N/C System Clock Alarm Out System Control and Data Inputs Hold Over Ex Ref 1 GND CNTL A PLL TVL CNTL B CNTL B PLL TVL BOTTOM VIEW Operational Modes Table 4 Control Input Pins Tri-State A 0 0 0 0 1 0 B 0 0 1 Output Indicator Pins Operational Mode Operational Mode Ref 1 Ref 2 Free Run (default) 0 0 0 Normal 1 0 Tune Limit 1 0 Mode #1 Mode #2 Hold Over Free Run PLL_TVL Alarm Out *Clock-Out Sync Out 1 0 2 Per Spec 0 0 0 0 Per Spec 0 0 1 1 Per Spec LOR + LOL 1 0 0 0 0 1 Per Spec Normal 0 1 0 0 0 0 Per Spec Tune Limit 0 1 0 0 1 1 Per Spec LOR + LOL 0 1 0 0 0 1 Per Spec 0 0 1 0 0 or 1 1 Per Spec 0 1 1 Hold Over Mode 1 X X Tri-State Mode High Impedence * See GR-1244-CORE, Issue 3 for Clock Out and Sync Out Preliminary Data Sheet #: TM021 Page 4 of 12 Rev: P03 Date: 06/27/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Pin Description Table 5 Pin # Pin Name Pin Information 1 Hold Over Mode indicator. When the STM is in holdover mode, Hold Over will be a logic high output. 2 Ref 1 Mode indicator. When the STM is using External Reference #1, Ref 1 will be a logic high output. 3 Ref 2 Mode indicator. When the STM is using External Reference #2, Ref 2 will be a logic high output. 4 Free Run Mode indicator. When the STM is in free run mode, Free Run will be a logic high output. 5 GND Ground. 6 N/C No connection required 7 N/C No connection required 8 Tri-State Tri-State control for all outputs. 1=Hi-Z, 0=normal. 9 N/C No connection required 10 Alarm Out Alarm indicator output. 11 CNTL A Mode control input. 12 CNTL B Mode control input. 13 PLL TVL Tuning Voltage Alarm. 14 GND Ground. 15 Sync_Out System clock output. 16 N/C No connection required 17 GND Ground. 18 Clock_Out An independent Stratum 3 clock output with the required ±4.6 ppm. Can be used for general purpose clocking needs. 19 N/C No connection required 20 GND Ground. 21 Ex Ref 2 External Reference #2 Input. 22 GND Ground. 23 Ex Ref 1 External Reference #1 Input. 24 +5 V DC +5 Volt DC supply. (Vcc) Preliminary Data Sheet #: TM021 © Copyright 2001 The Connor-Winfield Corp. Page 5 of 12 Rev: P03 Date: 06/27/01 All Rights Reserved Specifications subject to change without notice Operational Mode Change Timing Diagram Loss of Reference Timing Diagram Figure 5 Figure 6 Change in Operational Mode External Reference Input Operational Mode Indicator Dt Alarm m tA on 2 msec <Dtm < 4.125 msec tAoff 2 msec < tAon < 6.125 msec 0 msec < tAoff < 2.125 msec TVL Alarm Timing Diagram TVL Alarm Range Figure 7 Figure 8 Frequency (ppm) TVL Limit High Frequency max = 14ppm min 9ppm Sync_Out (Nominal Frequency) TVL Limit Low Frequency TVL Alarm & Alarm Out min = -9ppm max -14ppm Dt 0 < Dt < 2.125 msec 0.5 V *The DAC is updated only when the output changes level. The maximum update rate is 8 kHz 3.8 V Maximum Current Draw Mounting Clearances Figure 9 Figure 10 Voltage Controlled OCXO Voltage (V) 0.600 .020" MAX. 0.550 Current (A) 0.500 0.450 .020" 0.400 0.350 .030" PIN LAND 0.300 0 1 2 3 4 5 6 7 8 Elapsed Time (min) Preliminary Data Sheet #: TM021 ALL SOLDER AND/OR WIRE TAGS SHALL NOT EXTEND MORE THAN .020" BELOW PC BOARD BOTTOM SURFACE Page 6 of 12 Rev: P03 Date: 06/27/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Typical System Test Set-up Figure 11 GPS or LORAN Timing Source This device supplies system time information. It can be thought of as supplying "absolute time" reference information S a m p le M T IE D a t a fo r S T M -S 3 /M S T M -S 3 1 .0 E -6 Possible Choices Include Stanford Research Model: FS700 Truetime Model XXX T ypi c al r es p o n s e - 3 0 0 0 s e co nd t e s t - J it t e r a pp li ed (2 U I @ 1 0 H z ) re f dat e A P R 2 2 1 9 9 8 k dh M T IE (s 1 0 0 .0 E -9 10 MHz MT IE 1 0 .0 E -9 1 2 44 - 5.2 Ma s k ( A ) 1 2 44 - 5.2 Ma s k ( B ) 1 2 44 - 5.6 Ma s k G R 25 3 - 5 .4 .4 .3 .2 1 .0 E -9 1 0 0 .0 E - 3 1 .0 E +0 1 0 .0E +0 1 0 0 .0 E +0 O b s e rva tion T im e (s ) 1.0 E +3 1 0 .0 E +3 C o pyr i ght 19 9 8 C o nn o r - W in fi e ld al l r i ght s r es er v ed Target System Under Test Clock or BITS logic level clock input (TTL, CMOS, etc.) Arbitrary Waveform Generator [Noise Source] S a m p le W a n d e r G e n e ra ti o n (T D E V) fo r S T M /M S T M - S 3 1 .0 E- 6 T ypi cal r e s p o ns e - 3 0 0 0 s eco nd te s t - J it t er a ppl ie d (2 U I @ 1 0 H z ) r e f dat e A P R 2 2 1 9 9 8 k dh 1 0 0 .0 E- 9 1 0 .0 E- 9 TD E V (s e c DS-1 Line Card OC-48 Line Card OC-3 Line Card . . . . ... OC-12 Line Card MTIE, TDEV, Wander Transfer, and Wander Generation Plots Line Card Noise Modulation Input 10 MHz External Reference Input Standards Compliance Documents DS1 rate RZ (1.544 MHz), E1 rate RZ or 8 kHz clock RZ with noise modulation Timing Card Arbitrary Waveform Generator Timing Card External Reference Input T D EV G R 1 24 4- F ig5 .1 1 .0 E- 9 G R 1 24 4- F ig5 - 3 1 0 0 .0 E -1 2 1 0 .0 E - 3 1 0 0 .0 E - 3 1 .0 E +0 1 0.0 E +0 I n te g r a t i o n T i m e ( s e c ) 1 0 0 .0 E +0 1 .0 E +3 C o py ri ght 1 9 9 8 C o nno r -W i nf iel d al ll rig ht s r es e rv ed Time-stamped ensemble based on absolute time reference (10MHz input) 10 MHz DS1 rate [1.544 MHz] BITS Bipolar Phase Error data output DS-1, OC-3, OC-12 electrical or optical signals 10 MHz Tektronix SJ300E External Reference Input HP53310A Modulation Analyzer / Time Interval Analyzer Wander Analyzer data (IEEE-488) External Reference Input IEEE-488 Controller Platform for software HP 53305A Phase Analyzer HP E1748A Sync Measurement Tektronix Wander Analyzer TEKTRONIX SJ300E Preliminary Data Sheet #: TM021 © Copyright 2001 The Connor-Winfield Corp. Page 7 of 12 Rev: P03 Date: 06/27/01 All Rights Reserved Specifications subject to change without notice Typical MTIE - Over Temperature with Noise Figure 12 yp MTIE (ns) GR-1244-CORE Mask MTIE (ns) 100 10 1 0.01 0.1 1 10 100 1000 10000 1000 Observation Interval (sec) Typical TDEV - Over Temperature with Noise Figure 13 yp TDEV (ns) GR-1244-CORE Mask TDEV (ns) 10 1 0.1 0.01 0.01 0.1 1 10 100 1000 10000 100000 Observation Time (sec) Preliminary Data Sheet #: TM021 Page 8 of 12 Rev: P03 Date: 06/27/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice 1 µs Phase Transient Figure 14 µ 10000 MTIE (ns) GR-253-CORE Mask MTIE (ns) 1000 100 10 1 0.01 0.1 1 10 100 1000 Observation time (sec) Reference Switching Phase Transient Figure 15 g 10000 MTIE (ns) GR-253-CORE Mask MTIE (ns) 1000 100 10 1 0.01 0.1 1 10 100 1000 Observation Time (sec) Preliminary Data Sheet #: TM021 © Copyright 2001 The Connor-Winfield Corp. Page 9 of 12 Rev: P03 Date: 06/27/01 All Rights Reserved Specifications subject to change without notice Hold Over Entry and Exit with Same Reference Figure 1 10000 1000 Entry Exit MTIE (ns) GR-253-CORE Mask 100 10 1 0.01 0.1 1 10 100 Observation Interval Wander Transfer Figure 17 1000 Wander Transfer GR-253-CORE Mask TDEV (ns) 100 10 1 0.1 0.01 0.1 1 10 100 1000 10000 Observation Time (sec) Preliminary Data Sheet #: TM021 Page 10 of 12 Rev: P03 Date: 06/27/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice NOTES: 1.0 Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure ot Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2.0 Power-on reset will be acivated within this level. 3.0 Nominal signal into a CMOS load is usually 3V or greater. 4.0 Hold Over stability is the cumulative fractional frequency offset containing Initial Offset, Temperature, and Drift components as described by Bellcore GR-1244-CORE 5.2. 5.0 Pull-in range is the maximum frequency deviation on the reference inputs to the timing module that can be overcome to pull itself into synchronization with the reference. 6.0 After 100 seconds at stable room temperature. Ordering Information: STM-S3+ – 16.384 MHz STM-S3+ – 19.44 MHz STM-S3+ – 38.88 MHz REVISION REVISION DATE NOTE P00 6/29/00 Preliminary informational release P01 2/05/00 Changed Format P02 2/27/01 Minor Corrections P03 6/27/01 Reformatted Layout Preliminary Data Sheet #: TM021 © Copyright 2001 The Connor-Winfield Corp. Page 11 of 12 Rev: P03 Date: 06/27/01 All Rights Reserved Specifications subject to change without notice Data Sheet #: TM021 Page 12 of 12 Rev: 02 Date: 02/27/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice