DS125RT410 www.ti.com SNLS459 – APRIL 2011 DS125RT410 Low Power Multi-Rate Quad Channel Retimer Check for Samples: DS125RT410 FEATURES APPLICATIONS • • 1 2 • • • • • • • • • • • • • • Each channel independently locks to data rates from 9.8 to 12.5 Gbps and submultiples Fast lock operation based on protocol-select mode Low latency (~300ps) Adaptive equalization up to 34 dB boost at 5 GHz Adjustable transmit VOD : 600 to 1300 mVp-p Adjustable transmit de-emphasis to -15 dB Typical Power Dissipation (EQ+CDR+DE): 150 mW / channel Programmable output polarity inversion Input signal detection, CDR lock detection/indicator On-chip Eye Monitor (EOM), PRBS generator Single 2.5 V ±5% power supply SMBus/EEPROM configuration modes Operating temperature range of -40 to 85°C RHS 48-pin 7 mm x 7 mm package Easy pin compatible upgrade between repeater and retimers – DS100RT410 (EQ+CDR+DE): 10.3125 Gbps – DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps – DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps – DS110DF410 (EQ+DFE+CDR+DE): 8.5 - 11.3 Gbps – DS125RT410 (EQ+CDR+DE): 9.8 - 12.5 Gbps – DS125DF410 (EQ+DFE+CDR+DE): 9.8 - 12.5 Gbps – DS100BR410 (EQ+DE): Up to 10.3125 Gbps • • • • Front port SFF 8431 (SFP+) optical and direct • Input signal detection, CDR lock attach copper Backplane reach extension, data retimer Ethernet: 10GbE, 1GbE CPRI: Line bit rate options 3–7 Interlaken: All lane bit rates For other data rates and data transmission protocols, other pin-compatible devices in the retimer family can be used. DESCRIPTION The DS125RT410 is four channel retimers with integrated signal conditioning. The devices include a fully adaptive Continuous-Time Linear Equalizer (CTLE), Clock and Data Recovery (CDR) and transmit De-Emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1×10-15. Each channel can independently lock to data rate from 9.8 to 12.5 Gbps, and associated sub rates (div by 2, 4 and 8) to support a variety communication protocols. A 25 MHz reference clock is required, which need not be synchronous with the serial data. The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded via an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning. Flow-through pinout and single power supply make the DS125RT410 easy to use. The device is offered in a RHS 48-pin, 7 mm x 7 mm package with flow-through pinout for the high speed signals. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated DS125RT410 SNLS459 – APRIL 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Typical Application Diagram Line Card Switch Fabric Optical Modules DS125RT410 x4 DS125RT410 ASIC x4 Connector DS125RT410 x4 ASIC 10GbE CPRI Interlaken Others SFP+ (SFF8431) QSFP x4 Back Plane/ DS125RT410 Passive Copper Mid Plane Clean Signal 2 Submit Documentation Feedback Noisy Signal Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 VDD LOCK_0/ADDR_0 READ_EN INT REFCLK_OUT ALL_DONE LOCK_1/ADDR_1 GND LP F_CP_ 1 LP F_REF_1 45 44 43 42 41 40 39 38 37 LP F_CP_ 0 47 46 LP F_REF_0 48 Connection Diagram RXP0 1 36 TXP0 RXN0 2 35 TXN0 VDD 3 34 GND RXP1 4 33 TXP1 RXN1 5 32 TXN1 VDD 6 31 GND VDD 7 7 mm x 7 mm, 0.5 mm pitch 30 GND RXP2 8 TOP VIEW 29 TXP2 RXN2 9 DAP = GND 28 TXN2 VDD 10 27 GND RXP3 11 26 TXP3 RXN3 12 25 TXN3 13 14 15 16 17 18 19 20 21 22 23 24 LP F_REF_3 LP F_CP_ 3 VDD LOCK_3/ADDR_3 SDC SDA REFCLK_IN EN_SMB LOCK_2/ADDR_2 GND LP F_CP_ 2 LP F_REF_2 DS125RT410 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 3 DS125RT410 SNLS459 – APRIL 2011 www.ti.com Pin Descriptions Pin Name Pin # I/O, Type Description HIGH-SPEED DIFFERENTIAL I/O RXP0 RXN0 1 2 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. RXP1 RXN1 4 5 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. RXP2 RXN2 8 9 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. RXP3 RXN3 11 12 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100Ω. TXP0 TXN0 36 35 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. TXP1 TXN1 33 32 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. TXP2 TXN2 29 28 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. TXP3 TXN3 26 25 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100Ω. LOOP FILTER CONNECTION PINS LPF_CP_0 LPF_REF_0 47 48 I/O, analog Loop filter connection Place a 22 nF ± 10% Capacitor between LPF_CP_0 and LPF_REF_0 LPF_CP_1 LPF_REF_1 38 37 I/O, analog Loop filter connection Place a 22 nF ± 10% Capacitor between LPF_CP_1 and LPF_REF_1 LPF_CP_2 LPF_REF_2 23 24 I/O, analog Loop filter connection Place a 22 nF ± 10% Capacitor between LPF_CP_2 and LPF_REF_2 LPF_CP_3 LPF_REF_3 14 13 I/O, analog Loop filter connection Place a 22 nF ± 10% Capacitor between LPF_CP_3 and LPF_REF_3 REFCLK_IN 19 I, 2.5V analog Input is 2.5 V, 25 MHz ± 100 ppm reference clock from external oscillator No stringent phase noise requirement REFCLK_OUT 42 O, 2.5V analog Output is 2.5 V, buffered replica of reference clock input for connecting multiple DS125RT410s on a board. 45 40 21 16 O, 2.5V LVCMOS Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding channel. Note that these pins are shared with SMBus address strap input functions read at startup. REFERENCE CLOCK I/O LOCK INDICATOR PINS LOCK0 LOCK1 LOCK2 LOCK3 SMBus MASTER MODE PINS ALL_DONE 41 O, 2.5V LVCMOS Output is 2.5 V, the pin goes low to indicate that the SMBus master EEPROMread has been completed. READ_EN 44 I, 2.5V LVCMOS Input is 2.5 V, a transition from high to low starts the load from the external EEPROM. The READ_EN pin must be tied low when in SMBus slave mode. INTERRUPT OUTPUT INT 43 O, 3.3V Used to signal horizontal or vertical eye opening out of tolerance, loss of signal LVCMOS, Open detect, or CDR unlock. Drain External 2KΩ to 5KΩ pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant. SERIAL MANAGEMENT BUS (SMBus) INTERFACE EN_SMB 20 SDA 18 I/O, 3.3V Data Input / Open Drain Output LVCMOS, Open External 2KΩ to 5KΩ pull-up resistor is required. Drain Pin is 3.3 V LVCMOS tolerant. SDC 17 I/O, 3.3V Clock Input / Open Drain Clock Output LVCMOS, Open External 2KΩ to 5KΩ pull-up resistor is required. Drain Pin is 3.3 V LVCMOS tolerant. 4 I, 2.5V analog Input is 2.5 V, selects SMBus master mode or SMBus slave mode. EN_SMB = High for slave mode EN_SMB = Float for master mode Tie READ_EN pin low for SMBus slave mode. See Table 3 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 Pin Descriptions (continued) Pin Name Pin # I/O, Type 45 40 21 16 I, 2.5V LVCMOS VDD 3, 6, 7, 10, 15, 46 Power VDD = 2.5 V ± 5% GND 22, 27, 30, 31, 34, 39 Power Ground reference. DAP PAD Power Ground reference. The exposed pad at the center of the package must be connected to ground plane of the board with at least 4 vias to lower the ground impedance and improve the thermal performance of the package. ADDR_0 ADDR_1 ADDR_2 ADDR_3 Description Input is 2.5 V, the ADDR_[3:0] pins set the SMBus address for the retimer. These pins are strap inputs. Their state is read on power-up to set the SMBus address in SMBus control mode. High = 1KΩ to VDD, Low = 1KΩ to GND Note that these pins are shared with the lock indicator functions. See Table 4 POWER Absolute Maximum Ratings (1) Supply Voltage (VDD) -0.5V to +2.75V 2.5 I/O Voltage (LVCMOS and Analog) -0.5V to +2.75V 3.3 LVCMOS I/O Voltage (SDA, SDC, INT) -0.5V to +4.0V Signal Input Voltage (RXPn, RXNn) -0.5V to +2.75V Signal Output Voltage (TXPn, TXNn) -0.5V to +2.75V Junction Temperature +150°C Storage Temperature -65°C to +150°C ESD Rating HBM, STD - JESD22-A114F ≥6 kV MM, STD - JESD22-A115-A ≥250 V CDM, STD - JESD22-C101-D ≥1250 V Thermal Resistance θJA, No Airflow, 4 layer JEDEC, 9 thermal vias 26.1 °C/W For soldering specifications: see product folder at http://www.ti.com/lit/an/snoa549c/snoa549c.pdf (1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated outside these conditions. Recommended Operating Conditions Min Typ Max Units 2.375 2.5 2.625 V -40 25 +85 °C Supply Voltage VDD to GND Ambient Temperature Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 5 DS125RT410 SNLS459 – APRIL 2011 www.ti.com Electrical Characteristics Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. Symbol Parameter Conditions Min Typ Max (1) Units POWER PD Power Supply Consumption NTPS Supply Noise Tolerance (4) Average Power Consumption (2) 660 Max Transient Power Supply Current (3) 500 50 Hz to 100 Hz 100 mVP-P 100 Hz to 10 MHz 40 mVP-P 10 MHz to 5.0 GHz 10 mVP-P mW 610 mA 2.5V LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage 1.75 VDD V VIL Low Level Input Voltage GND 0.7 V VOH High Level Output Voltage IOH = -3mA VOL Low Level Output Voltage IOL = 3mA 0.4 V IIN Input Leakage Current VIN = VDD +10 μA VIN = GND 2.0 V μA -10 IIH Input High Current (EN_SMB pin) VIN = VDD +55 μA IIL Input Low Current (EN_SMB pin) VIN = GND -110 μA 3.3 V LVCMOS DC SPECIFICATIONS (SDA, SDC, INT) VIH High Level Input Voltage VDD = 2.5 V 1.75 3.6 V VIL Low Level Input Voltage VDD = 2.5 V GND 0.7 V VOL Low Level Output Voltage IPULLUP = 3mA IIH Input High Current VIN = 3.6 V, VDD = 2.5V IIL Input Low Current VIN = GND, VDD = 2.5V fSDC SMBus clock rate 0.4 V +20 +40 μA -10 +10 μA 100 400 KHz 9.8 12.5 Gbps DATA BIT RATES RB Bit Rate Range SIGNAL DETECT SDH Signal Detect ON Threshold Level SDL Signal Detect OFF Threshold Level Default input signal level to deassert signal detect, 10.3125 Gbps, PRBS-31 (1) (2) (3) (4) 6 Default input signal level to assert signal detect, 10.3125 Gbps, PRBS-31 70 mVp-p 10 mVp-p Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization. VDD= 2.5V, TA = 25°C. All four channels active and locked. Max momentary power supply current lasting less than 1s. The retimer may consume more power than the maximum average power rating during the time required to acquire CDR lock. Allowed supply noise (mVP-P sine wave) under typical conditions. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. (1) Symbol Parameter Conditions Min Typ Max Units RECEIVER INPUTS (RXPn, RXNn) VTX2, min Minimum Source Transmit Launch Signal Level (IN, diff) (5) VTX2, max Maximum Source Transmit Launch Signal Level (IN, diff) (5) VTX1, max Maximum Source Transmit Launch Signal Level (IN, diff) (6) VTX0, max Maximum Source Transmit Launch Signal Level (IN, diff) (7) LRI Maximum Differential Input Return Loss - |SDD11| 100 MHz – 6 GHz ZD Differential Input Impedance ZS Single-Ended Input Impedance 600 mVP-P 1000 mVP-P 1200 mVP-P 1600 mVP-P -15 dB 100 MHz – 6 GHz 100 Ω 100 MHz – 6 GHz 50 Ω DRIVER OUTPUTS (TXPn, TXNn) VOD0 VOD7 VOD_DE tR, tF Differential output voltage Differential output voltage De-emphasis level (8) Transition time (rise and fall times) (8) (9) Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled, SMBus register VOD control (Register 0x2d bits 2:0) set to 0, minimum VOD De-emphasis control set to minimum (0 dB) 400 Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled SMBus register VOD control (Register 0x2d bits 2:0) set to 7, maximum VOD De-emphasis control set to minimum (0 dB) 1000 dB Transition time control = Full Slew Rate 39 ps Transition time control = Limited Slew Rate 50 ps -15 dB 300 ps 75 ps 10 ps 100 MHz – 6 GHz (10) tDP Propagation Delay Retimed data TJ De-emphasis pulse duration Output total jitter mVP-P -15 Maximum Differential Output Return Loss - |SDD22| TDE mVP-P Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled Set by SMBus register control to maximum de-emphasis setting Relative to the nominal 0 dB deemphasis level set at the minimum de-emphasis setting LRO (11) 675 Measured at VOD = 1000 mVP-P, de-emphasis setting = -12 dB -12 (12) Measured at BER = 10 Differential signal amplitude at the transmitter output providing < 1x10-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. Input transmission channel is 40-inch long FR-4 stripline, 4-mil trace width. (6) Differential signal amplitude at the transmitter output providing < 1x10-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. Input transmission channel is 30-inch long FR-4 stripline, 4-mil trace width. (7) Differential signal amplitude at the transmitter output providing < 1x10-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. No input transmission channel. (8) Measured with clock-like {11111 00000} pattern. (9) Slew rate is controlled by SMBus register settings. (10) Measured with 10 MHz clock pattern output. (11) De-emphasis pulse width varies with VOD and de-emphasis settings. (12) Typical with no output de-emphasis, minimum output transmission channel. (5) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 7 DS125RT410 SNLS459 – APRIL 2011 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. (1) Symbol TSKEW Parameter Intra Pair Skew Conditions Difference in 50% crossing between TXPn and TXNn for any output Min Typ Max Units 3 ps 5 MHz 0.6 UI -6 dB 15 ms CLOCK AND DATA RECOVERY BWPLL JTOL JTRANS TLOCK 8 PLL Bandwidth -3 dB Measured at 10.3125 Gbps -15 Input sinusoidal jitter tolerance 10 kHz to 250 MHz sinusoidal jitter frequency Measured at BER = 10 Jitter Transfer Sinusoidal jitter at 10 MHz jitter frequency Measured at BER = 10-15 CDR Lock Time Measured at 10.3125 Gbps Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 FUNCTIONAL DESCRIPTION The DS125RT410 is a low-power, multi-rate, 4-channel retimer. Each of the four channels operates independently. Each channel includes a Continuous-Time Linear Equalizer (CTLE) which compensates for the presence of a dispersive transmission channel between the source and the DS125RT410's input. Each channel includes an independent Voltage-Controlled Oscillator (VCO) and Phase-Locked Loop (PLL) which produce a clean clock. The clean clock produced by the VCO and the PLL is phase-locked to the incoming data clock and the high-frequency jitter on the incoming data is attenuated by the PLL, producing a clean clock with substantially reduced jitter. This clean clock is used to retime the incoming data, removing high-frequency jitter from the data stream and producing a data output signal with reduced jitter. Each channel of the DS125RT410 features an output driver with programable differential output voltage and output de-emphasis control. The output de-emphasis compensates for dispersion in the transmission channel at the output of the DS125RT410. These three functions together make up the data path for the DS125RT410. EQ RETIMER DRIVER RXPn TXPn CDR RXNn TXNn 100 100 SMBus SMBus SMBus SDC SDA EN_SMB LOCK REFCLK_IN Signal Detect Figure 1. DS125RT410 Data Path Block Diagram — One of Four Channels Device Data Path Operation The data path operation of the DS125RT410 comprises three functional sections as shown in the data path block diagram of Figure 1. The three functional sections are as follows. • Channel Equalization • Clock and Data Recovery • Output Driver Channel Equalization Physical transmission media such as traces on printed circuit boards (PCBs) or copper cables exhibit a low-pass frequency response characteristic. The magnitude of the high-frequency loss varies with the length of the transmission media and with the loss of the materials which comprise it. This differential high-frequency loss and the frequency-dependent group delay of the transmission media introduce inter-symbol interference in the highspeed broadband signals propagating through the transmission media. The DS125RT410 applies a frequency-response equalization function to the incoming data stream. The equalization function reduces the effect of the frequency-dependent loss in the transmission media between the transmitter output and the input of the DS125RT410. The DS125RT410 includes a Continuous Time Linear Equalizer or CTLE which applies the frequency-response equalization. The CTLE is designed to provide a controlled-amount of high-frequency boost to the signal in the frequency domain to compensate for the frequency-dependent loss in the transmission media. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 9 DS125RT410 SNLS459 – APRIL 2011 www.ti.com The CTLE is a four-stage variable boost high-gain amplifier with a quasi-high-pass characteristic. Each of the four stages can be set to provide various amounts of high-frequency boost with the overall transfer function of the CTLE set by the cascade of all four sections. The high-frequency boost of each CTLE stage is variable. The optimum boost for each stage is one that causes the transfer function magnitude of the transmission channel and the CTLE in cascade to be flat over a band of frequencies extending up to half the data rate which is commonly referred to as the “Nyquist” frequency. In normal operation, the DS125RT410 sets the boost of the CTLE automatically to approximate the optimum cascaded response. Clock and Data Recovery The DS125RT410 performs its clock and data recovery function by detecting the bit transitions in the incoming data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit transitions. This process produces a recovered clock with greatly reduced jitter at jitter frequencies outside the bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the DS125RT410 in a system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the system. The DS125RT410 uses the 25 MHz reference to determine the coarse tuning setting for its internal VCO. On power-up, on CDR reset, and when the DS125RT410 loses lock and cannot re-acquire lock after four attempts, the 25 MHz reference is used to calibrate the VCO frequency. The required VCO frequency is set by using the rate/subrate settings (see Table 1) or by manually setting the PPM count and divide ratio. To calibrate the VCO frequency, the DS125RT410 searches through the available VCO coarse tuning settings and counts the divided VCO frequency using the 25 MHz reference as a clock source. The VCO coarse tuning setting which provides the VCO frequency closest to the required frequency is stored, and this coarse tuning setting is used for subsequent operation. This produces a fast, robust phase lock to the input signal. Output Driver The DS125RT410 is commonly used in applications where lossy transmission media exist both at the input and the output of the DS125RT410. The CTLE compensates for lossy transmission media at the input to the DS125RT410. The output de-emphasis compensates for the lossy transmission media at the output of the DS125RT410. When there is a transition in the output data stream, the output differential voltage reaches its configured maximum value within the configured rise/fall time of the output driver. Following this, the differential voltage rapidly falls off until it reaches the configured VOD level minus the configured de-emphasis level. This accentuates the high-frequency components of the output driver signal at the expense of the low-frequency components. This pre-distorted signal, with its high-frequency components emphasized relative to its lowfrequency components, travels down the dispersive transmission media at the output of the DS125RT410 with less inter-symbol interference than an undistorted signal would exhibit. The output driver is capable of driving variable output voltages with variable amounts of analog de-emphasis. The output voltage and de-emphasis level can be configured by writing registers over the SMBus. The DS125RT410 cannot determine independently the appropriate output voltage or de-emphasis setting, so the user is responsible for configuring these parameters. They can be set for each channel independently. An idealized transmit waveform with analog de-emphasis applied is shown in Figure 2. 1.0 VOD (V) 0.5 0.0 -0.5 -1.0 0 1 2 3 4 5 6 TIME (UI) 7 8 9 10 Figure 2. Idealized De-Emphasis Waveform 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 DEVICE CONFIGURATION The DS125RT410 can be configured by the user to optimize its operation. The four channels can be optimized independently in SMBus master or SMBus slave mode. The operational settings available for user configuration include the following. • CTLE boost setting • Rate and subrate setting • Driver output voltage • Driver output de-emphasis • Driver output rise/fall time CTLE Boost Setting The CTLE is a four-stage amplifier with an adjustable, quasi-high-pass transfer function on each stage. The overall frequency response of the CTLE is set by adjusting the boost of each stage independently. Each stage of the CTLE can be set to one of four boost settings. The amount of high-frequency boost supplied by each stage generally increases with increasing boost settings. The CTLE can also be configured to adapt automatically to provide the optimum boost level for its input signal. Automatic adaptation of the CTLE only is the default mode of operation for the DS125RT410. Rate and Subrate Setting Register 0x2f, bits 7:4, Registers 0x60, 0x61, 0x62, 0x63, and 0x64 The DS125RT410 is part of a family of retimer devices differentiated by different VCO frequency ranges. Each device in the retimer family is designed for operation in specific frequency bands and with specific data rate standards. The DS125RT410 is designed to lock rapidly to any valid signal present at its inputs. It is also designed to detect incorrect lock conditions which can arise when the input data signals are strongly periodic. This condition is referred to as “false lock”. The DS125RT410 discriminates against false lock by using its 25 MHz reference to ensure that the VCO frequency resulting from its internal phase-locking process is correct. To determine the correct VCO frequency, the digital circuitry in the DS125RT410 requires some user-supplied information about the expected data rate or data rates. This information is provided by writing several device register using the SMBus. Standards-Based Modes The DS125RT410 is designed to automatically operate with various multi-band data standards. The first set of register writes constrain the coarse VCO tuning and the VCO divider ratios. When these registers are set as indicated in Table 1, the DS125RT410 restricts its coarse VCO tuning to a set of coarse tuning values. It also restricts the VCO divider ratio to the set of divider ratios required to cover the frequency bands for the desired data rate standard. This enables the DS125RT410 to acquire phase lock more quickly than would be possible if the coarse tuning range were unrestricted. Table 1. Rate and Subrate Values versus Standards and Data Rates Standards Data Rates (Gb/s) VCO Frequencies (GHz) Divider Ratios Register 0x2F Value (hex) CPRI1 2.4576, 4.9152, 9.8304 9.8304 1, 2, 4 0x34 CPRI2 3.072, 6.144 12.288 2, 4 0x44 PROP3 6.25 12.5 2 0xA4 Interlaken1 3.125, 6.25 12.5 2, 4 0xB4 Interlaken2 10.3125 10.3125 1 0xC4 Ethernet 1.25, 10.3125 10.0, 10.3125 1, 8 0xF4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 11 DS125RT410 SNLS459 – APRIL 2011 www.ti.com As an example of the usage of the registers in Table 1, assume that the retimer is required to operate in 10 GbE or 1GbE mode. By setting register 0x2f, bits 7:4, to 4'b1111, the DS125RT410 will automatically set its divider ratio and its coarse VCO tuning setting to lock to either a 10 GbE signal (at 10.3125 Gb/s) or a 1 GbE signal (at 1.25 Gb/s) at its input. For the some standards shown in the table above, the required VCO frequency is the same for each data rate in the standard. Only the divider ratios are different. The retimer can automatically switch between the required divider ratios with a single set of register settings. For other data rates, it is also necessary to set the expected PPM count and the PPM count tolerance. These are the values the retimer uses to detect a valid frequency lock. For the 10 GbE and 1 GbE mode shown in the table above, two frequency groups are defined. These two frequency groups are referred to as “Group 0”, for 1 GbE, and “Group 1”, for 10 GbE. This same frequency group structure is present for all frequency modes, but for some modes the expected frequency for both groups is the same. The expected PPM count information for Group 0 is set in registers 0x60 and 0x61. For Group 1, it is set in registers 0x62 and 0x63. For both groups, the PPM count tolerance is set in register 0x64. The value of the PPM count for either group is computed the same way from the expected data rate in Gbps, RGbps. The PPM count value, denoted NPPM, is computed by NPPM = RGbps X 1280. As an example we consider the PPM count setup for 10 GbE and 1 GbE. The expected PPM count for Group 0, which in this case is 1 GbE, is set in registers 0x60 and 0x61. The expected VCO frequency for 1 G is 10.0 G. The actual data rate for 1 GbE, which is 8B/10B coded, is 1.25 Gbps. With a VCO divide ratio of 8, which is the divide ratio automatically used by the retimer for 1 GbE, this yields a VCO frequency of 10.0 GHz. We compute the PPM count as NPPM = 10.0 X 1280 = 12,800. This is a decimal value. In hexadecimal, this is 0x3200. The lower-order byte is loaded into register 0x60. The higher order byte, 0x32, is loaded into the 7 least significant bits of register 0x61. In addition, bit 7 of register 0x61 is set, indicating manual load of the PPM count. When this is complete, register 0x60 will contain 0x00. Register 0x61 will contain 0xb2. For the example we are considering, Group 1 is for 10 GbE. Here the actual data rate for the 64/66B encoded 10 GbE data is 10.3125 Gbps. For 10 GbE, the retimer automatically uses a divide ratio of 1, so the VCO frequency is also 10.3125 GHz. For 10 GbE, we compute the expected PPM count as NPPM = 10.3125 X 1280 = 13,200. Again, this is a decimal value. In hexadecimal, this is 0x3390. The lower order byte for Group 1, 0x90, is loaded into register 0x62. The higher-order byte, 0x33, is loaded into the 7 least-significant bits of register 0x63. As with the Group 0 settings, bit 7 of register 0x63 is also set. When this is complete, register 0x62 will contain 0x90. Register 0x63 will contain 0xb3. Finally, register 0x64 should be set to a value of 0xff. This is the PPM count tolerance. The resulting tolerance in parts per million is given by TolPPM = (1 X 10^-6 X NTOL) / NPPM. In this equation, NTOL is the 4-bit tolerance value loaded into the upper or lower four bits of register 0x64. For the example we are using here, both of these values are 0xf, or decimal 15. For a PPM count value of 12,800, for Group 0, this yields a tolerance of 1172 parts per million. For a PPM count value of 13,200, for Group 1, this yields a tolerance of 1136 parts per million. These tolerance values can be reduced if it is known that the frequency accuracy of the system and of the 25 MHz reference clock are very good. For most applications, however, a value of 0xff in register 0x64 will give robust performance. For all the other standards shown in Table 1 the expected PPM count for Group 0 (registers 0x60 and 0x61) and Group 1 (registers 0x62 and 0x63) will be set the same, since there is only one VCO frequency for these standards. The expected PPM count and tolerance are computed as described above for 10 GbE and 1 GbE. The same values are written to each pair of PPM count registers for these standards. As is the case with the standards-based mode of operation, the expected PPM count value and the PPM count tolerance must be written to registers 0x60, 0x61, 0x62, 0x63, and 0x64. These are computed exactly as described above for the standards-based mode of operation. Since the frequency-range-based mode of operation uses both Group 0 and Group 1 with the same expected PPM count, the same values should be loaded into the pairs of registers 0x60 and 0x62, and 0x61 and 0x63. 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 As an example, suppose that the expected data rate is 8.5 Gbps. The VCO frequency for the frequencyrangebased mode of operation is also 8.5 GHz. So we compute NPPM = 8.5 X 1280 = 10,880. This is a decimal value. In hexadecimal this is 0x2a80. We write the lower-order byte, 0x80 into registers 0x60 and 0x62. We write the higher order byte, 0x2a, into the least-significant 7 bits of registers 0x61 and 0x63. We also set bit 7 of registers 0x61 and 0x63. When this operation is complete, registers 0x60 and 0x62 will contain a value of 0x80. Registers 0x61 and 0x63 will contain a value of 0xaa. We also write the PPM tolerance into both the upper and lower four bits of register 0x64. If we write this register to a value of 0xff, then the PPM count tolerance in parts per million will be given by TolPPM = (1 X 10^-6 X NTOL) / NPPM = 1379 parts per million. This value will be appropriate for most systems. In summary, for data rates that correspond to the pre-defined standards for the DS125RT410, the standardsbased mode of operation can be used. This mode offers automatic switching of the divide ratio (and, for 10 GbE and 1 GbE, the VCO frequency) to easily accommodate operation over harmonically-related data rates. For data rates that are not covered by the pre-defined standards, the frequency-range-based mode of operation can be used. This mode works with a fixed divider ratio, which is nominally 1. However, the divider ratio can be forced to other values if desired. The register configuration procedure is as follow: 1. Select the desired channel of the DS125RT410 by writing the appropriate value to register 0xff. 2. Set bits 5:4 of register 0x36 to a value of 2'b11 as described above to enable the 25 MHz reference clock. 3. Write registers 0x2f with the correct values. 4. Compute the expected PPM count values for Group 0 and Group 1 as described above. 5. Write the expected PPM count values into registers 0x60-0x63 as described above, setting bit 7 of both registers 0x61 and 0x63. 6. Set the value 0xff into register 0x64 for an approximate PPM count tolerance of 1100-1400 PPM. 7. Reset the retimer CDR by setting and then clearing bits 3:2 of register 0x0a. If there is a signal at the correct data rate present at the input to the DS125RT410, the retimer will lock to it. In ref_mode 3, bits 5:4 of register 0x36 are set to 2'b11, it is not necessary to set the CAP DAC values the DS125RT410 determines the correct CAP DAC values automatically. Because it is not necessary to set the CAP DAC values for Group 0 and Group 1 a-priori in ref_mode 3, the DS125RT410 can be set up to use automatically switching divider ratios and arbitrary VCO frequencies in this mode. The mapping of values in register 0x2f, bits 7:4, versus the divider ratios used for each of the two groups is shown in Table 2. Table 2. Divider Ratio Settings versus Register 0x2f Setting Register 0x2f, Bits 7:4 Divider Ratio Group 0 Divider Ratio Group 1 4'b0011 1, 2, 4 1, 2, 4 4'b0100 2, 4 2, 4 4'b0110 1, 2, 4, 8 1, 2, 4, 8 4'b1010 2 2 4'b1011 2, 4 2, 4 4'b1100 1 1 4'b1111 8 1 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 13 DS125RT410 SNLS459 – APRIL 2011 www.ti.com Note that for the entries in Table 2 where the divider ratios are the same for the two groups, the expected PPM count for the two groups does not have to be the same. Therefore, in ref_mode 3, a single set of register settings can be used to specify multiple VCO frequencies either with the same divider ratio or with different divider ratios. Ref_mode 3 Mode (reference clock required) Ref_mode 3 requires an external 25 MHz clock. This mode of operation is set in register 0x36 bits [5:4] = 2'b11 and is the default setting. In ref_mode 3, the external reference clock is used to aid initial phase lock, and to determine when its VCO is properly phase-locked. An external oscillator should be used to generate a 2.5V, 25 MHz reference signal which is connected to the DS125RT410 on the reference clock input pin (pin 19). The DS125RT410 does not include a crystal oscillator circuit, so a stand-alone external oscillator is required. The reference clock speeds up the initial phase lock acquisition. The DS125RT410 is set to phase lock to a known data rate, or a constrained set of known data rates, and the digital circuitry in the DS125RT410 preconfigures the VCO frequency. This enables the DS125RT410 phase-lock to the incoming signal very quickly. The reference clock is used to calibrate the VCO coarse tuning. However, the reference clock is not synchronous to the data stream, and the quality of the reference clock does not affect the jitter on the output retimed data. The retimed data clock for each channel is synchronous to the VCO internal to that channel of the DS125RT410. The phase noise of the reference clock is not critical. Any commercially-available 25 MHz oscillator can provide an acceptable reference clock. The reference clock can be daisy-chained from one retimer to another so that only one reference oscillator is required in a system. False Lock Detector Setting The register 0x2F, bit 1 is set to 1 by default, which disables the false lock detector. This bit must be set to 0 to enable the false lock detector function. Reference Clock In REFCLK_IN pin 19 is for reference clock input. A 25 MHz oscillator should be connected to pin 19. See Electrical Characteristics for the requirements on the 25 MHz clock. The frequency of the reference clock should always be 25 MHz no matter what data rate or mode of operation is used. Reference Clock Out REFCLK_OUT pin 42 is the reference clock output pin. The DS125RT410 drives a buffered replica of the 25 MHz reference clock input on this output pin. If there are multiple DS125RT410 in the system, the REFCLK_OUT pin can be directly connected to the REFCLK_IN pin of another DS125RT410 in a daisy chain connection. The other option is to connect the external 25 MHz oscillator to a clock fanout buffer to distribute the 25 MHz clock to each DS125RT410, which ensures there is a reference clock for the DS125RT410. Driver Output Voltage The differential output voltage of the DS125RT410 can be configured from a nominal setting of 600 mV peak-topeak differential to a nominal setting of 1.3 V peak-to-peak differential, depending upon the application. The driver output voltage as set is the typical peak-to-peak differential output voltage with no de-emphasis enabled. Driver Output De-Emphasis The output de-emphasis level of the DS125RT410 can be configured from a nominal setting of 0 dB to a nominal setting of -15 dB depending upon the application. Larger absolute values of the de-emphasis setting provide more pre-distortion of the output driver waveform, accentuating the high-frequency components of the output driver waveform relative to the low-frequency components. Greater values of de-emphasis can compensate for greater dispersion in the transmission media at the output of the DS125RT410. The output de-emphasis level as set is the typical value to which the output signal will settle following the de-emphasis pulse interval in dB relative to the output VOD. Driver Output Rise/Fall Time In some applications, a longer rise/fall time for the output signal is desired. This can reduce electromagnetic interference (EMI) generated by fast switching waveforms. This is necessary in some applications for regulatory compliance. In others, it can reduce the crosstalk in the system. 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 The DS125RT410 can be configured to operate with a nominal rise/fall time corresponding to the maximum slew rate of the output drivers into the load capacitance. Alternatively, the DS125RT410 can be configured to operate with a slightly greater rise/fall time if desired. For the typical specifications on rise/fall time, see Electrical Characteristics INT The INT line is an open-drain, 3.3V tolerant, LVCMOS active-low output. The INT lines from multiple DS125RT410s can be wired together and connected to an external controller. The Horizontal Eye Opening/Vertical Eye Opening (HEO/VEO) interrupt can be enabled using SMBus control for each channel independently. This interrupt is disabled by default. The thresholds for horizontal and vertical eye opening that will trigger the interrupt can be set using the SMBus control for each channel. If any interrupt occurs, registers in the DS125RT410 latch in information about the event that caused the interrupt. This can then be read out by the controller over the SMBus. LOCK_3, LOCK_2, LOCK_1, and LOCK_0 Each channel of the DS125RT410 has an independent lock indication pin. These lock indication pins, LOCK_3, LOCK_2, LOCK_1, and LOCK_0, are pin 16, pin 21, pin 40, and pin 45 respectively. These pins are shared with the SMBus address strap lines. After the address values have been latched in on power-up, these lines revert to their lock indication function. When the corresponding channel of the DS125RT410 is locked to the incoming data stream, the lock indication pin goes high. This pin can be used to drive an LED on the board, giving a visual indication of the lock status, or it can be connected to other circuitry which can interpret the lock status of the channel. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 15 DS125RT410 SNLS459 – APRIL 2011 www.ti.com DEVICE CONFIGURATION MODES The DS125RT410 can be configured using two different methods. • SMBus Master Configuration Mode • SMBus Slave Configuration Mode The configuration mode is selected by the state of the SMBus Enable pin (pin 20) when the DS125RT410 is powered-up. This pin should be either left floating or tied to the device VDD through an optional 1KΩ resistor. The effect of each of these settings is shown in Table 3. Table 3. SMBus Enable Settings Pin Setting Configuration Mode Description READ_EN Pin Float SMBus Master Mode Device reads its configuration from an external EEPROM on power-up. Pull low to initiate reading configuration data from external EEPROM High (1) SMBus Slave Mode Device is configured over the SMBus by an external controller. Tie low to enable proper address strapping on power-up SMBus Master Mode and SMBus Slave Mode In SMBus master mode the DS125RT410 reads its initial configuration from an external EEPROM upon powerup. A description of the operation of this mode appears in a separate application note. Some of the pins of the DS125RT410 perform the same functions in SMBus master and SMBus slave mode. Once the DS125RT410 has finished reading its initial configuration from the external EEPROM in SMBus master mode it reverts to SMBus slave mode and can be further configured by an external controller over the SMBus. There are two pins that provide unique functions in SMBus master mode. These are as follows: • ALL_DONE • READ_EN These pins are meant to work together. When the DS125RT410 is powered up in SMBus master mode, it reads its configuration from the external EEPROM when the READ_EN pin goes low. When the DS125RT410 is finished reading its configuration from the external EEPROM, it drives its ALL_DONE pin low. After the DS100RT410 has finished reading its configuration from the EEPROM, it releases control of the SMBus and becomes a SMBus slave. In applications where there is more than one DS125RT410 on the same SMBus, bus contention can result if more than one DS125RT410 tries to take command of the SMBus at the same time. The READ_EN and ALL_DONE pins prevent this bus contention. The system should be designed so that the READ_EN pin of one of the DS125RT410s in the system is driven low on power-up. This DS125RT410 will take command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When it is finished reading its configuration, it will set its ALL_DONE pin low. This pin should be connected to the READ_EN pin of another DS125RT410. When this DS125RT410 senses its READ_EN pin driven low, it will take command of the SMBus and read its initial configuration from the external EEPROM, after which it will set its ALL_DONE pin low. By connecting the ALL_DONE pin of each DS125RT410 to the READ_EN pin of the next DS125RT410, each DS125RT410 can read its initial configuration from the EEPROM without causing bus contention. For SMBus slave mode, the READ_EN pin must be tied low. Do not leave it floating or tie it high. A connection diagram showing several DS125RT410s along with an external EEPROM and an external SMBus master is shown in Figure 3 below. The SMBus master must be prevented from trying to take control of the SMBus until the DS125RT410s have finished reading their initial configurations from the EEPROM. 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 SDA From External SMBus Master SDC ALL_DONE_N SDA ADDR3 READ_EN_N ADDR2 ADDR1 ADDR0 ADDR3 ADDR2 ADDR1 ADDR0 READ_EN_N ADDR2 ADDR1 ADDR0 Set to unique SMBus address Set to unique SMBus address ALL_DONE_N SDA SDC ALL_DONE_N SDA SDC ALL_DONE_N SDA SDC DS125RT410 DS125RT410 DS125RT410 ADDR3 READ_EN_N ADDR1 ADDR2 Set to unique SMBus address ADDR0 ADDR3 READ_EN_N ADDR1 ADDR2 ADDR0 ADDR3 READ_EN_N ADDR2 ADDR1 ADDR0 Set to unique SMBus address DS125RT410 DS125RT410 One or both of these lines should float for an EEPROM larger than 256 bytes SDC ALL_DONE_N SDA SDC SDC SDA EEPROM Set to unique SMBus address Figure 3. Connection Diagram for Multiple DS125RT410s in SMBus Master Mode In SMBus master mode after the DS125RT410 has finished reading its initial configuration from the external EEPROM it reverts to SMBus slave mode. In either mode the SMBus data and clock lines, SDA and SDC, are used. Also, in either mode, the SMBus address is latched in on the address strap lines on power-up. In SMBus slave mode, if the READ_EN pin is not tied low, the DS125RT410 will not latch in the address on its address strap lines. It will instead latch in an SMBus write address of 0x30 regardless of the state of the address strap lines. This is a test feature. Obviously a system with multiple retimers cannot operate properly if all the retimers are responding to the same SMBus address. Tie the READ_EN pin low when operating in SMBus slave mode to avoid this condition. The DS125RT410 reads its SMBus address upon power-up from the SMBus address lines. Address Lines <ADDR_[3:0]> In either SMBus master or SMBus slave mode the DS125RT410 must be assigned an SMBus address. A unique address should be assigned to each device on the SMBus. The SMBus address is latched into the DS125RT410 on power-up. The address is read in from the state of the <AD3:AD0> lines (pins 16, 21, 40, and 45 respectively) upon power-up. In either SMBus mode these address lines are input pins on power-up. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 17 DS125RT410 SNLS459 – APRIL 2011 www.ti.com The DS125RT410 can be configured with any of 16 SMBus addresses. The SMBus addressing scheme uses the least-significant bit of the SMBus address as the Read/Write_N address bit. When an SMBus device is addressed for writing, this bit is set to 0; for reading, to 1. Table 4 below shows the write address setting for the DS125RT410 versus the values latched in on the address lines at power-up. The address byte sent by the SMBus master over the SMBus is always 8 bits long. The least-significant bit indicates whether the address is for a write operation, in which the master will output data to the SMBus to be read by the slave, or a read operation, in which the slave will output data to the SMBus to be read by the master. if the least-significant bit is a 0, the address is for a write operation. If it is a 1, the address is for a read operation. Accordingly, SMBus addresses are sometimes referred to as seven-bit addresses. To produce the write address for the SMBus, the seven-bit address is left-shifted by one bit. To produce the read address, it is left shifted by one bit and the least-significant bit is set to 1. Table 4 shows the seven-bit addresses corresponding to each set of address line values. When the DS125RT410 is used in SMBus slave mode, the READ_EN pin must be tied low. If it is tied high or floating, the DS125RT410 will not latch in its address from the address lines on power-up. When the READ_EN pin is tied high in SMBus slave mode i.e. when the EN_SMB pin (pin 20) is tied high, the DS125RT410 will revert to an SMBus write address of 0x30. This is a test feature. If there are multiple DS125RT410s on the same SMBus, they will all revert to an SMBus write address of 0x30, which can cause SMBus collisions and failure to access the DS125RT410s over the SMBus. Table 4. DS125RT410 SMBus Write Address Assignment ADDR_3 ADDR_2 ADDR_1 ADDR_0 SMBus Write Address Seven-bit SMBus Address 0 0 0 0 0x30 0x18 0 0 0 1 0x32 0x19 0 0 1 0 0x34 0x1a 0 0 1 1 0x36 0x1b 0 1 0 0 0x38 0x1c 0 1 0 1 0x3a 0x1d 0 1 1 0 0x3c 0x1e 0 1 1 1 0x3e 0x1f 1 0 0 0 0x40 0x20 1 0 0 1 0x42 0x21 1 0 1 0 0x44 0x22 1 0 1 1 0x46 0x23 1 1 0 0 0x48 0x24 1 1 0 1 0x4a 0x25 1 1 1 0 0x4c 0x26 1 1 1 1 0x4e 0x27 Once the DS125RT410 has latched in its SMBus address, its registers can be read and written using the two pins of the SMBus interface, Serial Data (SDA) and Serial Data Clock (SDC). SDA and SDC In both SMBus master and SMBus slave mode, the DS125RT410 is configured using the SMBus. The SMBus consists of two lines, the SDA or serial data line (pin 18) and the SDC or serial clock line (pin 17). In the DS125RT410 these pins are 3.3V tolerant. The SDA and SDC lines are both open-drain. They require a pull-up resistor to a supply voltage, which may be either 2.5V or 3.3V. A pull-up resistor in the 2KΩ to 5KΩ range will provide reliable SMBus operation. The SMBus is a standard communications bus for configuring simple systems. For a specification of the SMBus an description of its operation, see http://smbus.org/specs/. 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 REGISTER INFORMATION There are two types of device registers in the DS125RT410. These are the control/shared registers and the channel registers. The control/shared registers control or allow observation of settings which affect the operation of all channels of the DS125RT410. They are also used to select which channel of the device is to be the target channel for reads from and writes to the channel registers. The channel registers are used to set all the configuration settings of the DS125RT410. They provide independent control for each channel of the DS125RT410 for all the settable device characteristics. Any registers not described in the tables that follow should be treated as reserved. The user should not try to write new values to these registers. The user-accessible registers described in the tables that follow provide a complete capability for customizing the operation of the DS125RT410 on a channel-by-channel basis. Bit Fields in the Register Set Many of the registers in the DS125RT410 are divided into bit fields. This allows a single register to serve multiple purposes, which may be unrelated. Often configuring the DS125RT410 requires writing a bit field that makes up only part of a register value while leaving the remainder of the register value unchanged. The procedure for accomplishing this is to read in the current value of the register to be written, modify only the desired bits in this value, and write the modified value back to the register. Of course, if the entire register is to be changed, rather than just a bit field within the register, it is not necessary to read in the current value of the register first. In all the register configuration procedures described in the following sections, this procedure should be kept in mind. In some cases, the entire register is to be modified. When only a part of the register is to be changed, however, the procedure described above should be used. Writing to and Reading from the Control/Shared Registers Any write operation targeting register 0xff writes to the control/shared register 0xff. This is the only register in the DS125RT410 with an address of 0xff. Bit 2 of register 0xff is used to select either the control/shared register set or a channel register set. If bit 2 of register 0xff is cleared (written with a 0), then all subsequent read and write operations over the SMBus are directed to the control/shared register set. This situation persists until bit 2 of register 0xff is set (written with a 1). There is a register with address 0x00 in the control/shared register set, and there is also a register with address 0x00 in each channel register set. If you read the value in register 0x00 when bit 2 of register 0xff is cleared to 0, then the value returned by the DS125RT410 is the value in register 0x00 of the control/shared register set. If you read the value in register 0x00 when bit 2 of register 0xff is set to 1, then the value returned by the DS125RT410 is the value in register 0x00 of the selected channel register set. The channel register set is selected by bits 1:0 of register 0xff. If bit 3 of register 0xff is set to 1 and bit 2 of register 0xff is also set to 1, then any write operation to any register address will write all the channel register sets in the DS125RT410 simultaneously. This situation will persist until either bit 3 of register 0xff or bit 2 of register 0xff is cleared. Note that when you write to register 0xff, independent of the current settings in register 0xff, the write operation ALWAYS targets the control/shared register 0xff. This channel select register, register 0xff, is unique in this regard. Table 5 below shows the control/shared register set. Any register addresses or register bits in the control/shared register set not shown in this table should be considered reserved. In this table, the mode is either R for ReadOnly, R/W for Read-Write, or R/W/SC for Read-Write-Self-Clearing. If you try to write to a Read-Only register, the DS125RT410 will ignore it. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 19 DS125RT410 SNLS459 – APRIL 2011 www.ti.com Table 5. Control/Shared Registers Address (Hex) Bits Default Value (Hex) Mode Description 0x00 7:4 0x0 R SMBus Address Strap Observation <3:0> 0x01 7:5 0x6 R Device Revision 4:0 0x11 R Device ID 6 0x0 R/W/SC Self-Clearing Reset for Control/Shared Registers 5 0x0 R/W Reset for SMBus Master Mode 4 0x0 R/W Force EEPROM Configuration 7 0x0 R/W Disable Master Mode EEPROM Configuration 4 (1) R EEPROM Read Complete 3 0x0 R Set on Channel 0 Interrupt 2 0x0 R Set on Channel 1 Interrupt 1 0x0 R Set on Channel 2 Interrupt 0x04 0x05 0 0x0 R Set on Channel 3 Interrupt 0x06 3:0 0X0 R/W Diagnostic Test Control Set to 0xa to read SMBus strap values from register 0x00 0xff 3 0x0 R/W Selects All Channels for Register Write See Table 6 2 0x0 R/W Enables Register Write to One or All Channels and Register Read from One Channel See Table 6 1:0 0x0 R/W Selects Target Channel for Register Reads and Writes See Table 6 (1) There is no default value. This bit always indicates whether the EEPROM read is complete or not. SMBus Strap Observation Register 0x00, bits 7:4 and register 0x06, bits 3:0 In order to communicate with the DS125RT410 over the SMBus, it is necessary for the SMBus controller to know the address of the DS125RT410 . The address strap observation bits in control/shared register 0x00 are primarily useful as a test of SMBus operation. There is no way to get the DS125RT410 to tell you what its SMBus address is unless you already know what it is. In order to use the address strap observation bits of control/shared register 0x00, it is necessary first to set the diagnostic test control bits of control/shared register 0x06. This four-bit field should be written with a value of 0xa. When this value is written to bits 3:0 of control/shared register 0x06, then the value of the SMBus address straps can be read in register 0x00, bits 7:4. The value read will be the same as the value present on the ADDR3:ADDR0 lines when the DS125RT410 was powered up. For example, if a value of 0x1 is read from control/shared register 0x00, bits 7:4, then at power-up the ADDR0 line was set to 1 and the other address lines, ADDR3:ADDR1, were all set to 0. The DS125RT410 is set to an SMBus Write address of 0x32. 20 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 Device Revision and Device ID Register 0x01 Control/shared register 0x01 contains the device revision and device ID. The device revision shown in Table 5 is the current revision for the DS125RT410. The device ID will be different for the different devices in the retimer family. This register is useful because it can be interrogated by software to determine the device variant and revision installed in a particular system. The software might then configure the device with appropriate settings depending upon the device variant and revision. Control/Shared Register Reset Register 0x04, bit 6 Register 0x04, bit 6, clears all the control/shared registers back to their factory defaults. This bit is self-clearing, so it is cleared after it is written and the control/shared registers are reset to their factory default values. Interrupt Channel Flag Bits Register 0x05, bits 3:0 The operation of these bits is described in the section on interrupt handling later in this data sheet. SMBus Master Mode Control Bits Register 0x04, bits 5 and 4 and register 0x05, bits 7 and 4 Register 0x04, bit 5, can be used to reset the SMBus master mode. This bit should not be set if the DS125RT410 is in SMBus slave mode. This is an undefined condition. When this bit is set, if the EN_SMB pin is floating (meaning that the DS125RT410 is in SMBus master mode), then the DS125RT410 will read the contents of the external EEPROM when the READ_EN pin is pulled low. This bit is not self-clearing, so it should be cleared after it is set. When the DS125RT410 EN_SMB pin is floating (meaning that the DS125RT410 is in SMBus master mode), it will read from its external EEPROM when its READ_EN pin goes low. After the EEPROM read operation is complete, register 0x05, bit 4 will be set. Alternatively, the DS125RT410 will read from its external EEPROM when triggered by register 0x04, bit 4, as described below. When register 0x04, bit 4, is set, the DS125RT410 reads its configuration from an external EEPROM over the SMBus immediately. When this bit is set, the DS125RT410 does not wait until the READ_EN pin is pulled low to read from the EEPROM. This EEPROM read occurs whether the DS125RT410 is in SMBus master mode or not. If the read from the EEPROM is not successful, for example because there is no EEPROM present, then the DS125RT410 may hang up and a power-up reset may be necessary to return it to proper operation. You should only set this bit if you know that the EEPROM is present and properly configured. If the EEPROM read has already completed, then setting register 0x04, bit 4, will not have any effect. To cause the DS125RT410 to read from the EEPROM again it is necessary to set bit 5 of register 0x04, resetting the SMBus master mode. If the DS125RT410 is not in SMBus master mode, do not set this bit. After setting this bit, it should be cleared before further SMBus operations. After SMBus master mode has been reset, the EEPROM read may be initiated either by pulling the READ_EN pin low or by then setting register 0x04, bit 4. Register 0x05, bit 7, disables SMBus master mode. This prevents the DS125RT410 from trying to take command of the SMBus to read from the external EEPROM. Obviously this bit will have no effect if the EEPROM read has already taken place. It also has no effect if an EEPROM read is currently in progress. The only situations in which disabling EEPROM master mode read is valid are (1) when the DS125RT410 is in SMBus master mode, but the READ_EN pin has not yet gone low, and (2) when register 0x04, bit 5, has been used to reset SMBus master mode but the EEPROM read operation has not yet occurred. Do not set this bit and bit 4 of register 0x04 simultaneously. This is an undefined condition and can cause the DS125RT410 to hang up. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 21 DS125RT410 SNLS459 – APRIL 2011 www.ti.com Channel Select Register Register 0xff, bits 3:0 Register 0xff, as described above, selects the channel or channels for channel register reads and writes. It is worth describing the operation of this register again for clarity. If bit 3 of register 0xff is set, then any channel register write applies to all channels. Channel register read operations always target only the channel specified in bits 1:0 of register 0xff regardless of the state of bit 3 of register 0xff. Read and write operations target the channel register sets only when bit 2 of register 0xff is set. Bit 2 of register 0xff is the universal channel register enable. This bit must be set in order for any channel register reads and writes to occur. If this bit is set, then read operations from or write operations to register 0x00, for example, target channel register 0x00 for the selected channel rather than the control/shared register 0x00. In order to access the control/shared registers again, bit 2 of register 0xff should be cleared. Then the control/shared registers can again be accessed using the SMBus. Write operations to register 0xff always target the register with address 0xff in the control/shared register set. There is no other register, and specifically, no channel register, with address 0xff. The contents of the channel select register, register 0xff, cannot be read back over the SMBus. Read operations on this register will always yield an invalid result. All eight bits of this register should always be set to the desired values whenever this register is written. Always write 0x0 to the four MSBs of register 0xff. The register set target selected by each valid value written to the channel select register is shown in Table 6 Table 6. Channel Select Register Values Mapped to Register Set Target Register 0xff Value (hex) Shared/Channel Register Selection Broadcast Channel Register Selection Targeted Channel Selection Comments 0x00 Shared N/A N/A All reads and writes target shared register set 0x04 Channel No 0 All reads and writes target channel 0 register set 0x05 Channel No 1 All reads and writes target channel 1 register set 0x06 Channel No 2 All reads and writes target channel 2 register set 0x07 Channel No 3 All reads and writes target channel 3 register set 0x0c Channel Yes 0 All writes target all channel register sets, all reads target channel 0 register set 0x0d Channel Yes 1 All writes target all channel register sets, all reads target channel 1 register set 0x0e Channel Yes 2 All writes target all channel register sets, all reads target channel 2 register set 0x0f Channel Yes 3 All writes target all channel register sets, all reads target channel 3 register set Reading to and Writing from the Channel Registers Each of the four channels has a complete set of channel registers associated with it. The channel registers or the control/shared registers are selected by channel select register 0xff. The settings in this register control the target for subsequent register reads and writes until the contents of register 0xff are explicitly changed by a register write to register 0xff. As noted, there is only one register with an address of 0xff, the channel select register. 22 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 Table 7. Channel Registers Address (Hex) Bits Default Value (Hex) Mode Field Name Description 0x00 2 0x0 R/W/SC rst_regs Reset Channel Registers to Defaults (Self-clearing) 0x01 4 0x0 R cdr_lock_loss_int CDR Lock Loss Interrupt 0 0x0 R signal_detect_loss_int Signal Detect Loss Interrupt 7:6 0x0 R/W eq_BST0[1:0] CTLE Boost Stage 0 <1:0> 5:4 0x0 R/W eq_BST1[1:0] CTLE Boost Stage 1 <1:0> 3:2 0x0 R/W eq_BST2[1:0] CTLE Boost Stage 2 <1:0> 1:0 0x0 R/W eq_BST3[1:0] CTLE Boost Stage 3 <1:0> 0x08 4:0 0x00 R/W cdr_cap_dac_start[4: 0] Override Starting VCO Cap DAC Setting 0 <4:0> 0x09 7 0x0 R/W reg_divsel_vco_cap_ ov Enable Override VCO Cap DAC (Registers 0x08 and 0x0b) 5 0x0 R/W reg_bypass_pfd_ov Enable Override Output Mux (Register 0x1e) 2 0x0 R/W reg_divsel_ov Enable Override Divider Select (Register 0x18) 3 0x0 R/W reg_cdr_reset_ov Enable CDR Reset Override (Register 0x0a) 2 0x0 R/W reg_cdr_reset_sm CDR Reset Override Bit 0x0b 4:0 0x0f R/W cdr_cap_dac_start1[4 Override VCO Cap :0] DAC Setting 1 <4:0> 0x0d 5 0x0 R/W PRBS_PATT_SHIFT_ PRBS Generator EN Clock Enable 0x11 7:6 0x0 R/W eom_sel_vrange[1:0] Eye Opening Monitor Voltage Range <1:0> 5 0x1 R/W eom_PD Eye Opening Monitor Power Down 0x13 2 0x0 RW eq_BST3[2] CTLE Boost Stage 3, Bit 2 (Limiting Bit) 0x14 7 0x0 R/W eq_sd_preset Force Signal Detect On 6 0x0 R/W eq_sd_reset Force Signal Detect Off 6 0x0 R/W drv_dem_range Driver De-emphasis Range 2:0 0x0 R/W drv_dem[2:0] Driver De-emphasis Setting<2:0> 6:4 0x4 R/W pdiq_sel_div[2:0] VCO Divider Ratio <2:0> (Enable from Register 0x09, Bit 2) 2 0x0 R/W drv_sel_slow Enable Slow Rise/Fall Time on Output Driver 0x03 0x0a 0x15 0x18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 23 DS125RT410 SNLS459 – APRIL 2011 www.ti.com Table 7. Channel Registers (continued) Address (Hex) Bits Default Value (Hex) Mode Field Name 0x1e 7:5 0x7 R/W pfd_sel_data_mux[2:0 OutputMux <2:0> ] (Enable from Register 0x09, Bit 5) 4 0x0 R/W prbs_en Enable PRBS Generator 0x1f 7 0x0 R/W drv_sel_inv Select Output Polarity Inverted 0x24 7 0x0 R/W fast_eom Enable Fast Eye Opening Monitor Mode 0 0x0 R/W/SC eom_start Start Eye Opening Monitor Counter (Self-Clearing) 0x25 7:0 0x0 R eom_count[15:8] Eye Opening Monitor Count <15:8> 0x26 7:0 0x0 R eom_count[7:0] Eye Opening Monitor Count <7:0> 0x27 7:0 0x0 R heo[7:0] HEO Value <7:0> 0x28 7:0 0x0 R veo[7:0] VEO Value <7:0> 0x29 6:5 0x0 R eom_vrange_setting[ 1:0] Eye Opening Monitor Voltage Range Setting <1:0> 0x2a 7:0 0x30 R/W eom_timer_thr[7:0] Eye Opening Monitor Timer Threshold <7:0> 0x2d 2:0 0x0 R/W drv_sel_vod[2:0] Driver VOD <2:0> 0x2f 7:6 0x0 R/W RATE[1:0] Rate <1:0> 5:4 0x0 R/W SUBRATE[1:0] Subrate <1:0> 3 0x0 R/W index_ov CTLE Adaptation Index Override (Register 0x13) 2 0x1 R/W en_ppm_check Enable Frequency Counter for Lock Detect 1 0x1 R/W en_fld_check False Lock Detector for lock detect is disabled by default. Must set bit to 0 to enable the FLD. 0 0x0 R/W ctle_adapt Start CTLE Adaptation 4 0x0 R heo_veo_interrupt Goes High if Interrupt from CDR Goes High 3 0x0 R/W prbs_en_dig_clk PRBS Generator Enable 1:0 0x0 R/W prbs_pattern_sel[1:0] PRBS Generator Pattern Select <1:0> 6:5 0x1 R/W adapt_mode[1:0] Adaptation Mode <1:0> 4:3 0x0 R/W eq_sm_fom[1:0] CTLE Adaptation Figure of Merit Type <1:0> 7:4 0x1 R/W heo_int_thresh[3:0] HEO Interrupt Threshold <3:0> 3:0 0x1 R/W veo_int_thresh[3:0] VEO Interrupt Threshold <3:0> 0x30 0x31 0x32 24 Submit Documentation Feedback Description Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 Table 7. Channel Registers (continued) Address (Hex) Bits Default Value (Hex) Mode Field Name Description 0x33 7:4 0x8 R/W heo_thresh[3:0] HEO Threshold for CTLE Adaptation Handoff 3:0 0x8 R/W veo_thresh[3:0] VEO Threshold for CTLE Adaptation Handoff 6 0x0 R/W heo_veo_int_enable Enable HEO/VEO Interrupt 5:4 0x3 R/W ref_mode[1:0] Reference Clock Mode <1:0> 2 0x0 R/W mr_cdr_cap_dac_rng _ov Enable Override for VCO Cap DAC Range 1:0 0x1 R/W mr_cdr_cap_dac_rng[ Cap DAC Range 1:0] <1:0> 0x39 4:0 0x0 R/W start_index[4:0] Start Index for CTLE Adaptation <4:0> (Enable from Register 0x2f, Bit 3) 0x3a 7:6 0x2 R/W fixed_eq_BST0[1:0] Fixed CTLE Stage 0 Boost Setting for Lower Data Rates <1:0> 5:4 0x2 R/W fixed_eq_BST1[1:0] Fixed CTLE Stage 1 Boost Setting for Lower Data Rates <1:0> 3:2 0x1 R/W fixed_eq_BST2[1:0] Fixed CTLE Stage 2 Boost Setting for Lower Data Rates <1:0> 1:0 0x1 R/W fixed_eq_BST3[1:0] Fixed CTLE Stage 3 Boost Setting for Lower Data Rates <1:0> 0x3e 7 0x1 R/W HEO_VEO_LOCKMO Enable HEO/VEO N_EN Lock Monitoring 0x40 – 0x5f CTLE Settings for Adaptation – see Table 14 0x6a 7:4 0x4 R/W veo_lck_thrsh[3:0] Vertical Eye Opening Lock Threshold <3:0> 3:0 0x4 R/W heo_lck_thrsh[3:0] Horizontal Eye Opening Lock Threshold <3:0> 0x6b 7:0 0x0 R/W fom_a[7:0] Adaptation Figure of Merit Term a<7:0> 0x6c 7:0 0x0 R/W fom_b[7:0] Adaptation Figure of Merit Term b<7:0> 0x6d 7:0 0x0 R/W fom_c[7:0] Adaptation Figure of Merit Term c<7:0> 0x6e 7 0x0 R/W en_new_fom_ctle Enable Alternate Figure of Merit for CTLE Adaptation 0x70 2:0 0x3 R/W eq_lb_cnt[2:0] CTLE Adaptation Look-Beyond Count <2:0> 0x36 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 25 DS125RT410 SNLS459 – APRIL 2011 www.ti.com Resetting Individual Channels of the Retimer Register 0x00, bit 2, and register 0x0a, bits 3:2 Bit 2 of channel register 0x00 are used to reset all the registers for the corresponding channel to their factory default settings. This bit is self-clearing. Writing this bit will clear any register changes you have made in the DS125RT410 since it was powered-up. To reset just the CDR state machine without resetting the register values, which will re-initiate the lock and adaptation sequence for a particular channel, use channel register 0x0a. Set bit 3 of this register to enable the reset override, then set bit 2 to force the CDR state machine into reset. These bits can be set in the same operation. When bit 2 is subsequently cleared, the CDR state machine will resume normal operation. If a signal is present at the input to the selected channel, the DS125RT410 will attempt to lock to it and will adapt its CTLE. Interrupt Status Control/Shared Register 0x05, bits 3:0, Register 0x01, bits 4 and 0, Register 0x30, bit 4, Register 0x32, and Register 0x36, bit 6 Each channel of the DS125RT410 will generate an interrupt under several different conditions. The DS125RT410 will always generate an interrupt when it loses CDR lock or when a signal is no longer detected at its input. If the HEO/VEO interrupt is enabled by setting bit 6 of register 0x36, then the retimer will generate an interrupt when the horizontal or vertical eye opening falls below the preset values even if the retimer remains locked. When one of these interrupt conditions occurs, the retimer alerts the system controller via hardware and provides additional details via register reads over the SMBus. First, the open-drain interrupt line INT is pulled low. This indicates that one or more of the channels of the retimer has generated an interrupt. The interrupt lines from multiple retimers can be wire-ANDed together so that if any retimer generates an interrupt the system controller can be notified using a single interrupt input. if the interrupt has occurred because the horizontal or vertical eye opening has dropped below the pre-set threshold, which is set in channel register 0x32, then bit 4 of register 0x30 will go high. This indicates that the source of the interrupt was the HEO or VEO. If the interrupt has occurred because the CDR has fallen out of lock, or because the signal is no longer detected at the input, then bit 4 and/or bit 0 of register 0x01 will go high, indicating the cause of the interrupt. In either case, the control/shared register set will indicate which channel caused the interrupt. This is read from bits 3:0 of control/shared register 0x05. When an interrupt is detected by the controller on the interrupt input, the controller should take the following steps to determine the cause of the interrupt and clear it. 1. The controller detects the interrupt by detecting that the INT line has been pulled low by one of the retimers to which it is connected. 2. The controller reads control/shared register 0x05 from all the DS125RT410s connected to the INT line. For at least one of these devices, at least one of the bits 3:0 will be set in this register. 3. For each device with a bit set in bits 3:0 of control/shared register 0x05, the controller determines which channel or channels produced an interrupt. Refer to Table 5 for a mapping of the bits in this bit field to the channel producing the interrupt. 4. When the controller detects that one of the retimers has a 1 in one of the four LSBs of this register, the controller selects the channel register set for that channel of that retimer by writing to the channel select register, 0xff, as previously described. 5. For each channel that generated an interrupt, the controller reads channel register 0x01. If bit 4 of this register is set, then the interrupt was caused by a loss of CDR lock. If bit 0 is set, then the interrupt was caused by a loss of signal. it is possible that both bits 0 and 4 could be set. Reading this register will clear these bits. 6. Optionally, for each channel that generated an interrupt, the controller reads channel register 0x30. If bit 4 of this register is set, then the interrupt was caused by HEO and/or VEO falling out of the configured range. This interrupt will only occur if bit 6 of channel register 0x36 is set, enabling the HEO/VEO interrupt. Reading register 0x30 will clear this interrupt bit. 7. Once the controller has determined what condition caused the interrupt, the controller can then take the appropriate action. For example, the controller might reset the CDR to cause the retimer to re-adapt to the incoming signal. If there is no longer an incoming signal (indicated by a loss of signal interrupt, bit 0 of 26 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 channel register 0x01), then the controller might alert an operator or change the channel configuration. This is system dependent. 8. Reading the interrupt status registers will clear the interrupt. if this does not cause the interrupt input to go high, then another device on the same input has generated an interrupt. The controller can address the next device using the procedure above. 9. Once all the interrupt registers for all channels for all DS125RT410s that generated interrupts have been read, clearing all the interrupt indications, the INT line should go high again. This indicates that all the existing interrupt conditions have been serviced. The channel registers referred to above, registers 0x01, 0x30, 0x32, and 0x36, are described in the channel registers table, Table 7. Overriding the CTLE Boost Setting Register 0x03, Register 0x13, bit 2, and Register 0x3a To override the CTLE boost settings, register 0x03 is used. This register contains the currently-applied CTLE boost settings. The boost values can be overridden by using the two-bit fields in this register as shown in the table. The final stage of the CTLE has an additional control bit which sets it to a limiting mode. For some channels, this additional setting improves the bit error rate performance. This bit is bit 2 of register 0x13. If the DS125RT410 loses lock because of a change in the CTLE settings, the DS125RT410 will initiate its lock and adaptation sequence again. Thus, if you write new CTLE boost values to register 0x03 and 0x13 which cause the DS125RT410 to drop out of lock, the DS125RT410 may, in the process of reacquiring the CDR lock, reset the CTLE settings to different values than those you set in register 0x03 and 0x13. If this behavior is not understood, it can appear that the DS125RT410 did not accept the values you wrote to the CTLE boost registers. What's really happening, however, is that the lock and adaptation sequence is overriding the CTLE values you wrote to the CTLE boost registers. This will not happen unless the DS125RT410 drops out of lock. if the adapt mode is set to 0 (bits 6:5 of channel register 0x31), then the CTLE boost values will not be overridden, but the DS125RT410 may still lose lock. If this happens, the DS125RT410 will attempt to reacquire lock. if the reference mode is set appropriately, and if the rate/subrate code is set to permit it, the DS125RT410 will begin searching for CDR lock at the highest allowable VCO divider ratio – that is, at the lowest configured bit rate. At this lowest bit rate, the CTLE boost settings used will come not from the values in register 0x03, and 0x13, but rather from register 0x3a, the fixed CTLE boost setting for lower data rates. This setting will be written into boost setting register 0x03 during the lock search process. This value may be different from the value you set in register 0x03, so, again, it may appear that the DS125RT410 has not accepted the CTLE boost settings you set in registers 0x03 and 0x13. The interactions of the lock and adaptation sequences with the manually-set CTLE boost settings can be difficult to understand. To manually override the CTLE boost under all conditions, perform the following steps. 1. Set the DS125RT410 channel adapt mode to 0 by writing 0x0 to bits 6:5 of channel register 0x31. 2. Set the desired CTLE boost setting in register 0x3a. If the DS125RT410 loses lock and attempts to lock to a lower data rate, it will use this CTLE boost setting. 3. Set the desired CTLE boost setting in register 0x03. This may cause the DS125RT410 to lose lock. 4. If desired, set the CTLE stage 3 limiting bit, bit 2 of register 0x13. If the DS125RT410 loses lock when the CTLE boost settings are set according to the sequence above, the DS125RT410 will try to reacquire lock, but it will not change the CTLE boost settings in order to do so. Overriding the VCO Search Values Register 0x08, bits 4:0, Register 0x09, bit 7, Register 0x0b, bits 4:0, Register 0x36, bits 5:4 and 2:0, and Register 0x2f, bits 7:6 and 5:4 Registers 0x08 and 0x0b contain CAP DAC override values. Normally, when bits 5:4 of register 0x36 are set to 2'b11, then the DS125RT410 performs an initial search to determine the correct CAP DAC setting (coarse VCO tuning) for the selected rate and subrate. The rate and subrate settings (bits 7:6 and 5:4 of register 0x2f) determine the frequency range to be searched, with the 25 MHz reference clock used as the frequency reference for the frequency search. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 27 DS125RT410 SNLS459 – APRIL 2011 www.ti.com The CAP DAC value can be overridden by writing new values to bits 4:0 of register 0x08 (for CAP DAC setting 1) and bits 4:0 of 0x0b (for CAP DAC setting 2). The override bit, bit 7 of register 0x09 must be set for the override CAP DAC values to take effect. Since the valid rate and subrate setting for 10 GbE and 1 GbE applies to multiple data rates, there are two CAP DAC values for this rate. The first is in register 0x08, bits 4:0, and the second is in register 0x0b, bits 4:0. The DS125RT410 will use the CAP DAC value in register 0x08 for the larger divide ratio (8) associated with the selected rate and subrate to try and acquire lock. If it fails to acquire lock, it will use the CAP DAC value in register 0x0b with the smaller divide ratio (higher VCO frequency) associated with the selected rate and subrate (1). It will continue to try to acquire lock in this way until it either succeeds or the override bit (bit 7 of register 0x09) is cleared. Overriding the Output Multiplexer Register 0x09, bit 5, Register 0x14, bits 7:6, and Register 0x1e, bits 7:5 By default, the DS125RT410 output for each channel will be as shown in Table 8. Table 8. Default Output Status Description Input Signal Status Channel Status Output Status Not Present No Signal Detected Muted Present Not Locked Muted Present Locked Retimed Data This default behavior can be modified by register writes. Register 0x1e, bits 7:5, contain the output multiplexer override value. The values of this three-bit field and the corresponding meanings of each are shown in Table 9. Table 9. Output Multiplexer Override Settings Bit Field Value Output Multiplexer Setting Comments 0x7 Mute Default when no signal is present or when the retimer is unlocked 0x6 N/A Invalid Setting 0x5 10 MHz Clock Internal 10 MHz clock Clock frequency may not be precise 0x4 PRBS Generator PRBS Generator must be enabled to output PRBS sequence 0x3 VCO Q-Clock Register 0x09, bit 4, and register 0x1e, bit 0, must be set to enable the VCO Q-Clock 0x2 VCO I-Clock 0x1 Retimed Data 0x0 Raw Data Default when the retimer is locked If the output multiplexer is not overridden, that is, if bit 5 of register 0x09 is not set, then the value in register 0x1e, bits 7:5, controls the output produced when the retimer has a signal at its input, but is not locked to it. The default value for this bit field, 0x7, causes the retimer output to mute when the retimer is not locked to an input signal. Writing a value of 0x0 to this bit field, for example, will cause the retimer to output raw data when it is not locked to its input signal. Setting the override bit, bit 5 of register 0x09, will cause the retimer to output the value selected by the bit field in register 0x1e, bits 7:5, even when the retimer is locked. When no signal is present at the input to the selected channel of the DS125RT410 the signal detect circuitry will power down the channel. This includes the output driver which is therefore muted when no signal is present at the input. If you want to get an output when no signal is present at the input, for example to enable a freerunning PRBS sequence, the first step is to override the signal detect. In order to force the signal detect on, set bit 7 and clear bit 6 of channel register 0x14. Even if there is no signal at the input to the channel, the channel will be enabled. If the channel was disabled before, the current drain from the supply will increase by 100–150 mA depending upon the other channel settings in the device. This increased current drain indicates that the channel is now enabled. 28 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 The second step is to override the output multiplexer setting. This is accomplished by setting bit 5 of register 0x09, the output multiplexer override. Once this bit is set, the value of register 0x1e, bits 7:5 will control the output of the channel. Note that if either retimed or raw data is selected, the output will just be noise. The device output may saturate to a static 1 or 0. If there is no signal, the VCO clock will be free-running. Its frequency will depend upon the divider and CAP DAC settings and it will vary from part to part and over temperature. If the PRBS generator is enabled, the PRBS generator output can be selected. This can either be at a data rate determined by the free-running VCO or at a data rate determined by the input signal, if one is present. If a signal is present at the input and the DS125RT410 can lock to it, the output of the PRBS generator will be synchronous with the input signal, but the bit stream output will be determined by the PRBS generator selection. The 10 MHz clock is always available at the output when the output multiplexer is overridden. The 10 MHz clock is a free-running oscillator in the DS125RT410 and is not synchronous to the input or to anything else in the system. The clock frequency will be approximately 10 MHz, but this will vary from part to part. If there is a signal present at the input, it is not necessary to override the signal detect. Clearing bits 7 and 6 of register 0x14 will return control of the signal detect to the DS125RT410. Normally, when the retimer is locked to a signal at its input, it will output retimed data. However, if desired, the output multiplexer can be overridden in this condition to output raw data. It can also be set to output any of the other signals shown in Table 9. If there is an input signal, and if the DS125RT410 is locked to it, the VCO I-Clock, the VCO Q-Clock, and the output of the PRBS generator, if it is enabled, will be synchronous to the input signal. When a signal is present at the input, it might be desired to output the raw data in order to see the effects of the CTLE without the CDR. It might also be desired to enable the PRBS generator and output this signal, replacing the data content of the input signal with the internally-generated PRBS sequence. Overriding the VCO Divider Selection Register 0x09, bit 2, and Register 0x18, bits 6:4 In normal operation, the DS125RT410 sets its VCO divider to the correct divide ratio, either 1, 2, 4, 8, or 16, depending upon the bit rate of the signal at the channel input. It is possible to override the divider selection. This might be desired if the VCO is set to free-run, for example, to output a signal at a sub-harmonic of the actual VCO frequency. In order to override the VCO divider settings, first set bit 2 of register 0x09. This is the VCO divider override enable. Once this bit is set, the VCO divider setting is controlled by the value in register 0x18, bits 6:4. The valid values for this three-bit field are 0x0 to 0x4. The mapping of the bit field values to the divider ratio is shown in Table 10. Table 10. Divider Ratio Mapping to Register 0x18, Bits 6:4 Bit Field Value Divider Ratio 0 1 1 2 2 4 3 8 4 16 In normal operation, the DS125RT410 will determine the required VCO divider ratio automatically. The most common application for overriding the divider ratio is when the VCO is set to free-run. Normally the divider ratio should not be overridden except in this case. Using the PRBS Generator Register 0x0d, bit 5, Register 0x1e, bit 4, and Register 0x30, bit 3 and bits 1:0 The DS125RT410 includes an internal PRBS generator which can generate standard PRBS-9 and PRBS-31 bit sequences. The PRBS generator can produce a PRBS sequence that is synchronous to the incoming data signal, or it can generate a PRBS sequence using the internal free-running VCO as a clock. Both modes of operation are described in the paragraphs that follow. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 29 DS125RT410 SNLS459 – APRIL 2011 www.ti.com To produce a PRBS sequence that is synchronized to the incoming data signal, the DS125RT410 must be locked to the incoming signal. When this is true, the signal detect is set and the channel is active. In addition, the VCO is locked to the incoming signal The VCO will remain locked to the incoming signal regardless of the state of the output multiplexer. To activate the PRBS generator, first set bit 4 of register 0x1e. This bit enables the PRBS generator digital circuitry. Then reset the PRBS clock by clearing bit 3 of register 0x30. Select either PRBS-9 or PRBS-31 by setting bits 1:0 of register 0x30. Set this bit field to 0x0 for PRBS-9 and to 0x2 for PRBS-31. Then load the PRBS clock by setting bit 3 of register 0x30. Finally, enable the PRBS clock by setting bit 5 of register 0x0d. This sequence of register writes will enable the internal PRBS generator. As described above, to select the PRBS generator as the output for the selected channel, set bit 5 of register 0x09, the output multiplexer override. Then write 0x4 to bits 7:5 of register 0x1e. This selects the PRBS generator for output. For the case described above, the output PRBS sequence will be synchronous to the incoming data. There are two other cases of interest. The first is when there is an input signal but the PRBS sequence should not be synchronous to it. In other words, in this case it is desired that the VCO should free-run. The second case is when there is no input signal, but the PRBS sequence should still be output. Again, in this case, the VCO is freerunning. The register settings for these two cases are almost the same. The only difference is that, if there is no input signal, then the channel will be disabled and powered-down by default. In order to force enable the channel, write a 1 to bit 7 and a 0 to bit 6 of register 0x14. This forces the signal detect to be active and enables the selected channel. The remainder of the register write sequence is designed to disable the phase-locked loop so that the VCO can free run. First write a 1 to bit 3 of register 0x09, then 0x0 to bits 1:0 of register 0x1b. This disables the charge pump for the phase-locked loop. Next write a 1 to bit 2 of register 0x09. This enables the VCO divider override. Then set the VCO divider ratio by writing to register 0x18 as shown in Table 10. For an output frequency of approximately 10.3125 GHz, set the divider ratio to 1 by writing 0x0 to bits 6:4 of register 0x18. Do not clear bit 3 when you write a 1 to bit 2 of register 0x09. Now write a 1 to bit 7 of register 0x09. This enables the VCO CAP DAC override. Write the desired VCO cap count to register 0x08, bits 4:0. The mapping of VCO frequencies to cap count will vary somewhat from part to part. The VCO cap count should be set to 0x08 to yield an output VCO frequency of approximately 10.3125 GHz. Do not clear bits 3 and 2 when you write a 1 to bit 7 of register 0x09. Now write a 1 to bit 6 of register 0x09. This enables the VCO LPF DAC which can generate a VCO control voltage internally to the DS125RT410. Once the LPF DAC is enabled, write the desired value of the LPF DAC output in register 0x1f, bits 4:0. For an output VCO frequency of approximately 10.3125 GHz, set the LPF DAC setting to 0x12. Do not clear the remaining bits of register 0x09 when you write a 1 to bit 6. Now, as above, enable the PRBS generator and set it to the desired bit sequence, then select the output to be the PRBS generator by setting the output multiplexer. Notice that when this entire sequence has been completed, bits 7:2 of register 0x09 will all be set. The default value of register 0x09 is 0x00, so you can clear all the overrides when you are ready to return to normal operation by writing 0x00 to register 0x09. The VCO frequency in free-run will vary somewhat from part to part. In order to determine exact values of the CAP DAC and LPF DAC settings, it will be necessary to directly measure the VCO frequency using some sort of frequency-measurement device such as a frequency counter or a spectrum analyzer. When the VCO is set to free-run mode as above, you can select the VCO I-clock (in-phase clock) to be the output as shown in Table 9. You can measure the frequency of the VCO I-clock while adjusting the CAP DAC and LPF DAC values until the VCO I-clock frequency is acceptable for your application. Then you can once again select the PRBS generator as the output using the output multiplexer selection field. 30 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 Using the Internal Eye Opening Monitor Register 0x11, bits 7:6 and bit 5, Register 0x22, bit 7, Register 0x24, bit 7 and bit 0, Register 0x25, Register 0x26, Register 0x27, Register 0x28, Register 0x2a and Register 0x3e, bit 7 The DS125RT410 includes an internal eye opening monitor. The eye opening monitor is used by the retimer to compute a figure of merit for automatic adaptation of the CTLE. It can also be controlled and queried through the SMBus by a system controller. The eye opening monitor produces error hit counts for settable phase and voltage offsets of the comparator in the retimer. This is similar to the way many Bit Error Rate Test Sets measure eye opening. At each phase and amplitude offset setting, the eye opening monitor determines the nominal bit value (“0” or “1”) using its primary comparator. This is the bit value that is resynchronized to the recovered clock and presented at the output of the DS125RT410. The eye opening monitor also determines the bit value detected by the offset comparator. This information yields an eye contour. Here's how this works. If the offset comparator is offset in voltage by an amount larger than the vertical eye opening, for example, then the offset comparator will always decide that the current bit has a bit value of “0”. When the bit is really a “1”, as determined by the primary comparator, this is considered a bit error. The number of bit errors is counted for a settable interval at each setting of the offset phase and voltage of the offset comparator. These error counts can be read from registers 0x25 and 0x26 for sequential phase and voltage offsets. These error counts for all phase and voltage offsets form a 64 X 64 point array. A surface or contour plot of the error hit count versus phase and voltage offset produces an eye diagram, which can be plotted by external software. The eye opening monitor works in two modes. In the first, only the horizontal and vertical eye openings are measured. The eye opening monitor first sweeps its variable-phase clock through one unit interval with the comparison voltage set to the mid point of the signal. This determines the midpoint of the horizontal eye opening. The eye opening monitor then sets its variable phase clock to the midpoint of the horizontal eye opening and sweeps its comparison voltage. These two measurements determine the horizontal and vertical eye openings. The horizontal eye opening value is read from register 0x27 and the vertical eye opening from register 0x28. Both values are single byte values. The measurement of horizontal and vertical eye opening is very fast. The speed of this measurement makes it useful for determining the adaptation figure of merit. In normal operation, the HEO and VEO are automatically measured periodically to determine whether the DS125RT410 is still in lock. Reading registers 0x27 and 0x28 will yield the most-recently measured HEO and VEO values. In normal operation, the eye monitor circuitry is powered down most of the time to save power. When the eye is to be measured under external control, it must first be enabled by writing a 0 to bit 5 of register 0x11. The default value of this bit is 1, which powers down the eye monitor except when it is powered-up periodically by the CDR state machine and used to test CDR lock. The eye monitor must be powered up to measure the eye under external SMBus control. Bits 7:6 of register 0x11 are also used during eye monitor operation to set the EOM voltage range. This is described below. A single write to register 0x11 can set both bit 5 and bits 7:6 in one operation. Register 0x3e, bit 7, enables horizontal and vertical eye opening measurements as part of the lock validation sequence. When this bit is set, the CDR state machine periodically uses the eye monitor circuitry to measure the horizontal and vertical eye opening. If the eye openings are too small, according to the pre-determined thresholds in register 0x6a, then the CDR state machine declares lock loss and begins the lock acquisition process again. For SMBus acquisition of the internal eye, this lock monitoring function must be disabled. Prior to overriding the EOM by writing a 1 to bit 0 of register 0x24, disable the lock monitoring function by writing a 0 to bit 7 of register 0x3e. Once the eye has been acquired, you can reinstate HEO and VEO lock monitoring by once again writing a 1 to bit 7 of register 0x3e. Under external SMBus control, the eye opening monitor can be programmed to sweep through all its 64 states of phase and voltage offset autonomously. This mode is initiated by setting register 0x24, bit 7, the fast_eom mode bit. Register 0x22, bit 7, the eom_ov bit, should be cleared in this mode. When the fast_eom bit is set, the eye opening monitor operation is initiated by setting bit 0 of register 0x24, which is self-clearing. As soon as this bit is set, the eye opening monitor begins to acquire eye data. The results of the eye opening monitor error counter are stored in register 0x25 and 0x26. In this mode the eye opening monitor results can be obtained by repeated multi-byte reads from register 0x25. It is not necessary to read from register 0x26 for a multi-byte read. As soon as the eight most significant bits are read from register 0x25, the eight least significant bits for the current setting are loaded into register 0x25 and they can be read immediately. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 31 DS125RT410 SNLS459 – APRIL 2011 www.ti.com As soon as the read of the eight most significant bits has been initiated, the DS125RT410 sets its phase and voltage offsets to the next setting and starts its error counter again. The result of this is that the data from the eye opening monitor is available as quickly as it can be read over the SMBus with no further register writes required. The external controller just reads the data from the DS125RT410 over the SMBus as fast as it can. When all the data has been read, the DS125RT410 clears the eom_start bit. If multi-byte reads are not used, meaning that the device is addressed each time a byte is read from it, then it is necessary to read register 0x25 to get the MSB (the eight most significant bits) and register 0x26 to get the LSB (the eight least significant bits) of the current eye monitor measurement. Again, as soon as the read of the MSB has been initiated, the DS125RT410 sets its phase and voltage offsets to the next setting and starts its error counter again. In this mode both registers 0x25 and 0x26 must be read in order to get the eye monitor data. The eye monitor data for the next set of phase and voltage offsets will not be loaded into registers 0x25 and 0x26 until both registers have been read for the current set of phase and voltage offsets. In all eye opening monitor modes, the amount of time during which the eye opening monitor accumulates eye opening data can be set by the value of register 0x2a. In general, the greater this value the longer the accumulation time. When this value is set to its maximum possible value of 0xff, the maximum number of samples acquired at each phase and amplitude offset is approximately 218. Even with this setting, the eye opening monitor values can be read from the SMBus with no delay. The eye opening monitor operation is sufficiently fast that the SMBus read operation cannot outrun it. The eye opening is measured at the input to the data comparator. At this point in the data path, a significant amount of gain has been applied to the signal by the CTLE. In many cases, the vertical eye opening as measured by the EOM will be on the order of 400 to 500 mV peak-to-peak. The secondary comparator, which is used to measure the eye opening, has an adjustable voltage range from ±100 mV to ±400 mV. The EOM voltage range is normally set by the CDR state machine during lock and adaptation, but the range can be overridden by writing a two-bit code to bits 7:6 of register 0x11. The values of this code and the corresponding EOM voltage ranges are shown in Table 11. Table 11. EOM Voltage Range vs. Bits 7:6 of Register 0x11 Value in Bits 7:6 of Register 0x11 EOM Voltage Range (± mV) 0x0 ±100 0x1 ±200 0x2 ±300 0x3 ±400 Note that the voltage ranges shown in Table 11 are the voltage ranges of the signal at the input to the data path comparator. These values are not directly equivalent to any observable voltage measurements at the input to the DS125RT410 . Note also that if the EOM voltage range is set too small the voltage sweep of the secondary comparator may not be sufficient to capture the vertical eye opening. When this happens the eye boundaries will be outside the vertical voltage range of the eye measurement. To summarize, the procedure for reading the eye monitor data from the DS125RT410 is shown below. 1. Select the DS125RT410 channel to be used for the eye monitor measurement by writing the channel select register, register 0xff, with the appropriate value as shown in Table 6. if the correct channel register set is already selected, this step may be skipped. 2. Select the eye monitor voltage range by setting bits 7:6 of register 0x11 according to the values in Table 11. The CDR state machine will have set this range during lock acquisition, but it may be necessary to change it to capture the entire vertical eye extent. 3. Power up the eye monitor circuitry by clearing bit 5 of register 0x11. Normally the eye monitor circuitry is powered up periodically by the CDR state machine. Clearing bit 5 of register 0x11 enables the eye monitor circuitry unconditionally. This bit should be set again once the eye acquisition is complete. Clearing bit 5 and setting bits 7:6 of register 0x11 as desired can be combined into a single register write if desired. 4. Clear bit 7 of register 0x22. This is the eye monitor override bit. It is cleared by default, so you may not need to change it. 5. Set bit 7 of register 0x24. This is the fast eye monitor enable bit. 6. Set bit 1 of register 0x24. This initiates the automatic fast eye monitor measurement. This bit can be set at the same time a bit 7 of register 0x24 if desired. 32 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 7. Read the data array from the DS125RT410. This can be accomplished in two ways. – If you are using multi-byte reads, address the DS125RT410 to read from register 0x25. Continue to read from this register without addressing the device again until you have read all the data desired. The read operation can be interrupted by addressing the device again and then resumed by reading once again from register 0x25. – If you are not using multi-byte reads, then read the MSB for each phase and amplitude offset setting from register 0x25 and the LSB for each setting from register 0x26. In this mode, you address the device each time you want to read a new byte. 8. In either mode, the first four bytes do not contain valid data. These should be discarded. 9. Continue reading eye monitor data until you have read the entire 64 X 64 array. 10. Clear bit 7 of register 0x24. This disables fast eye monitor mode. 11. Set bit 5 of register 0x11. This will return control of the eye monitor circuitry to the CDR state machine. 12. Set bit 7 of register 0x3e. This re-enables the HEO and VEO lock monitoring. Enabling Slow Rise/Fall Time on the Output Driver Register 0x18, bit 2 Normally the rise and fall times of the output driver of the DS125RT410 are set by the slew rate of the output transistors. By default, the output transistors are biased to provide the maximum possible slew rate, and hence the minimum possible rise and fall times. In some applications, slower rise and fall times may be desired. For example, slower rise and fall times may reduce the amplitude of electromagnetic interference (EMI) produced by a system. Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal. Setting this bit will approximately double the nominal rise and fall times of the DS125RT410 output driver. This bit is cleared by default. Inverting the Output Polarity Register 0x1f, bit 7 In some systems, the polarity of the data does not matter. In systems where it does matter, it is sometimes necessary, for the purposes of trace routing, for example, to invert the normal polarities of the data signals. The DS125RT410 can invert the polarity of the data signals by means of a register write. Writing a 1 to bit 7 of register 0x1f inverts the polarity of the output signal for the selected channel. This can provide additional flexibility in system design and board layout. Overriding the Figure of Merit for Adaptation Register 0x2c, bits 5:4, Register 0x31, bits 6:5, Register 0x6b, Register 0x6c, Register 0x6d, and Register 0x6e, bits 7 and 6 The default figure of merit for both the CTLE adaptation in the DS125RT410 is simple. The horizontal and vertical eye openings are measured for each CTLE boost setting. The vertical eye opening is scaled to a constant reference vertical eye opening and the smaller of the horizontal or vertical eye opening is taken as the figure of merit for that set of equalizer settings. The objective is to adapt the equalizer to a point where the horizontal and vertical eye openings are both as large as possible. This usually provides optimum bit error rate performance for most transmission channels. In some systems the adaptation can reach a better setting if only the horizontal or only vertical eye opening is used to compute the figure of merit rather than using both. This will be system-dependent and the user must determine through experiment whether this provides better adaptation in the user's system. For the DS125RT410, the CTLE figure of merit type can be set using register 0x31, bits 4:3. The value of this two-bit field versus the configured figure of merit type is shown in Table 12. Table 12. Figure of Merit Type Setting Register 0x31, bits 4:3 Figure of Merit Type 0x0 Both HEO and VEO are used 0x1 Only HEO is used 0x2 Only VEO is used Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 33 DS125RT410 SNLS459 – APRIL 2011 www.ti.com Table 12. Figure of Merit Type Setting (continued) Register 0x31, bits 4:3 Figure of Merit Type 0x3 Both HEO and VEO are used (default) For some transmission media the adaptation can reach a better setting if a different figure of merit is used. The DS125RT410 includes the capability of adapting based on a configurable figure of merit. The configurable figure of merit is structured as shown in the equation below. FOM = (HEO – b) X a + (VEO – c) x (1 – a) In this equation, HEO is horizontal eye opening, VEO is vertical eye opening, FOM is the figure of merit, and the factors a, b, and c are set using registers 0x6b, 0x6c, and 0x6d respectively. In order to use the configurable figure of merit, the enable bits must be set. To use the configurable figure of merit for the CTLE adaptation, set bit 7 of register 0x6e, the en_new_fom_ctle bit. Setting the Rate and Subrate for Lock Acquisition Register 0x2f, bits 7:6 and 5:4 The rate and subrate settings, which constrain the data rate search in order to reduce lock time, can be set using channel register 0x2f. Bits 7:6 are RATE<1:0>, and bits 5:4 are SUBRATE<1:0>. These four bits form a hex digit which matches the codes in Table 1. Setting the Adaptation/Lock Mode Register 0x31, bits 6:5, Register 0x3e, bit 7, and Register 0x6a There are 2 adaptation modes available in the DS125RT410. • Mode 0: The user is responsible for setting the CTLE values. This mode is used if the transmission channel response is fixed. • Mode 1: Only the CTLE is adapted to equalize the transmission channel. This mode is primarily used for smoothly-varying high-loss transmission channels such as cables and simple PCB traces. Bits 6:5 of register 0x31 determine the adaptation mode to be used. The mapping of these register bits to the adaptation algorithm is shown in Table 13. Table 13. DS125RT410 Adaptation Algorithm Settings Register 0x31, Bit 6 adapt_mode[1] Register 0x31, Bit 5 adapt_mode[0] Adapt Mode Setting <1:0> Adaptation Algorithm 0 0 00 No Adaptation 0 1 01 Adapt CTLE Until Optimum (Default) By default the DS125RT410 requires that the equalized internal eye exhibit horizontal and vertical eye openings greater than a pre-set minimum in order to declare a successful lock. The minimum values are set in register 0x6a. The DS125RT410 continuously monitors the horizontal and vertical eye openings while it is in lock. If the eye opening falls below the threshold set in register 0x6a, the DS125RT410 will declare a loss of lock. Initiating Adaptation Register 0x24, bit 2, and Register 0x2f, bit 0 When the DS125RT410 becomes unlocked, it will automatically try to acquire lock. If an adaptation mode is selected using bits 6:5 in register 0x31, the DS125RT410 will also try to adapt its CTLE. Adaptation can also be initiated by the user. CTLE adaptation can be initiated by setting and then clearing register 0x2f, bit 0. Setting the Reference Enable Mode Register 0x36, bits 5:4 34 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 The reference clock mode is set by a two-bit field, register 0x36, bits 5:4. This field should always be set to a value of 3 or 2'b11. A 25 MHz reference clock signal must be provided on the reference in pin (pin 19). The use of the reference clock in the DS125RT410 is explained below. First, the reference clock allows the DS125RT410 to calibrate its VCO frequency at power-up and upon reset. This enables the DS125RT410 to determine the optimum coarse VCO tuning setting a-priori, which makes phase lock much faster. The DS125RT410 is not required to tune through the available coarse VCO tuning settings as it tries to acquire lock to an input signal. It can select the correct setting immediately. Second, if the DS125RT410 loses lock for some reason and the VCO drifts from its phase-locked frequency, the DS125RT410 can detect this very quickly using the reference clock. Detecting an out-of-lock condition quickly allows the DS125RT410 to raise an interrupt indicating that it has lost lock quickly, which the system controller can then service to correct the problem quickly. Finally, some data signals with large jitter spurs in their frequency spectra can cause the DS125RT410 to false lock. This occurs when the data pattern exhibits strong discrete frequency components in its frequency spectrum, or when the data pattern has a lot of periodic jitter imposed on it. If you look at such a signal in the frequency domain using a spectrum analyzer, it will clearly show “spurs” close in to the fundamental data rate frequency. These spurs can cause the DS125RT410 to false lock. Using the 25 MHz reference clock, the DS125RT410 can detect when it is locked to a jitter spur. When this happens, the DS125RT410 will re-initiate the adaptation and lock sequence until it locks to the correct data rate. This provides immunity to false lock conditions. Overriding the CTLE Settings Used for CTLE Adaptation Register 0x2c, bits 3:0, Register 0x2f, bit 3, Register 0x39, bits 4:0, and Registers 0x50-0x5f The CTLE adaptation algorithm operates by setting the CTLE boost stage controls to a set of pre-determined boost settings, each of which provides progressively more high-frequency boost. At each stage in the adaptation process, the DS125RT410 attempts to phase lock to the equalized signal. If the phase lock succeeds, the DS125RT410 measures the horizontal and vertical eye openings using the internal eye monitor circuit. The DS125RT410 computes a figure of merit for the eye opening and compares it to the previous best value of the figure of merit. While the figure of merit continues to improve, the DS125RT410 continues to try additional values of the CTLE boost setting until the figure of merit ceases to improve and begins to degrade. When the figure of merit starts to degrade, the DS125RT410 still continues to try additional CTLE settings for a pre-determined trial count called the “look-beyond” count, and if no improvement in the figure of merit results, it resets the CTLE boost values to those that produced the best figure of merit. The resulting CTLE boost values are then stored in register 0x03. The “look-beyond” count is configured by the value in register 0x2c, bits 3:0. The value is 0x2 by default. The set of boost values used as candidate values during CTLE adaptation are stored as bit fields in registers 0x40-0x5f. The default values for these settings are shown in Table 14. These values may be overridden by setting the corresponding register values over the SMBus. If these values are overridden, then the next time the CTLE adaptation is performed the set of CTLE boost values stored in these registers will be used for the adaptation. Resetting the channel registers by setting bit 2 of channel register 0x00 will reset the CTLE boost settings to their defaults. So will power-cycling the DS125RT410. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 35 DS125RT410 SNLS459 – APRIL 2011 www.ti.com Table 14. CTLE Settings for Adaptation Register (Hex) Bits 7:6 (CTLE Stage 0) Bits 5:4 (CTLE Stage 1) Bits 3:2 (CTLE Stage 2) Bits 1:0 (CTLE Stage 3) CTLE Boost String CTLE Adaptation Index 40 0 0 0 0 0000 0 41 0 0 0 1 0001 1 42 0 0 1 0 0010 2 43 0 1 0 0 0100 3 44 1 0 0 0 1000 4 45 0 0 2 0 0020 5 46 0 0 0 2 0002 6 47 2 0 0 0 2000 7 48 0 0 0 3 0003 8 49 0 0 3 0 0030 9 4A 0 3 0 0 0300 10 4B 1 0 0 1 1001 11 4C 1 1 0 0 1100 12 4D 3 0 0 0 3000 13 4E 1 2 0 0 1200 14 4F 2 1 0 0 2100 15 50 2 0 2 0 2020 16 51 2 0 0 2 2002 17 52 2 2 0 0 2200 18 53 1 0 1 2 1012 19 54 1 1 0 2 1102 20 55 2 0 3 0 2030 21 56 2 3 0 0 2300 22 57 3 0 2 0 3020 23 58 1 1 1 3 1113 24 59 1 1 3 1 1131 25 5A 1 2 2 1 1221 26 5B 1 3 1 1 1311 27 5C 3 1 1 1 3111 28 5D 2 1 2 1 2121 29 5E 2 1 1 2 2112 30 5F 2 2 1 1 2211 31 As an alternative to, or in conjunction with, writing the CTLE boost setting registers 0x40 through 0x5f, it is possible to set the starting CTLE boost setting index. To override the default setting, which is 0, set bit 3 of register 0x2f. When this bit is set, the starting index for adaptation comes from register 0x39, bits 4:0. This is the index into the CTLE settings table in registers 0x40 through 0x5f. When this starting index is 0, which is the default, CTLE adaptation starts at the first setting in the table, the one in register 0x40, and continues until the optimum FOM is reached. Setting the Output Differential Voltage Register 0x2d, bits 2:0 There are eight levels of output differential voltage available in the DS125RT410, from 0.6 V to 1.3 V in 0.1 V increments. The values drv_sel_vod[2:0] in bits 2:0 of register 0x2d set the output VOD. The available VOD settings and the corresponding values of this bit field are shown in Table 15. 36 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 DS125RT410 www.ti.com SNLS459 – APRIL 2011 Table 15. VOD Settings Bit 2, drv_sel_vod[2] Bit 1, drv_sel_vod[1] Bit 0, drv_sel_vod[0] Selected VOD (V, peak-to-peak, differential) 0 0 0 0.6 0 0 1 0.7 0 1 0 0.8 0 1 1 0.9 1 0 0 1.0 1 0 1 1.1 1 1 0 1.2 1 1 1 1.3 Setting the Output De-emphasis Setting Register 0x15, bits 2:0 and bit 6 Fifteen output de-emphasis settings are available in the DS125RT410, ranging from 0 dB to -15 dB. The deemphasis values come from register 0x15, bits 2:0, which make up the bit field dvr_dem<2:0>, and register 0x15, bit 6, which is the third de-emphasis setting bit. The available driver de-emphasis settings and the mapping to these bits are shown in Table 16. Table 16. Driver De-Emphasis Settings Register 0x15, Bit 2, dvr_dem[2] Register 0x15, Bit 1, drv_dem[1] Register 15, Bit 0, drv_dem[0] Register 0x15, Bit 6, drv_dem_range De-emphasis Setting (dB) 0 0 0 X 0.0 0 0 1 1 -1.5 0 0 1 0 -2.0 0 1 0 1 -3.5 0 1 0 0 -4.2 0 1 1 1 -5.0 0 1 1 0 -6.0 1 0 0 1 -6.5 1 0 0 0 -7.2 1 0 1 1 -8.0 1 0 1 0 -9.0 1 1 0 1 -9.5 1 1 0 0 -11.0 1 1 1 1 -13.0 1 1 1 0 -15.0 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: DS125RT410 37 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DS125RT410SQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 125RT410 DS125RT410SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 125RT410 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS125RT410SQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 DS125RT410SQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS125RT410SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS125RT410SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 Pack Materials-Page 2 MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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