PRELIMINARY DATA SHEET 128MB DDR SDRAM S.O. DIMM EBD13UB6ALS (16M words × 64 bits, 2 Banks) Description Features The EBD13UB6ALS is 16M words × 64 bits, 2 banks Double Data Rate (DDR) SDRAM module, mounted 8 pieces of 128M bits DDR SDRAM (EDD1216ALTA) sealed in TSOP package. Read and write operations are performed at the cross points of the CLK and the /CLK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 200-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board. • 200-pin socket type package (dual lead out) Outline: 67.6mm (Length) × 31.75mm (Height) × 3.80mm (Thickness) Lead pitch: 0.6mm • 2.5V power supply • SSTL-2 interface for all inputs and outputs • Clock frequency: 133MHz/100MHz (max.) • Data inputs and outputs are synchronized with DQS • 4 banks can operate simultaneously and independently (Component) • Burst read/write operation • Programmable burst length: 2, 4, 8 Burst read stop capability • Programmable burst sequence Sequential Interleave • Start addressing capability Even and Odd • Programmable /CAS latency (CL): 2, 2.5 • 4096 refresh cycles: 15.6µs (4096/64ms) • 2 variations of refresh Auto refresh Self refresh Document No. E0219E10 (Ver. 1.0) Date Published October 2001 (K) Printed in Japan URL: http://www.elpida.com C Elpida Memory, Inc. 2001 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. EBD13UB6ALS Ordering Information Part number Clock frequency MHz (max.) /CAS latency Package Contact pad Mounted devices EBD13UB6ALS-7A EBD13UB6ALS-75 EBD13UB6ALS-1A 133 133 100 2.0 2.5 2.0 200-pin S.O. DIMM Gold EDD1216ALTA Pin Configurations Front side 1 pin 39 pin 41 pin 199 pin 2 pin 40 pin 42 pin 200 pin Back side Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VREF 51 VSS 2 VREF 52 VSS 3 VSS 53 DQ19 4 VSS 54 DQ23 5 DQ0 55 DQ24 6 DQ4 56 DQ28 7 DQ1 57 VDD 8 DQ5 58 VDD 9 VDD 59 DQ25 10 VDD 60 DQ29 11 DQS0 61 DQS3 12 DM0 62 DM3 13 DQ2 63 VSS 14 DQ6 64 VSS 15 VSS 65 DQ26 16 VSS 66 DQ30 17 DQ3 67 DQ27 18 DQ7 68 DQ31 19 DQ8 69 VDD 20 DQ12 70 VDD 21 VDD 71 NC 22 VDD 72 NC 23 DQ9 73 NC 24 DQ13 74 NC 25 DQS1 75 VSS 26 DM1 76 VSS 27 VSS 77 NC 28 VSS 78 NC 29 DQ10 79 NC 30 DQ14 80 NC 31 DQ11 81 VDD 32 DQ15 82 VDD 33 VDD 83 NC 34 VDD 84 NC 35 CLK0 85 NC 36 VDD 86 NC 37 /CLK0 87 VSS 38 VSS 88 VSS 39 VSS 89 CLK2 40 VSS 90 VSS 41 DQ16 91 /CLK2 42 DQ20 92 VDD 43 DQ17 93 VDD 44 DQ21 94 VDD 45 VDD 95 NC 46 VDD 96 CKE0 47 DQS2 97 NC 48 DM2 98 NC 49 DQ18 99 NC 50 DQ22 100 A11 Preliminary Data Sheet E0219E10 (Ver. 1.0) 2 EBD13UB6ALS Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 101 A9 151 DQ42 102 A8 152 DQ46 103 VSS 153 DQ43 104 VSS 154 DQ47 105 A7 155 VDD 106 A6 156 VDD 107 A5 157 VDD 108 A4 158 /CLK1 109 A3 159 VSS 110 A2 160 CLK1 111 A1 161 VSS 112 A0 162 VSS 113 VDD 163 DQ48 114 VDD 164 DQ52 115 A10/AP 165 DQ49 116 BA1 166 DQ53 117 BA0 167 VDD 118 /RAS 168 VDD 119 /WE 169 DQS6 120 /CAS 170 DM6 121 /CS0 171 DQ50 122 /CS1 172 DQ54 123 NC 173 VSS 124 NC 174 VSS 125 VSS 175 DQ51 126 VSS 176 DQ55 127 DQ32 177 DQ56 128 DQ36 178 DQ60 129 DQ33 179 VDD 130 DQ37 180 VDD 131 VDD 181 DQ57 132 VDD 182 DQ61 133 DQS4 183 DQS7 134 DM4 184 DM7 135 DQ34 185 VSS 136 DQ38 186 VSS 137 VSS 187 DQ58 138 VSS 188 DQ62 139 DQ35 189 DQ59 140 DQ39 190 DQ63 141 DQ40 191 VDD 142 DQ44 192 VDD 143 VDD 193 SDA 144 VDD 194 SA0 145 DQ41 195 SCL 146 DQ45 196 SA1 147 DQS5 197 VDDSPD 148 DM5 198 SA2 149 VSS 199 VDDID 150 VSS 200 NC Preliminary Data Sheet E0219E10 (Ver. 1.0) 3 EBD13UB6ALS Pin Description Pin name Function A0 to A11 Address input Row address Column address BA0, BA1 Bank select address A0 to A11 A0 to A8 DQ0 to DQ63 Data input/output /RAS Row address strobe command /CAS Column address strobe command /WE Write enable /CS0, /CS1 Chip select CKE0, CKE1 Clock enable CLK0 to CLK2 Clock input /CLK0 to /CLK2 Differential clock input DQS0 to DQS7 Input and output data strobe DM0 to DM7 Input mask SCL Clock input for serial PD SDA Data input/output for serial PD SA0 to SA2 Serial address input VDD Power for internal circuit VDDSPD Power for serial EEPROM VREF Input reference voltage VSS Ground VDDID VDD indentication flag NC No connection Preliminary Data Sheet E0219E10 (Ver. 1.0) 4 EBD13UB6ALS Serial PD Matrix Byte No. 0 1 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 80H 128 bytes 0 0 0 0 1 0 0 0 08H 256 bytes 0 0 0 0 0 1 1 1 07H DDR SDRAM 2 Memory type 3 Number of row address 0 0 0 0 1 1 0 0 0CH 12 4 Number of column address 0 0 0 0 1 0 0 1 09H 9 5 Number of DIMM banks 0 0 0 0 0 0 1 0 02H 2 6 Module data width 0 1 0 0 0 0 0 0 40H 64 7 Module data width continuation 0 0 0 0 0 0 0 0 00H 0 8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H SSTL2 9 DDR SDRAM cycle time, CL = 2.5 -7A 0 1 1 1 0 1 0 1 75H 7.5ns -75 0 1 1 1 0 1 0 1 75H 7.5ns -1A 1 0 1 0 0 0 0 0 A0H 10ns 0 1 1 1 0 1 0 1 75H 0.75ns -75 0 1 1 1 0 1 0 1 75H 0.75ns -1A 1 0 0 0 0 0 0 0 80H 0.8ns DIMM configuration type 0 0 0 0 0 0 0 0 00H None. 12 Refresh rate/type 1 0 0 0 0 0 0 0 80H Norm 13 Primary SDRAM width 0 0 0 1 0 0 0 0 10H × 16 Error checking SDRAM width 0 0 0 0 0 0 0 0 00H None. 0 0 0 0 0 0 0 1 01H 1 CLK 0 0 0 0 1 1 1 0 0EH 2,4,8 0 0 0 0 0 1 0 0 04H 4 0 0 0 0 1 1 0 0 0CH 2, 2.5 0 0 0 0 0 0 0 1 01H 0 0 0 0 0 0 0 1 0 02H 1 SDRAM module attributes 0 0 1 0 0 0 0 0 20H Differential Clock 22 SDRAM device attributes: General 0 0 0 0 0 0 0 0 00H VDD ± 0.2V 23 Minimum clock cycle time at CL = 2 -7A 0 1 1 1 0 1 0 1 75H 7.5ns -75 1 0 1 0 0 0 0 0 A0H 10ns -1A 1 0 1 0 0 0 0 0 A0H 10ns Maximum data access time (tAC) from 1 clock at CL = 2 -7A 0 0 0 0 0 0 0 80H 0.80ns 10 11 14 15 16 17 18 19 20 21 24 SDRAM access from clock (tAC) -7A SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency -75 0 1 1 1 0 1 0 1 75H 0.75ns -1A 1 0 0 0 0 0 0 0 80H 0.8ns 0 0 0 0 0 0 0 0 00H 25 to 26 Preliminary Data Sheet E0219E10 (Ver. 1.0) 5 EBD13UB6ALS Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 27 Minimum row precharge time (tRP) -7A 0 1 0 1 0 0 0 0 50H 20ns -75 0 1 0 1 0 0 0 0 50H 20ns -1A 0 1 0 1 0 0 0 0 50H 20ns 0 0 1 1 1 1 0 0 3CH 15ns -75 0 0 1 1 1 1 0 0 3CH 15ns -1A 0 0 1 1 1 1 0 0 3CH 15ns 0 1 0 1 0 0 0 0 50H 20ns -75 0 1 0 1 0 0 0 0 50H 20ns -1A 0 1 0 1 0 0 0 0 50H 20ns 0 0 1 0 1 1 0 1 2DH 45ns -75 0 0 1 0 1 1 0 1 2DH 45ns -1A 0 0 1 1 0 0 1 0 32H 50ns 28 29 30 Minimum row active to row active delay (tRRD) -7A Minimum /RAS to /CAS delay (tRCD) -7A Minimum active to precharge time (tRAS) -7A 31 Module bank density 0 0 0 1 0 0 0 0 10H 64M bytes 32 Address and command setup time before clock (tIS) -7A 1 0 0 1 0 0 0 0 90H 0.9ns -75 1 0 0 1 0 0 0 0 90H 0.9ns -1A 1 0 1 1 0 0 0 0 B0H 1.1ns Address and command hold time after 1 clock (tIH) -7A 0 0 1 0 0 0 0 90H 0.9ns 33 34 35 -75 1 0 0 1 0 0 0 0 90H 0.9ns -1A 1 0 1 1 0 0 0 0 B0H 1.1ns 0 1 0 1 0 0 0 0 50H 0.5ns -75 0 1 0 1 0 0 0 0 50H 0.5ns -1A 0 1 1 0 0 0 0 0 60H 0.6ns 0 1 0 1 0 0 0 0 50H 0.5ns -75 0 1 0 1 0 0 0 0 50H 0.5ns -1A 0 1 1 0 0 0 0 0 60H 0.6ns Data input setup time before clock (tDS) -7A Data input hold time after clock (tDH) -7A 36 to 61 Superset information 0 0 0 0 0 0 0 0 00H 62 SPD Revision 0 0 0 0 0 0 0 0 00H 63 Checksum for bytes 0 to 62 -7A 0 1 1 1 0 1 0 0 74H -75 1 0 0 1 0 1 0 0 94H -1A 0 0 1 1 1 0 1 0 3AH Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH 65 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H 72 Manufacturing location 73 to 90 Manufacturer’s part number 91 to 92 Revision code 93 to 94 Manufacturing date 64 Preliminary Data Sheet E0219E10 (Ver. 1.0) 6 Elpida Memory EBD13UB6ALS Byte No. Function described Bit7 95 to 98 Module serial number 99 to 127 Manufacture specific data Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments Block Diagram /CS1 /CS0 RS DQS0 LDQS /CS LDQS RS /CS DQS4 LDM DM0 8 LDM 8 I/O0 to I/O7 RS DQS1 RS DM1 8 DM4 RS DQ0 to DQ7 UDQS I/O0 to I/O7 D0 UDM UDQS LDQS D4 DQS5 UDM DM5 RS DQS3 RS DM3 8 /CS LDQS I/O0 to I/O7 D2 D6 UDQS UDM UDM I/O8 to I/O15 I/O8 to I/O15 RS /CS DQS6 /CS LDQS LDQS /CS RS LDM LDM I/O0 to I/O7 I/O0 to I/O7 DM6 8 UDQS D1 UDQS LDM LDM I/O0 to I/O7 I/O0 to I/O7 RS DQ48 to DQ55 RS D5 DQS7 D3 UDQS UDQS D7 RS UDM UDM DM7 RS DQ24 to DQ31 I/O0 to I/O7 RS DQ40 to DQ47 I/O8 to I/O15 RS DQ16 to DQ23 LDM UDQS RS 8 LDM RS 8 RS DM2 /CS RS I/O8 to I/O15 DQS2 LDQS RS DQ32 to DQ39 RS DQ8 to DQ15 /CS LDQS RS RS 8 I/O8 to I/O15 DQ56 to DQ63 I/O8 to I/O15 UDM UDM I/O8 to I/O15 I/O8 to I/O15 RS * D0 to D7 : EDD1216ALTA U0 : 2k bits EEPROM Rs : 22Ω Serial PD BA0 to BA1 SDRAMs (D0 to D7) A0 to A11 SDRAMs (D0 to D7) SCL SCL /RAS SDRAMs (D0 to D7) SA0 A0 /CAS SDRAMs (D0 to D7) SA1 A1 /WE SDRAMs (D0 to D7) CKE0 SA2 SDRAMs (D0 to D3) A2 CKE1 SDA SDA U0 SDRAMs (D4 to D7) VDDSPD SPD VREF SDRAMs (D0 to D7) VDD SDRAMs (D0 to D7), VDD and VDDQ VSS SDRAMs (D0 to D7), SPD CLK0 /CLK0 SDRAMs (D0, D1, D4, D5) CLK1 /CLK1 SDRAMs (D2, D3, D6, D7) CLK2 10 pF /CLK2 Notes : VDDID Open 1. DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. VDDID strap connections: (for memory device VDD, VDDQ) Strap out (open): VDD = VDDQ Strap in (closed): VDD ≠ VDDQ 2. The SDA pull-up registor is reguired due to the open-drain/open-collector output. 3. The SCL pull-up registor is recommended, because of the normal SCL lime inactive "high" state. Preliminary Data Sheet E0219E10 (Ver. 1.0) 7 EBD13UB6ALS Logical Clock Net Structure 4DRAM loads DRAM1 DRAM2 120Ω DIMM connector DRAM3 DRAM4 Pin Functions (1) CLK, /CLK (input pin): The CLK and the /CLK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CLK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CLK and the /CLK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CLK and the /CLK. /CS (input pin): When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A11 (input pins): Row address (AX0 to AX11) is determined by the A0 to the A11 level at the cross point of the CLK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY8) is loaded via the A0 to the A8 at the cross point of the CLK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected. CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. The CKE level must be kept for 1 CLK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the CLK rising edge and the VREF level with proper setup time tIS, at the next CLK rising edge CKE level must be kept with proper hold time tIH. Preliminary Data Sheet E0219E10 (Ver. 1.0) 8 EBD13UB6ALS Pin Functions (2) DQ (input and output pins): Data are input to and output from these pins. DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input). DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and VREF VDD (power supply pins): 2.5V is applied. VDDSPD (power supply pin): 2.5V is applied (For serial EEPROM). VSS (power supply pin): Ground is connected. Detailed Operation Part, AC Characteristics and Timing Waveforms Refer to the EDD1204ALTA, EDD1208ALTA, EDD1216ALTA Series datasheet (E0136E). Preliminary Data Sheet E0219E10 (Ver. 1.0) 9 EBD13UB6ALS Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 1ms and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to VSS VT –0.5 to +3.6 V Supply voltage relative to VSS VDD –0.5 to +3.6 V Short circuit output current IO 50 mA Power dissipation PD 8 W Operating temperature TA 0 to +70 °C Storage temperature Tstg –55 to +125 °C Caution Note Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC Operating Conditions (TA = 0 to +70°C) Parameter Symbol Supply voltage VDD 2.3 2.5 VSS 0 0 Input reference voltage VREF 0.49 × VDD — 0.51 × VDD V Termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V 1 DC Input high voltage VIH VREF + 0.18 — VDD + 0.3 V 1, 2 DC Input low voltage VIL –0.3 — VREF – 0.18 V 1, 3 DC Input signal voltage VIN (dc) –0.3 — VDD+ 0.3 V 4 DC differential input voltage VSWING (dc) 0.36 — VDD + 0.6 V 5 Notes: 1. 2. 3. 4. 5. min. Typ max. Unit Notes 2.7 V 1 0 V All parameters are referred to VSS, when measured. VIH is allowed to exceed VDD up to 4.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns. VIN (dc) specifies the allowable dc execution of each differential input. VSWING (dc) specifies the input differential voltage required for switching. Preliminary Data Sheet E0219E10 (Ver. 1.0) 10 1 EBD13UB6ALS DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol Operating current (ACTV-PRE) ICC0 Operating current (ACTV-READICC1 PRE) Idle power down standby current ICC2P Idle standby current ICC2N Active power down standby current ICC3P Active standby current ICC3N Operating current (Burst read operation) ICC4R Operating current (Burst write operation) ICC4W Auto refresh current ICC5 Self refresh current ICC6 Notes. 1. 2. 3. 4. 5. 6. 7. Grade -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A -7A -75 -1A max. Unit Test condition Notes TBD mA CKE ≥ VIH, tRC = tRC (min.) 1, 2, 5 TBD mA CKE ≥ VIH, BL = 2, CL = 3.5, tRC = tRC (min.) 1, 2, 5 TBD mA CKE ≤ VIL 4 TBD mA CKE ≥ VIH, /CS ≥ VIH 4 TBD mA CKE ≤ VIL 3 TBD mA CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.) 3 TBD mA CKE ≥ VIH, BL = 2, CL = 3.5 1, 2, 5, 6 TBD mA CKE ≥ VIH, BL = 2, CL = 3.5 1, 2, 5, 6 TBD mA tRFC = tRFC (min.) Input ≤ VIL or ≥ VIH TBD mA Input ≥ VDD – 0.2V Input ≤ 0.2V. These ICC data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. The ICC data on this table are measured with regard to tCK = tCK (min.) in general. DC Characteristics 2 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol min. max. Unit Test condition Input leakage current ILI –16 16 µA VDD ≥ VIN ≥ VSS Output leakage current ILO –10 10 µA VDD ≥ VOUT ≥ VSS Output high current IOH –15.2 — mA VOUT = 1.95V Output low current IOL 15.2 — mA VOUT = 0.35V Preliminary Data Sheet E0219E10 (Ver. 1.0) 11 Notes EBD13UB6ALS Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V) Parameter Symbol Pins Input capacitance CI1 Address, /RAS, /CAS, /WE, TBD /CS, CKE max. Unit pF Input capacitance CI2 CLK, /CLK TBD pF Data and DQS input/output capacitance CO DQ, DQS TBD pF Notes AC Characteristics (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V) Synchronous Characteristics -7A Parameter Clock cycle time CL = 2.5 -75 -1A Symbol min. max. min. max. min. max. Unit tCK 7.5 12 7.5 12 10 12 ns 7.5 12 10 12 10 12 ns CL = 2 CLK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CLK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQ output access time from CLK, /CLK tAC –0.75 0.75 –0.75 0.75 –0.8 0.8 ns DQS output access time from CLK, /CLK tDQSCK –0.75 0.75 –0.75 0.75 –0.8 0.8 ns — 0.5 — 0.5 — 0.6 ns DQS-DQ skew (for DQS and all DQ signals) tDQSQA — 0.5 — 0.5 — 0.6 ns Data out low-impedance time from CLK, /CLKtLZ –0.75 0.75 –0.75 0.75 –0.8 0.8 ns Data out high-impedance time from CLK, /CLK tHZ –0.75 0.75 –0.75 0.75 –0.8 0.8 ns Half clock period tHP tCH, tCL — tCH, tCL — tCH, tCL — Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS-DQ skew (for DQS and associated DQ tDQSQ signals) ns DQ/DQS output hold time from DQS tQH tHP – 0.75 — tHP – 0.75 — tHP – 1 — ns DQ and DM input setup time tDS 0.5 — 0.5 — 0.6 — ns DQ and DM input hold time tDH 0.5 — 0.5 — 0.6 — ns 1.75 — 1.75 — 2 — ns DQ and DM input pulse width (for each input) tDIPW Write preamble setup time tWPRES 0 — 0 — 0 — ns Write preamble tWPRE 0.25 — 0.25 — 0.25 — tCK Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS input high pulse width tDQSH 0.35 — 0.35 — 0.35 — tCK DQS input low pulse width tDQSL 0.35 — 0.35 — 0.35 — tCK DQS falling edge to CLK setup time tDSS 0.2 — 0.2 — 0.2 — tCK DQS falling edge hold time from CLK tDSH 0.2 — 0.2 — 0.2 — tCK Address and control input setup time tIS 0.9 — 0.9 — 1.1 — ns Address and control input hold time tIH 0.9 — 0.9 — 1.1 — ns Address and control input pulse width tIPW 2.2 — 2.2 — 2.5 — ns Internal write to read command delay tWTR 1 — 1 — 1 — tCK Preliminary Data Sheet E0219E10 (Ver. 1.0) 12 Note EBD13UB6ALS Synchronous Characteristics Example tCK 7.5 ns 10 ns Symbol min. max. min. max. Unit tCH 3.4 4.1 4.5 5.5 ns tCL 3.4 4.1 4.5 5.5 ns tRPRE 6.75 8.25 9 11 ns tRPST 3 4.5 4 6 ns tWPRE 0.25 — 2.5 — ns tWPST 3 4.5 4 6 ns tDQSS 5.6 9.4 7.5 12.5 ns tDQSH 2.63 — 3.5 — ns tDQSL 2.63 — 3.5 — ns tDSS 1.5 — 2 — ns tDSH 1.5 — 2 — ns tWTR 7.5 — 10 — ns Asynchronous Characteristics -7A Parameter -75 -1A Symbol min. max. min. max. min. max. Unit tRC 65 — 65 — 70 — ns tRFC 75 — 75 — 80 — ns ACT to PRE command period tRAS 45 120,000 45 120,000 50 120,000 ns PRE to ACT command period tRP 20 — 20 — 20 — ns ACT to READ/WRITE delay tRCD 20 — 20 — 20 — ns ACT(one) to ACT(another) command period tRRD 15 — 15 — 15 — ns Write recovery time tWR 2 — 2 — 2 — CLK Auto precharge write recovery time + precharge time tDAL TBD — TBD — TBD — ns Mode register set command cycle time tMRD 15 — 15 — 15 — ns Exit self refresh to command tXSNR 75 — 75 — 80 — ns Average periodic Refresh interval tREF1 — 15.6 — 15.6 — 15.6 µs ACT to REF/ACT command period (operation) REF to REF/ACT command period (refresh) Preliminary Data Sheet E0219E10 (Ver. 1.0) 13 EBD13UB6ALS Physical Outline Unit: mm 63.60 11.55 18.45 3.80 max. (DATUM -A-) 4x Full R 4.00 199 1 6.00 20.0 31.75 Component area (Front) 11.40 ± 0.05 2.15 A 47.40 ± 0.05 B 2.45 4.20 ± 0.05 1.00 ± 0.10 67.60 ± 0.15 4.20 ± 0.05 1.50 11.40 ± 0.05 2.45 2.15 47.40 ± 0.05 2 200 R0.50 ± 0.20 R0.50 ± 0.20 2x φ 1.80 4.00 ± 0.10 Component area (Back) (DATUM -A-) 2.00 min. Detail A Detail B (DATUM -A-) 4.00 ± 0.10 2.55 min. 0.25 max. FULL R 0.60 0.45 ± 0.05 1.80 1.00 ± 0.10 Preliminary Data Sheet E0219E10 (Ver. 1.0) 14 EBD13UB6ALS CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0107 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Preliminary Data Sheet E0219E10 (Ver. 1.0) 15 EBD13UB6ALS The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107 Preliminary Data Sheet E0219E10 (Ver. 1.0) 16