PRELIMINARY DATA SHEET 512MB Registered DDR SDRAM DIMM EBD51RD8ABFA (64M words × 72 bits, 1 Rank) Features The EBD51RD8ABFA is a 64M words × 72 bits, 1 rank Double Data Rate (DDR) SDRAM Module, mounting 9 pieces of DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board. • 184-pin socket type dual in line memory module (DIMM) PCB height: 30.48mm Lead pitch: 1.27mm • 2.5V power supply • Data rate: 333Mbps/266Mbps (max.) • 2.5 V (SSTL_2 compatible) I/O • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver • Data inputs and outputs are synchronized with DQS • 4 internal banks for concurrent operation (Component) • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Data mask (DM) for write data • Auto precharge option for each burst access • Programmable burst length: 2, 4, 8 • Programmable /CAS latency (CL): 2, 2.5 • Refresh cycles: (8192 refresh cycles /64ms) 7.8µs maximum average periodic refresh interval • 2 variations of refresh Auto refresh Self refresh • 1 piece of PLL clock driver, 2 pieces of register drivers and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD) L EO Description t uc od Pr Document No. E0376E10 (Ver. 1.0) Date Published April 2003 (K) Japan URL: http://www.elpida.com This product became EOL in March, 2004. Elpida Memory,Inc. 2003 EBD51RD8ABFA Ordering Information Part number Data rate Mbps (max.) Component JEDEC speed bin*1 (CL-tRCD-tRP) Package Contact pad Mounted devices EBD51RD8ABFA-6B 333 DDR333B (2.5-3-3) 184-pin DIMM Gold EDD5108ABTA-6B EBD51RD8ABFA-7A 266 DDR266A (2-3-3) EDD5108ABTA-6B, -7A DDR266B (2.5-3-3) EDD5108ABTA-6B, -7A, -7B EBD51RD8ABFA-7B Notes: 1. Module /CAS latency = component CL + 1. Pin Configurations EO Front side 1 pin 52 pin 53 pin 93 pin 92 pin 144 pin 145 pin 184 pin Back side Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VREF 47 DQS8 93 VSS 139 VSS 2 DQ0 48 A0 94 DQ4 140 DM8/DQS17 3 VSS 49 CB2 95 DQ5 141 A10 L Pin No. DQ1 50 VSS 96 VDD 142 CB6 5 DQS0 51 CB3 97 DM0/DQS9 143 VDD 6 DQ2 52 BA1 98 DQ6 144 CB7 7 VDD 53 8 DQ3 54 9 NC 55 Pr 4 DQ32 99 DQ7 145 VSS VDD 100 VSS 146 DQ36 DQ33 101 NC 147 DQ37 /RESET 56 11 VSS 57 DQS4 102 NC 148 VDD DQ34 103 NC 149 DM4/DQS13 12 DQ8 58 VSS 104 VDD 150 DQ38 13 DQ9 59 BA0 14 DQS1 60 DQ35 15 VDD 61 DQ40 16 NC 62 VDD 17 NC 63 /WE 18 VSS 64 DQ41 od 10 105 DQ12 151 DQ39 106 DQ13 152 VSS 107 DM1/DQS10 153 DQ44 108 VDD 154 /RAS 109 DQ14 155 DQ45 110 DQ15 156 VDD DQ10 65 /CAS 111 NC 20 DQ11 66 VSS 112 VDD 21 CKE0 67 DQS5 113 NC 22 VDD 68 DQ42 114 23 DQ16 69 DQ43 115 24 DQ17 70 VDD 116 VSS t uc 19 157 /CS0 158 NC 159 DM5/DQS14 DQ20 160 VSS A12 161 DQ46 162 DQ47 25 DQS2 71 NC 117 DQ21 163 NC 26 VSS 72 DQ48 118 A11 164 VDD 27 A9 73 DQ49 119 DM2/DQS11 165 DQ52 Preliminary Data Sheet E0376E10 (Ver. 1.0) 2 EBD51RD8ABFA Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 28 DQ18 74 VSS 120 VDD 166 DQ53 29 A7 75 NC 121 DQ22 167 NC 30 VDD 76 NC 122 A8 168 VDD 31 DQ19 77 VDD 123 DQ23 169 DM6/DQS15 32 A5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 A6 171 DQ55 34 VSS 80 DQ51 126 DQ28 172 VDD DQ25 81 VSS 127 DQ29 173 NC 36 DQS3 82 VDDID 128 VDD 174 DQ60 37 A4 83 DQ56 129 DM3/DQS12 175 DQ61 38 VDD 84 DQ57 130 A3 176 VSS 39 DQ26 85 VDD 131 DQ30 177 DM7/DQS16 40 DQ27 86 DQS7 132 VSS 178 DQ62 41 A2 87 DQ58 133 DQ31 179 DQ63 42 VSS 88 DQ59 134 CB4 180 VDD 43 A1 89 VSS 135 CB5 181 SA0 44 CB0 90 NC 136 VDD 182 SA1 45 CB1 91 SDA 137 CK0 183 SA2 46 L EO 35 VDD SCL 138 /CK0 184 VDDSPD 92 t uc od Pr Preliminary Data Sheet E0376E10 (Ver. 1.0) 3 EBD51RD8ABFA Pin Description Function A0 to A12 Address input Row address Column address BA0, BA1 Bank select address DQ0 to DQ63 Data input/output CB0 to CB7 Check bit (Data input/output) /RAS Row address strobe command /CAS Column address strobe command /WE Write enable /CS0 Chip select EO Pin name A0 to A12 A0 to A9, A11 CKE0 Clock enable CK0 Clock input /CK0 Differential clock input DQS0 to DQS8 Input and output data strobe DM0 to DM8/DQS9 to DQS17 Input mask SCL Clock input for serial PD SDA VDD VDDSPD VREF VDDID /RESET NC Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground Pr VSS Data input/output for serial PD L SA0 to SA2 VDD identification flag Reset pin (forces register inputs low) No connection t uc od Preliminary Data Sheet E0376E10 (Ver. 1.0) 4 EBD51RD8ABFA 1 Serial PD Matrix* Byte No. 0 1 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 80H 128 0 0 0 0 1 0 0 0 08H 256 byte 2 Memory type 0 0 0 0 0 1 1 1 07H SDRAM DDR 3 Number of row address 0 0 0 0 1 1 0 1 0DH 13 Number of column address 0 0 0 0 1 0 1 1 0BH 11 5 Number of DIMM ranks 0 0 0 0 0 0 0 1 01H 1 6 Module data width 0 1 0 0 1 0 0 0 48H 72 bits 7 Module data width continuation 0 0 0 0 0 0 0 0 00H 0 (+) 8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H SSTL 2.5V 9 DDR SDRAM cycle time, CL = X -6B 0 1 1 0 0 0 0 0 60H CL = 2.5*3 0 1 1 1 0 1 0 1 75H 0 1 1 1 0 0 0 0 70H 0.70ns*3 0 1 1 1 0 1 0 1 75H 0.75ns*3 EO 4 -7A, -7B 10 SDRAM access from clock (tAC) -6B -7A, -7B DIMM configuration type 0 0 0 0 0 0 1 0 02H ECC 12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.8 µs Self refresh 13 Primary SDRAM width 0 0 0 0 1 0 0 0 08H ×8 14 Error checking SDRAM width 0 0 0 0 1 0 0 0 08H ×8 0 0 0 0 0 0 0 1 01H 1 CLK 15 17 18 20 0 0 0 0 1 1 1 0 0EH 2, 4, 8 0 0 0 0 0 1 0 0 04H 4 0 0 0 0 1 1 0 0 0CH 2, 2.5 0 0 0 0 0 0 0 1 01H 0 0 0 0 0 0 0 1 0 02H 1 1 0 0 1 1 0 26H Registered 0 0 0 0 0 0 C0H ± 0.2V 1 1 0 1 0 1 75H 1 0 0 0 0 0 A0H 21 SDRAM module attributes 0 0 22 SDRAM device attributes: General 1 1 23 Minimum clock cycle time at CLX - 0.5 0 -6B, -7A 1 -7B 1 0 Maximum data access time (tAC) from 0 clock at CLX - 0.5 -6B 1 1 1 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 -7A, -7B 25 26 27 Minimum clock cycle time at CLX - 1 Maximum data access time (tAC) from 0 clock at CLX - 1 Minimum row precharge time (tRP) 0 -6B -7A, -7B 0 Preliminary Data Sheet E0376E10 (Ver. 1.0) 5 CL = 2*3 t uc 24 od 19 SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency Pr 16 L 11 0 0 70H 0.70ns*3 0 1 75H 0.75ns*3 0 0 00H 0 0 00H 0 0 48H 18ns 0 0 50H 20ns EBD51RD8ABFA Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 28 Minimum row active to row active delay (tRRD) -6B 0 0 1 1 0 0 0 0 30H 12ns 0 0 1 1 1 1 0 0 3CH 15ns 29 Minimum /RAS to /CAS delay (tRCD) -6B 0 1 0 0 1 0 0 0 48H 18ns 0 1 0 1 0 0 0 0 50H 20ns 30 Minimum active to precharge time (tRAS) -6B 0 0 1 0 1 0 1 0 2AH 42ns 0 0 1 0 1 1 0 1 2DH 45ns -7A, -7B -7A, -7B -7A, -7B Module rank density 1 0 0 0 0 0 0 0 80H 32 Address and command setup time before clock (tIS) -6B 0 1 1 1 0 1 0 1 75H 0.75ns*3 1 0 0 1 0 0 0 0 90H 0.9ns*3 Address and command hold time after 0 clock (tIH) -6B 1 1 1 0 1 0 1 75H 0.75ns*3 1 0 0 1 0 0 0 0 90H 0.9ns*3 0 1 0 0 0 1 0 1 45H 0.45ns*3 0 1 0 1 0 0 0 0 50H 0.5ns*3 0 1 0 0 0 1 0 1 45H 0.45ns*3 0 1 0 1 0 0 0 0 50H 0.5ns*3 0 0 0 0 0 0 0 0 00H Future use 0 0 1 1 1 1 0 0 3CH 60ns*3 0 1 0 0 0 0 0 1 41H 65ns*3 0 1 0 0 1 0 0 0 48H 72ns*3 0 1 EO 31 1 rank 512MB -7A, -7B 33 -7A, -7B Data input setup time before clock (tDS) -6B L 34 -7A, -7B 35 Data input hold time after clock (tDH) -6B 36 to 40 Superset information 41 Active command period (tRC) -6B -7A, -7B 42 Auto refresh to active/ Auto refresh command cycle (tRFC) -6B -7A, -7B od Pr -7A, -7B 0 0 1 0 1 1 4BH 75ns*3 1 1 0 0 0 0 30H 12ns*3 1 0 1 1 0 1 2DH 0.45ns*3 1 1 0 0 1 0 32H 0.5ns*3 0 1 0 1 0 1 55H 0.55ns*3 SDRAM tCK cycle max. (tCK max.) 0 0 44 Dout to DQS skew -6B 0 0 0 0 0 1 0 1 1 1 0 1 -7A, -7B 45 Data hold skew (tQHS) -6B -7A, -7B 46 to 61 Superset information 0 0 0 0 0 0 62 SPD revision 0 0 0 0 0 0 63 Checksum for bytes 0 to 62 -6B 0 1 0 1 1 0 -7A 0 0 0 1 0 0 -7B 0 0 1 1 1 0 64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 67 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 Preliminary Data Sheet E0376E10 (Ver. 1.0) 6 0 1 75H 0.75ns*3 0 0 00H Future use 0 0 00H Initial 0 1 59H 89 0 0 10H 16 59 t uc 43 1 1 3BH 1 1 7FH 1 0 FEH 0 0 00H Elpida Memory EBD51RD8ABFA Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 72 Manufacturing location × × × × × × × × ×× *2 (ASCII-8bit code) 73 Module part number 0 1 0 0 0 1 0 1 45H E 74 Module part number 0 1 0 0 0 0 1 0 42H B Module part number 0 1 0 0 0 1 0 0 44H D 76 Module part number 0 0 1 1 0 1 0 1 35H 5 77 Module part number 0 0 1 1 0 0 0 1 31H 1 78 Module part number 0 1 0 1 0 0 1 0 52H R 79 Module part number 0 1 0 0 0 1 0 0 44H D 80 Module part number 0 0 1 1 1 0 0 0 38H 8 81 Module part number 0 1 0 0 0 0 0 1 41H A 82 Module part number 0 1 0 0 0 0 1 0 42H B 83 Module part number 0 1 0 0 0 1 1 0 46H F 84 Module part number 0 1 0 0 0 0 0 1 41H A 85 Module part number 0 0 1 0 1 1 0 1 2DH — 86 Module part number -6B 0 0 1 1 0 1 1 0 36H 6 0 0 1 1 0 1 1 1 37H 7 0 1 0 0 0 0 0 1 41H A EO 75 -7A, -7B Module part number -7A 0 1 0 0 0 0 1 0 42H B 88 to 90 Module part number 0 0 1 0 0 0 0 0 20H (Space) 91 Revision code 0 0 1 1 0 0 0 0 30H Initial 92 Revision code 0 0 1 0 0 0 0 0 20H L 87 -6B, -7B Pr 93 Manufacturing date 94 Manufacturing date 95 to 98 Module serial number 99 to 127 Manufacturer specific data × × × × × × × × ×× × × × × × × × × ×× (Space) Year code (HEX) Week code (HEX) *2 t uc od Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High” 2. Bytes 95 through 98 are assembly serial number. 3. These specifications are defined based on component specification, not module. Preliminary Data Sheet E0376E10 (Ver. 1.0) 7 EBD51RD8ABFA Block Diagram /RCS0 /CS RS DM0/DQS9 DM RS DQS0 RS DQS 8 RS DQ0 to DQ7 DQS4 D0 /CS EO DQ8 to DQ15 DQS5 D1 /CS DQ16 to DQ23 DQS6 D2 L 8 RS DQ24 to DQ31 RS DQ48 to DQ55 /CS I/O0 to I/O7 /CS RS DM7/DQS16 DM DM RS DQS3 D6 DQS 8 I/O0 to I/O7 RS DM3/DQS12 /CS DM RS DQS RS I/O0 to I/O7 RS DM6/DQS15 RS 8 RS DQ40 to DQ47 DM DQS2 D5 DQS 8 I/O0 to I/O7 RS DM2/DQS11 /CS DM RS DQS RS I/O0 to I/O7 RS DM5/DQS14 RS 8 RS DQ32 to DQ39 DM DQS1 D4 DQS 8 I/O0 to I/O7 RS DM1/DQS10 /CS RS DM4/DQS13 DM RS DQS DQS7 D3 I/O0 to I/O7 D7 DQS 8 RS DQ56 to DQ63 I/O0 to I/O7 /CS Pr RS DM8/DQS17 DM RS DQS8 DQS 8 RS CB0 to CB7 /CS0 A0 to A12 /RAS /CAS CKE0 /WE RS RS RS RS RS RS RS /RCS0 -> /CS: SDRAMs D0 to D8 R E G I S T E R PCK /PCK RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D8 RA0 to RA12 -> A0 to A12: SDRAMs D0 to D8 /RRAS -> /RAS: SDRAMs D0 to D8 Serial PD /RCAS -> /CAS: SDRAMs D0 to D8 RCKE0 -> CKE: SDRAMs D0 to D8 SCL SCL A0 VDD D0 to D8 VREF D0 to D8 SDA A1 A2 SA0 SA1 SA2 Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. t uc D0 to D8 SDA U0 /RWE -> /WE: SDRAMs D0 to D8 /RESET VSS * D0 to D8: 512M bits DDR SDRAM U0: 2k bits EEPROM RS: 22Ω PLL: CDCV857 Register: SSTV16857 od BA0 to BA1 D8 I/O0 to I/O7 VDDID open CK0, /CK0 PLL* Note: Wire per Clock loading table/Wiring diagrams. Preliminary Data Sheet E0376E10 (Ver. 1.0) 8 EBD51RD8ABFA Differential Clock Net Wiring (CK0, /CK0) 0ns (nominal) SDRAM PLL 120Ω OUT1 Capacitance 120Ω CK0 EO IN 240Ω /CK0 120Ω Register1 (Typically two registers per DIMM) OUT'N' C Feedback 240Ω Register2 L t uc od Pr Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register will be set to 0 ns (nominal). 2. Input, output and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. 4. Termination resistors for feedback path clocks are located after the pins of the PLL. 5. SDRAM clock pair inputs have a parallel capacitor equal to one-half nominal SDRAM input clock load. Preliminary Data Sheet E0376E10 (Ver. 1.0) 9 EBD51RD8ABFA Electrical Specifications • All voltages are referenced to VSS (GND). Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to VSS VT –1.0 to +3.6 V Supply voltage relative to VSS VDD –1.0 to +3.6 V Short circuit output current IOS 50 mA Power dissipation PD 9 W Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg –55 to +125 °C Note 1 EO Note: 1. DDR SDRAM component specification Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC Operating Conditions (TA = 0 to +70°C) (DDR SDRAM component Specification) L Parameter Symbol Supply voltage Min Typ Max Unit Notes 1 2.3 2.5 2.7 V 0 0 0 V VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V Termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V Input high voltage VIH (DC) VREF + 0.15 — VDDQ + 0.3 V 2 Input low voltage VIL (DC) –0.3 — VREF – 0.15 V 3 VIN (DC) –0.3 — VDDQ + 0.3 V 4 VIX (DC) 0.5 × VDDQ − 0.2V 0.5 × VDDQ 0.5 × VDDQ + 0.2V V VID (DC) 0.36 Input reference voltage Notes: 1. 2. 3. 4. 5. 6. od Input voltage level, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input differential voltage, CK and /CK inputs Pr VDD,VDDQ VSS — VDDQ + 0.6 V 5, 6 t uc VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns. VIN (DC) specifies the allowable DC execution of each differential input. VID (DC) specifies the input differential voltage required for switching. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement. Preliminary Data Sheet E0376E10 (Ver. 1.0) 10 EBD51RD8ABFA DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol Operating current (ACTV-PRE) IDD0 Operating current (ACTV-READ-PRE) IDD1 Grade max. -6B -7A, -7B -6B -7A, -7B 1740 1605 2010 1830 Idle power down standby current IDD2P -6B -7A, -7B Unit mA mA 417 mA 750 705 mA Floating idle standby current IDD2F Quiet idle standby current IDD2Q 615 mA Active power down standby current IDD3P 570 mA EO Active standby current -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B IDD3N Operating current (Burst read operation) Operating current (Burst write operation) IDD4R IDD4W IDD5 Self refresh current IDD6 Operating current (4 banks interleaving) IDD7A L Auto refresh current 1020 930 2280 2010 2280 2010 3000 2820 -6B -7A, -7B mA mA mA mA 426 mA 4260 3720 mA Test condition CKE ≥ VIH, tRC = tRC (min.) CKE ≥ VIH, BL = 4, CL = 3.5, tRC = tRC (min.) CKE ≤ VIL CKE ≥ VIH, /CS ≥ VIH, DQ, DQS, DM = VREF CKE ≥ VIH, /CS ≥ VIH, DQ, DQS, DM = VREF CKE ≤ VIL CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.) CKE ≥ VIH, BL = 2, CL = 3.5 CKE ≥ VIH, BL = 2, CL = 3.5 tRFC = tRFC (min.), Input ≤ VIL or ≥ VIH Input ≥ VDD – 0.2 V Input ≤ 0.2 V BL = 4 Notes 1, 2, 9 1, 2, 5 4 4, 5 4, 10 3 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6 5, 6, 7 od Pr Notes. 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one cycle. 6. DQ, DM and DQS transition twice per one cycle. 7. 4 banks active. Only one bank is running at tRC = tRC (min.) 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general. 9. Command/Address transition once every two clock cycles. 10. Command/Address stable at ≥ VIH or ≤ VIL. DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) (DDR SDRAM component Specification) Symbol min. max. Unit Test condition Input leakage current ILI –2 2 µA VDD ≥ VIN ≥ VSS Output leakage current ILO –5 5 µA VDDQ ≥ VOUT ≥ VSS Output high current IOH –15.2 — mA VOUT = 1.95V Output low current IOL 15.2 — mA Preliminary Data Sheet E0376E10 (Ver. 1.0) 11 Notes t uc Parameter VOUT = 0.35V EBD51RD8ABFA Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V) Parameter Symbol Pins max. Unit Notes Input capacitance CI1 Address, /RAS, /CAS, /WE, /CS, CKE 10 pF 1, 3 Input capacitance CI2 CK, /CK 20 pF 1, 3 Data and DQS input/output capacitance CO DQ, DQS, CB, DM 15 pF 1, 2, 3 Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V. 2. Dout circuits are disabled. 3. This parameter is sampled and not 100% tested. EO AC Characteristics (TA = 0 to +70°°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) (DDR SDRAM component Specification) -6B -7A -7B Symbol min. max min. max min. max Unit Notes Clock cycle time (CL = 2) tCK 7.5 12 7.5 12 10 12 ns (CL = 2.5) tCK 6 12 7.5 12 7.5 12 ns CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tHP min (tCH, tCL) — min (tCH, tCL) — min (tCH, tCL) — tCK tAC –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 2, 11 DQS output access time from CK, /CK tDQSCK –0.6 0.6 –0.75 0.75 –0.75 0.75 ns 2, 11 DQS to DQ skew 0.45 — 0.5 — 0.5 ns 3 CK half period L Parameter DQ output access time from CK, /CK Data hold skew factor tDQSQ — tQH tHP – tQHS — tHP – tQHS — tHP – tQHS — ns tQHS — 0.55 — 0.75 — 0.75 ns –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 5, 11 –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 6, 11 Data-out high-impedance time from tHZ CK, /CK Data-out low-impedance time from CK, tLZ /CK Read preamble tRPRE 0.9 Read postamble tRPST 0.4 DQ and DM input setup time tDS 0.45 DQ and DM input hold time tDH 0.45 DQ and DM input pulse width tDIPW 1.75 tWPRES 0 Write preamble tWPRE 0.25 Write postamble tWPST Write command to first DQS latching transition DQS falling edge to CK setup time 1.1 0.9 1.1 0.9 1.1 tCK 0.6 0.4 0.6 0.4 0.6 tCK — 0.5 — 0.5 — ns 8 — 0.5 — 0.5 — ns 8 — 1.75 — 1.75 — ns 7 — 0 — 0 — ns — 0.25 — 0.25 — tCK 0.4 0.6 0.4 0.6 0.4 0.6 tCK tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK tDSS 0.2 — 0.2 — 0.2 — tCK t uc Write preamble setup time od Pr DQ/DQS output hold time from DQS 10 DQS falling edge hold time from CK tDSH 0.2 — 0.2 — 0.2 — tCK DQS input high pulse width tDQSH 0.35 — 0.35 — 0.35 — tCK DQS input low pulse width tDQSL 0.35 — 0.35 — 0.35 — tCK 9 Address and control input setup time tIS 0.75 — 0.9 — 0.9 — ns 8 Address and control input hold time tIH 0.75 — 0.9 — 0.9 — ns 8 Preliminary Data Sheet E0376E10 (Ver. 1.0) 12 EBD51RD8ABFA -6B -7A -7B Parameter Symbol min. max min. max min. max Unit Notes Address and control input pulse width tIPW 2.2 — 2.2 — 2.2 — ns Mode register set command cycle time tMRD 2 — 2 — 2 — tCK Active to Precharge command period 42 120000 45 120000 45 120000 ns 60 — 65 — 65 — ns 72 — 75 — 75 — ns tRAS Active to Active/Auto refresh command tRC period Auto refresh to Active/Auto refresh tRFC command period Active to Read/Write delay tRCD 18 — 20 — 20 — ns Precharge to active command period tRP 18 — 20 — 20 — ns Active to auto precharge delay tRAP tRCD min. — tRCD min. — tRCD min. — ns tRRD 12 — 15 — 15 — ns Write recovery time tWR 15 — 15 — 15 — ns Auto precharge write recovery and precharge time tDAL (tWR/tCK)+ — (tRP/tCK) (tWR/tCK)+ — (tRP/tCK) (tWR/tCK)+ — (tRP/tCK) tCK Internal write to Read command delay tWTR 1 — 1 — 1 — tCK Average periodic refresh interval — 7.8 — 7.8 — 7.8 µs EO Active to active command period tREF 7 13 L Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions, refer to the corresponding component data sheet. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT. 5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK. 12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than 0.4V/400 cycle. 13. tDAL = (tWR/tCK)+(tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3) tDAL = 5 clocks t uc od Pr Preliminary Data Sheet E0376E10 (Ver. 1.0) 13 EBD51RD8ABFA Timing Parameter Measured in Clock Cycle for Registered DIMM Number of clock cycle tCK 6ns Parameter 7.5ns Symbol min. tWPD 4 + BL/2 3 + BL/2 tCK tRPD BL/2 BL/2 tCK tWRD 2 + BL/2 2 + BL/2 tCK tBSTW — 2 tCK (CL = 3.5) tBSTW 3 3 tCK Burst stop command to DQ High-Z (CL = 3) tBSTZ — — 3 3 tCK (CL = 3.5) tBSTZ 3.5 3.5 3.5 3.5 tCK Read command to write command delay (to output all data) (CL = 3) tRWD — — 2 + BL/2 tCK (CL = 3.5) tRWD 3 + BL/2 3 + BL/2 tCK Pre-charge command to High-Z (CL = 3) tHZP — — 3 3 tCK (CL = 3.5) tHZP 3.5 3.5 3.5 3.5 tCK Write command to data in latency tWCD 2 2 2 2 tCK Write recovery tWR 2 1 tCK tMRD 2 2 tCK Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CL = 3) L EO — Pr Register set command to active or register set command max. min. max. Unit Self refresh exit to non-read command tSNR 12 10 tCK Self refresh exit to read command tSRD 200 200 tCK tPDEN 1 tPDEX 1 Power down entry Power down exit to command input 1 1 1 1 tCK tCK t uc od Preliminary Data Sheet E0376E10 (Ver. 1.0) 14 EBD51RD8ABFA Pin Functions CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. EO /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is loaded via the A0 to the A9 and the A11 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. L A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. [Bank Select Signal Table] Bank 0 BA0 BA1 L L H Bank 2 L Bank 3 H Remark: H: VIH. L: VIL. L od Bank 1 Pr BA0, BA1 (input pin) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) H H t uc CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH. DQ, CB (input and output pins) Data are input to and output from these pins. DQS (input and output pin) DQS provide the read data strobes (as output) and the write data strobes (as input). Preliminary Data Sheet E0376E10 (Ver. 1.0) 15 EBD51RD8ABFA DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and VREF VDD (power supply pins) 2.5V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 2.5V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. EO /RESET (input pin) LVCMOS reset input. When /RESET is low, all registers are reset and all outputs are low. Detailed Operation Part and Timing Waveforms Refer to the EDD5104AB, EDD5108AB datasheet (E0237E). DIMM /CAS latency = component CL + 1 for registered type. L t uc od Pr Preliminary Data Sheet E0376E10 (Ver. 1.0) 16 EBD51RD8ABFA Physical Outline Unit: mm 133.35 ± 0.15 128.95 4.80 4.00 min (DATUM -A-) (64.48) 2.30 Component area (Front) 1 92 B EO 64.77 A 1.27 ± 0.10 49.53 R 2.00 3.00 min Detail A Detail B (DATUM -A-) 1.27 typ 0.20 ± 0.15 6.62 2.175 R 0.90 1.00 ± 0.05 3.80 Pr 2.50 ± 0.20 30.48 ± 0.15 Component area (Back) 17.80 184 L 4.00 ± 0.10 93 10.00 2 – φ 2.50 ± 0.10 6.35 1.80 ± 0.10 od Note: Tolerance on all dimensions ± 0.13 unless otherwise specified. ECA-TS2-0058-01 t uc Preliminary Data Sheet E0376E10 (Ver. 1.0) 17 EBD51RD8ABFA CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 EO NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES L Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES 3 od Pr No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. STATUS BEFORE INITIALIZATION OF MOS DEVICES t uc Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Preliminary Data Sheet E0376E10 (Ver. 1.0) 18 EBD51RD8ABFA The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. EO [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. L [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. M01E0107 t uc od Pr If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Preliminary Data Sheet E0376E10 (Ver. 1.0) 19